阅读说明：本技术 一种基于描述符表的参数加载方法 (Parameter loading method based on descriptor table ) 是由 李世平 周小龙 何国强 曹舟 于 2020-06-17 设计创作，主要内容包括：本发明克服了现有DBF系统参数加载技术中定制化、专用化等缺点,提供了一种基于描述符表的参数加载方法,通过软件定义描述符表序列,实现分布式参数的灵活加载,大幅提升了通用性和可扩展性,通过FPGA或芯片均可实现,能够广泛应用于各型雷达的DBF系统。(The invention overcomes the defects of customization, specialization and the like in the existing DBF system parameter loading technology, provides a descriptor table-based parameter loading method, realizes flexible loading of distributed parameters by defining descriptor table sequences through software, greatly improves the universality and expandability, can be realized through both an FPGA (field programmable gate array) or a chip, and can be widely applied to DBF systems of various radars.)

1. A parameter loading method based on descriptor tables is characterized by comprising the following steps: storing the parameters in an RAM, uniformly addressing and hanging the parameters on a bus, and adjusting the quantity of the RAM according to actual use requirements; adopting DMA (direct memory access) to move numbers, and reading parameters in the RAM through a bus; controlling DMA (direct memory access) moving number by adopting a loading state machine, analyzing DMA moving number information by adopting a descriptor table, and adjusting a control instruction of the loading state machine through the descriptor table; and establishing virtual storage, defining DMA (direct memory access) number moving operation by loading a state machine and a descriptor table, and mapping external data transmission into on-chip RAM read-write operation.

2. The descriptor table-based parameter loading method of claim 1, wherein the external data transmission comprises: the interface mode is selected by an interface mode control signal, and a starting mark is sent to the loading state machine by the controller; in the external memory interface mode, parameters are automatically loaded when the system is powered on and reset, whether the system is started or not is controlled by the system in the running process, and the input RAM read operation is converted into the external memory read operation of a corresponding address according to time sequence through a read conversion logic; in the packet transmission interface mode, receiving a parameter loading data packet, analyzing to obtain effective packet data, storing the effective packet data in the RAM, and dynamically loading specified parameters.

3. The descriptor table-based parameter loading method according to claim 2, wherein the parameter loading comprises: power-on loading and dynamic loading; the method comprises the steps that a corresponding external memory interface mode is powered on and loaded, a complete descriptor table sequence and corresponding parameters are stored in an external memory, after power-on reset, a virtual memory actively requires a loading state machine to start, all the parameters are loaded from the external memory, and the descriptor table sequence is stored in sequence from the first address of the external memory; and dynamically loading a corresponding packet transmission interface mode, inputting a parameter loading data packet during system operation, caching in virtual storage, dynamically loading and updating the specified parameter, and sequentially storing descriptor table sequences from the first address of the RAM.

4. The descriptor table-based parameter loading method of claim 1, wherein the descriptor table parsing comprises: obtaining a starting mark by an RAM (random access memory) read controller, and analyzing a current descriptor table; if the result is invalid, the loading is not needed, and if the result is the last one, the loading is finished; otherwise, continuing loading, and writing the source address, the target address and the data length into corresponding registers in the system.

5. The descriptor table-based parameter loading method of claim 4, wherein the descriptor table comprises: the total 12 bytes, the 0 th byte to the 3 rd byte are the table head, the Bit [31] is 1 to indicate that the current table is invalid, the Bit [30] is 1 to indicate that the current table is the last one, the Bit [29:16] is reserved, and the Bit [15:0] indicates the total number of bytes to be carried; bytes 4 to 7 indicate the source address of the move number, and bytes 8 to 11 indicate the destination address of the move number.

6. The descriptor table-based parameter loading method of claim 4, wherein the loading state machine comprises: receiving a parameter loading start flag, setting an interface mode, extracting and analyzing a descriptor table from virtual storage, controlling DMA (direct memory access) moving number if the current descriptor table is valid, accessing the virtual storage according to a source address, reading data with corresponding length, and writing the data into an RAM (random access memory) corresponding to a target address through a bus; if the move is finished, judging whether the current descriptor table is the last one, if so, finishing the parameter loading, and if not, continuously extracting and analyzing the descriptor table.

7. The descriptor table-based parameter loading method according to any one of claims 1 to 6, comprising: 595 RAMs are set, each RAM is 8KB, an external memory adopts FLASH, packet transmission adopts high-speed SerDes, the RAM, the FLASH and a virtual memory are uniformly addressed, the address bit width is 32 bits, wherein 0xF000_0000 to 0xFFFF _ FFFF is the address space of the FLASH, and 0xE000_0000 to 0xEFFF _ FFFF is the address space of the high-speed SerDes data packet in the virtual memory; the bus uses APB bus, uses 8-port APB bus decoder, cascade plug-in RAM, realizes the doubling expansion of port.

Technical Field

The invention belongs to the technical field of data processing, and particularly relates to a virtual storage reading technology.

Background

The active phased array radar adopting the digital beam forming DBF technology has the characteristics of self-adaptive interference suppression, simultaneous multi-beam forming and the like, and is a research hotspot in the field of radar array signal processing. Currently, the DBF technology has been developed from the research stage of concept and key technology to the research stage of practical system application, and is a necessary choice for a new generation of high performance radar systems.

Let N be the array element number of the phased array radar, M be the number of beams synthesized, B_jFor the j-th beam synthesized, S_iFor inputting data of the ith array element, w_ijThe weighting coefficients corresponding to the ith array element and the jth beam are obtained, and the basic principle of the DBF is as follows:

the direction and shape of the beam can be controlled by changing the weighting coefficients. In practical applications, the weighting coefficients are usually calculated from the orientation, the amplitude weights and various correction coefficients.

A typical coefficient calculation formula is:

wherein a is_ij△ a being amplitude weights_iAnd phi_iI △ phi, an amplitude correction weight and a phase correction weight, respectively_BjThe phase difference in the array pointed to by the jth beam corresponding to the ith array element is other than i △_BjBesides dynamic calculation according to the direction, other parameters are quasi-static parameters and need to be loaded before DBF calculation. The data amount of the parameters usually reaches MB magnitude, and when broadband application is considered in the future, more parameters such as channel equalization coefficients and delay filter coefficients are increased. In order to improve the parallel computing capability of the DBF, all parameters need to be stored in blocks, and two modes of power-on loading and dynamic loading in operation are supported.

The large-data-volume distributed parameter loading method is usually designed and developed individually according to the specific requirements of each product, presents the characteristics of customization and specialization, and has no universality and flexibility. With the development of radar towards broadband, the requirement on the parallel computing capability of the DBF is higher and higher, and the FPGA and the chip become mainstream technical means for realizing the DBF. A set of special parameter loading RTL logic is customized and developed for each product, a large amount of labor and time are consumed, the requirements of the products cannot be met gradually, and a universal and flexible parameter loading method is needed to be researched, so that the method is suitable for the application requirements of different products and supports future parameter expansion.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a parameter loading method based on a descriptor table.

The method comprises the steps of loading large-data-volume distributed DBF system parameters through a descriptor table sequence which can be defined by software, supporting flexible expansion of various characteristics such as parameter types, parameter sizes and parameter blocking modes, and supporting modes such as power-on loading and dynamic loading of specified parameters during operation.

Firstly, a loading state machine informs a descriptor table analysis module, reads and analyzes a first descriptor table from a base address, if the descriptor table is electrified and loaded, the base address is an external storage first address, and if the descriptor table is dynamically loaded, the base address is an RAM first address in virtual storage; then, the DMA number moving module is informed to complete one-time data moving according to the source address, the target address and the data length obtained by analysis; and finally, judging whether the current descriptor table is the last one, if so, finishing the parameter loading, and if not, continuously reading the next descriptor table until all the descriptor tables are processed.

Storing the parameters in an RAM, uniformly addressing, hanging the parameters on a bus, and adjusting the quantity of the RAM according to actual use requirements; reading parameters in the RAM by adopting DMA (direct memory access) moving number through a bus; controlling DMA (direct memory access) moving number by adopting a loading state machine, analyzing DMA moving number information by adopting a descriptor table, and adjusting a control instruction of the loading state machine through the descriptor table; and establishing virtual storage, defining DMA (direct memory access) number moving operation by loading a state machine and a descriptor table, and mapping external data transmission into on-chip RAM read-write operation.

The external data transmission comprises a packet transmission interface mode and an external memory interface mode, an interface form control signal is input into the controller, the interface mode is selected, and the controller sends a starting mark to the loading state machine; in a packet transmission interface mode, receiving a parameter loading data packet, analyzing to obtain effective packet data, storing the effective packet data in an RAM (random access memory), and dynamically loading specified parameters; in the external memory interface mode, the system is powered on to reset and automatically load parameters, whether the system is started or not is controlled by the system in the running process, and the input RAM read operation is converted into the external memory read operation of the corresponding address according to the time sequence through the read conversion logic.

The descriptor table analysis comprises the steps that the RAM read controller acquires a starting mark and analyzes the current descriptor table; if the result is invalid, the loading is not needed, and if the result is the last one, the loading is finished; otherwise, continuing loading, and writing the source address, the target address and the data length into corresponding registers in the system.

12 bytes of descriptor table, 0 to 3 bytes are table head, Bit [31] is 1 to indicate that the current table is invalid, Bit [30] is 1 to indicate that the current table is the last one, Bit [29:16] is reserved, Bit [15:0] indicates the total number of bytes of transport; bytes 4 to 7 indicate the source address of the move number, and bytes 8 to 11 indicate the destination address of the move number.

The loading state machine receives the parameter loading starting mark, sets an interface mode, extracts and analyzes the descriptor table from the virtual storage, controls the DMA transfer number if the current descriptor table is effective, accesses the virtual storage according to a source address, reads data with corresponding length, and writes the data into the RAM corresponding to a target address through a bus; if the move is finished, judging whether the current descriptor table is the last one, if so, finishing the parameter loading, and if not, continuously extracting and analyzing the descriptor table.

The parameter loading comprises power-on loading and dynamic loading, wherein the power-on loading corresponds to an external memory interface mode, a complete descriptor table sequence and corresponding parameters are stored in an external memory, after power-on reset, a virtual memory actively requires a loading state machine to start, all the parameters are loaded from the external memory, and the descriptor table sequence is sequentially stored from the first address of the external memory; and dynamically loading a corresponding packet transmission interface mode, inputting a parameter loading data packet during system operation, caching in virtual storage, dynamically loading and updating the specified parameter, and sequentially storing descriptor table sequences from the first address of the RAM.

595 RAMs are set, each RAM is 8KB, an external memory adopts FLASH, packet transmission adopts high-speed SerDes, the RAM, the FLASH and a virtual memory are uniformly addressed, the address bit width is 32 bits, wherein 0xF000_0000 to 0xFFFF _ FFFF is the address space of the FLASH, and 0xE000_0000 to 0xEFFF _ FFFF is the address space of the high-speed SerDes data packet in the virtual memory; the bus uses APB bus, uses 8-port APB bus decoder, cascade plug-in RAM, realizes the doubling expansion of port.

The invention realizes the large-data-volume distributed parameter loading through the descriptor table sequence which can be defined by software, and supports the flexibility and the expandability of various characteristics such as parameter types, parameter sizes, parameter blocking modes and the like; the RTL logic is universal, is realized through an FPGA or a chip, and can be widely applied to DBF systems of various radars; the RAMs of all storage parameters support unified addressing, and all the RAMs can be accessed through a bus; the decoupling of an external interface and internal logic is realized through virtual storage, a packet transmission interface is converted into an internal RAM according to a data packet, and the dynamic loading of specified parameters during running is realized; but not limited to, two modes of power-on loading and dynamic loading of the specified parameters in runtime are supported.

Drawings

Fig. 1 is a schematic block diagram, fig. 2 is a schematic block diagram of virtual storage, fig. 3 is a workflow of a load state machine, fig. 4 is a schematic block diagram of a descriptor table, fig. 5 is a schematic block diagram of descriptor table parsing, fig. 6 is a schematic block diagram of a DMA transfer module, and fig. 7 is a schematic block diagram of an embodiment.

Detailed Description

The technical scheme of the invention is specifically explained in the following by combining the attached drawings.

The principle of the invention is as shown in figure 1, all RAMs storing parameters are addressed and hung on a bus in a unified way, and then external data transmission is mapped into on-chip RAM read-write operation through virtual storage, so that the whole parameter loading process is decomposed into a series of operations of moving from a source address to a target address in a unified way, each moving operation can be accurately defined by a descriptor table, and then the whole parameter loading process can be realized through a description table sequence from sheet _1 to sheet _ N.

The principle of virtual storage is shown in fig. 2, and includes but is not limited to two interface forms based on packet transmission and based on external storage, which respectively correspond to two modes of dynamic loading and power-on loading, and are selected by an interface form control signal.

For an interface based on packet transmission, after receiving a parameter loading data packet, storing effective packet data obtained by analysis in an RAM (random access memory), wherein the effective packet data is represented as RAM read-write operation to the outside, and meanwhile, a controller sends a starting mark to a loading state machine to start dynamic loading of specified parameters in one-time operation, and at the moment, descriptor table sequences are sequentially stored from the first address of the RAM.

For the interface based on the external memory, the external memory reading operation of converting the input RAM reading into the corresponding address according to the time sequence is realized through a reading conversion logic, the parameter loading based on the external memory is automatically started once after the system is powered on and reset, the starting mark is actively sent out by a controller, whether the system is restarted or not is controlled in the running process, and the descriptor table sequence at the moment is sequentially stored from the first address of the external memory.

The parameter loading comprises two modes of power-on loading and dynamic loading during operation:

the power-on loading refers to loading all parameters in the chip from an external memory FLASH after power-on reset. At this time, the complete 595 descriptor table sequences and corresponding parameters are stored in the external FLASH, the descriptor table start address bit is 0xF000_0000, after power-on reset, the virtual storage will actively inform the loading state machine to start parameter loading once, and inform the current interface of the FLASH interface. Subsequently, the loading state machine informs the descriptor table parsing module to read the descriptor table from the start address 0xF000_0000 by taking 12 bytes as a unit, parses information such as a source address, a target address and data length, and starts DMA (direct memory access) for one time, and executes the DMA in sequence until all 595 description tables are processed, and the power-on loading is completed.

A typical descriptor table is shown in fig. 4, which has 12 bytes, the 0 th byte to the 3 rd byte are table heads, Bit [31] indicates whether the current table is valid, if not, the current table does not need to be moved, Bit [30] indicates whether the current table is the last one, if yes, the current table is processed, then the parameter loading is finished, otherwise, the next descriptor table needs to be processed; bit [29:16] is reserved, Bit [15:0] represents the total byte number to be carried at this time, bytes 4 to 7 represent the source address of the carrying number, and bytes 8 to 11 represent the destination address of the carrying number.

The descriptor table parsing principle is as shown in fig. 5, after a module reads a descriptor table of 12 bytes, whether the current table is valid is judged according to a table header Bit [31], if the current table is valid, three data including a data length, a source address and a target address are parsed and written into a DMA data handling module, and finally whether the last table is judged according to a table header Bit [30], and information is fed back to a loading state machine.

The DMA transfer module principle is as shown in fig. 6, the descriptor table parsing module writes a source address, a destination address and a data length into its internal corresponding register, and when it receives a DMA transfer start flag from the load state machine, the controller reads corresponding data from the virtual storage according to the source address, writes the corresponding data into the destination address through the bus, and feeds back a completion flag to the load state machine after sequentially transferring the set data length.

According to the technical scheme, when the number of the parameter RAMs is 595, the external memory is FLASH, and the packet transmission interface is high-speed SerDes, a parameter loading module based on a descriptor table is designed, as shown in FIG. 7, all the internal RAMs, the external memory and the virtual storage are addressed uniformly, the address bit width is 32 bits, wherein the address space of the external FLASH is 0xF000_0000 to 0xFFFF _ FFFF, 0xE000_0000 to 0xEFFF _ FFFF is the RAM in the virtual storage of the high-speed SerDes data packet, and the RAM size is 8 KB.

The bus uses APB bus, because the RAM number is as many as 595, and the bus port number is limited, need to use APB bus decoder (APB _ dec), an 8 port APB _ dec will be to appointing 3bit address bits in the address of inputting 32bit to decode, thus provide the read-write visit of 8 ports, APB _ dec can be cascaded hierarchically, namely 8 ports APB _ dec are connected to 8 ports APB _ dec, finally 64 RAM are connected, realize the port number is expanded by times.

The dynamic loading refers to that in the running process of the system, a data packet is loaded through high-speed SerDes input parameters, and the specified parameters are dynamically loaded and updated. Data for the high-speed SerDes input is cached in RAM in virtual storage at a starting address of 0xE000 — 0000, and then the virtual storage informs the load state machine to initiate a dynamic load and informs its current interface to be the high-speed SerDes interface. And then, the loading state machine informs the descriptor table analysis module to read the descriptor table from the initial address 0xE000_0000 by taking 12 bytes as a unit, analyzes information such as a source address, a target address and data length, and starts DMA (direct memory access) for one time, and sequentially executes the DMA until all the description tables in the current packet are completely processed, and the dynamic loading is completed.

The loading state machine is responsible for scheduling control of the whole loading process, the working process is as shown in fig. 3, when the state machine receives a parameter loading start mark, a correct interface form needs to be set firstly, and simultaneously a descriptor table analyzing module is informed to extract and analyze a descriptor table from a virtual memory, after the analysis is completed, if the current descriptor table is valid, the state machine informs a DMA move module to start a DMA move according to a source address, a target address and a data length obtained by the analysis, after the move is completed, the state machine judges whether the current descriptor table is the last one, if so, the parameter loading is completed, otherwise, the descriptor table analyzing module is informed to extract and analyze the next descriptor table again, and the analogy is carried out until the last descriptor table is processed.

The above-described embodiments are not intended to limit the present invention, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present invention are included in the scope of the present invention.