High speed circuit and method for generating low interference differential trace
阅读说明:本技术 高速电路及产生低干扰差分迹线的方法 (High speed circuit and method for generating low interference differential trace ) 是由 李政宪 于 2019-05-14 设计创作,主要内容包括:本发明公开一种高速电路及产生低干扰差分迹线的方法。高速电路具有一印刷电路板。一对的第一差分信号迹线和第二差分信号迹线是形成在印刷电路板的一第一表面上。第一差分信号迹线和第二差分信号迹线传输一电信号。一部分回路延伸通过印刷电路板。部分回路包括位于第一差分信号迹线和第二差分信号迹线下方的第一端槽和第二端槽。部分回路包括实质上平行于第一差分信号迹线和第二差分信号迹线的一对的侧槽。一固定构件将印刷电路板连接至由第一端槽、第二端槽与侧槽形成的一分隔区。固定构件在第一端槽和第二端槽中的一者或在侧槽中形成一间隙。侧槽的长度与间隙的长度可选定以降低来自电信号的一目标共同模态频率。(The invention discloses a high-speed circuit and a method for generating low-interference differential traces. The high-speed circuit has a printed circuit board. A pair of first and second differential signal traces are formed on a first surface of the printed circuit board. The first differential signal trace and the second differential signal trace transmit an electrical signal. A portion of the loop extends through the printed circuit board. The partial loop includes a first end slot and a second end slot located below the first differential signal trace and the second differential signal trace. The partial loop includes a side slot substantially parallel to a pair of the first differential signal trace and the second differential signal trace. A fixing member connects the printed circuit board to a partition formed by the first end groove, the second end groove and the side groove. The securing member forms a gap in one of the first and second end slots or in the side slot. The length of the side slots and the length of the gaps are selected to reduce a target common mode frequency from the electrical signal.)
1. A high-speed circuit, comprising:
the printed circuit board is provided with a first surface;
a pair of first and second differential signal traces on the first surface of the printed circuit board; the first differential signal trace and the second differential signal trace transmit an electrical signal;
a partial loop extending through the printed circuit board, the partial loop including first and second end slots located below the first and second differential signal traces and a pair of side slots substantially parallel to the first and second differential signal traces;
a fixing member connecting the printed circuit board to a partition formed by the first end groove, the second end groove and the two side grooves, the fixing member forming a gap in one of the first end groove and the second end groove or in the two side grooves;
wherein the length of the two-sided slot and the length of the gap are selected to reduce a target frequency from the electrical signal.
2. The high speed circuit of claim 1, wherein the two side slots have the same shape.
3. The high speed circuit of claim 1, wherein the length of the two side slots and the length of the gap are determined by:
wherein the length of the two side grooves is LpathThe length of the gap is LgapTD is a time delay per milli-inch (mil) length of a differential signal transmitted in the first and second differential signal traces, f is a target frequency, and K is1And K2Is a scaling factor.
4. A high speed circuit as recited in claim 3, wherein the length of the gap and the length of the two side slots are limited to:
5. the high speed circuit of claim 1, wherein the securing member is located in the middle of one of the two side slots.
6. The high-speed circuit of claim 1, wherein the target frequency is dependent on a trace data rate of the electrical signal transmitted on the first and second differential signal traces.
7. A method of generating a low-interference differential trace, the method comprising:
forming a first differential signal trace and a second differential signal trace on a first surface of a printed circuit board;
selecting a path length and a gap length of a partial loop on the printed circuit board to reduce a target frequency from signals transmitted by the first differential signal trace and the second differential signal trace;
forming first and second end slots below the first and second differential signal traces, the first and second end slots separated by the selected path length;
forming a pair of side slots connecting the first end slot and the second end slot; and
forming a securing member to form a gap in one of the first end slot and the second end slot or in one of the two side slots, the gap having a length selected to be the gap length.
8. The method of claim 7, wherein the two side grooves have the same shape.
9. The method of claim 7, wherein the length of the two side slots and the length of the gap are determined by:
wherein the length of the two side grooves is LpathThe length of the gap is LgapTD is a time delay per milli-inch (mil) length of differential signal transmission in the first and second differential signal traces, f is a target frequency, and K is1And K2Is a scaling factor.
10. The method of claim 9, wherein the length of the gap and the length of the two side slots are limited by:
11. the method of claim 7, wherein the securing member is located in the middle of one of the two side slots.
12. The method of claim 7, wherein the target frequency is dependent on a trace data rate of the electrical signal transmitted on the first and second differential signal traces.
Technical Field
The present invention relates generally to high speed traces and, more particularly, to the structure of a portion of a loop on a circuit board to suppress radiation from a high speed differential signal trace.
Background
High-speed differential signal traces are widely used in product designs for servers or memories. Many server or memory products include a chassis (chassis) that is mounted to different printed circuit boards for electronic components. The printed circuit board includes various signal traces to provide signals to components on the printed circuit board. The signal traces are typically provided in differential trace pairs (differential trace pairs) for a particular signal line. Such differential traces on a printed circuit board have different modes, including differential mode, common mode, and mode conversion between differential signals during transmission. As more and more product applications include differential signal conversion between different circuit boards or between a circuit board and a cable, common mode energy will be radiated through the connector to the hole in the chassis by this conversion. The common mode energy produces a signal on both differential traces. Thus, common mode energy may thereby generate noise that disrupts signal transmission on the traces and creates interference problems. Thus, radiation is generated when the differential signal passes through a skewing channel (skewed channel) or a printed circuit board.
Fig. 1 is an example of a prior art
In current circuit designs, a common mode filter (common mode filter) is used to reduce signal radiation on the differential traces. Thus, the circuit components of the common mode filter are implemented on a printed circuit board on the wiring of the differential traces to reduce signal radiation from the traces. The use of a common mode filter is effective, but the circuitry of the filter requires space on the printed circuit board. This creates a space problem for the layout of the circuit board, considering that as many components as possible need to be placed on the printed circuit board to use all physical surface space.
Therefore, there is a need for a common mode filter in a printed circuit board having less spaced differential traces and an effective bandwidth (effective bandwidth) to reduce radiation caused by common mode energy. It is desirable to apply a portion of the ring shape to a printed circuit board to form a common mode filter.
Disclosure of Invention
An example of a disclosed circuit is a high speed circuit. The high-speed circuit has a printed circuit board having a first surface. A pair (a pair of) a first differential signal trace and a second differential signal trace are located on a first surface of the printed circuit board. The first differential signal trace and the second differential signal trace transmit an electrical signal. A portion of the loop (partial loop) extends through the printed circuit board. The partial loop includes a first end slot and a second end slot below the first differential signal trace and the second differential signal trace. The partial loop includes a pair of side slots substantially parallel to the first differential signal trace and the second differential signal trace. A fixing member (anchor member) connects the printed circuit board to a divided area (island) formed by the first end groove, the second end groove and the side groove. The securing member forms a gap in one of the first and second end slots or in the side slot. The length of the side slots and the length of the gap are selected to reduce the target mode frequency from the electrical signal.
Another example disclosed is a method of generating a low interference differential trace. A first differential signal trace and a second differential signal trace are formed on a first surface of a printed circuit board. A path length and a gap length of a portion of the loop on the printed circuit board are selected to reduce a target frequency from a signal transmitted by the first differential signal trace and the second differential signal trace. A first end slot and a second end slot are formed below the first differential signal trace and the second differential signal trace. The first end slot and the second end slot are separated by a selected path length. A pair of side grooves connecting the first end groove and the second end groove is formed. A securing member is formed to form a gap in one of the first end slot and the second end slot or in one of the two side slots, the length of the gap being a selected gap length.
Another disclosed example is a high speed differential trace structure including a first differential signal trace, a second differential signal trace parallel to the first differential signal trace, a printed circuit board, a ground plane layer, a portion of a loop, and a securing member. The printed circuit board has a top surface and an opposite bottom surface. The first differential signal trace and the second differential signal trace are formed on the top surface. The ground plane layer has a top layer that contacts an opposite bottom surface of the printed circuit board. A partial loop extends through the printed circuit board, the partial loop including a first end slot and a second end slot located below the first differential signal trace and the second differential signal trace and a pair of side slots substantially parallel to the first differential signal trace and the second differential signal trace. The fixing member connects the printed circuit board to a partition formed by the first end groove, the second end groove and the two side grooves, the fixing member forming a gap in one of the first end groove and the second end groove or in the two side grooves. The length of the two-sided slot and the length of the gap are selected based on an electrical signal transmitted through the first differential signal trace and the second differential signal trace to reduce a common mode frequency.
The above summary is not intended to represent each embodiment or every aspect of the present invention. Rather, the foregoing summary merely provides an exemplification of some of the novel aspects and features set forth herein. The above features and advantages and other features and advantages of the present invention are readily apparent from the following detailed description of the representative embodiments and aspects of the present invention when taken in connection with the accompanying drawings and appended claims.
Drawings
In order that the manner in which the above recited and other aspects of the present invention are obtained can be understood in detail, a more particular description of the invention, briefly summarized below, may be had by reference to the appended drawings, in which:
FIG. 1 is a schematic diagram of a prior art printed circuit board having a differential trace radiating from common mode operation;
FIG. 2A is a perspective view of a printed circuit board having a differential trace and a portion of a loop as a filter for common mode radiation;
FIG. 2B is a top view of the printed circuit board of FIG. 2A;
FIG. 2C is a schematic diagram of another printed circuit board having a portion of the loop as a filter for common mode radiation from the signal traces;
FIG. 3 is a graphical representation of the output levels of the differential traces of FIGS. 2A and 2B at different frequencies, illustrating the effect of a portion of the loop;
FIG. 4 is a graph illustrating the output levels of different frequencies for different lengths of a portion of a loop;
FIG. 5 is a table diagram of predicted and measured frequency responses for partial loops having different lengths and gap widths.
The invention is susceptible to various modifications and alternative forms. Representative embodiments have been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the invention is not intended to be limited to the particular forms disclosed. Rather, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the following appended claims.
Description of the symbols
10: return circuit trace
12. 100, 200: printed circuit board
14: ground plane layer
20: surface of
22. 24: differential trace
30. 32, 34: arrow head
40: first interface
42: second interface
44: third interface
46: fourth interface
110. 112, 112: differential signal traces
114: top surface
130. 230: partial loop
132. 232: separate zone
134. 234: bridge connector
140. 142: end slot
144. 146: side groove
150. 152: trough part
240: big circular groove
302: first curve
304: second curve
306: third curve
308: fourth curve
310: fifth curve
410. 420: curve line
Lpath、Lgap: length of
Scc21: common mode output
Detailed Description
The invention may be embodied in many different forms. The accompanying drawings illustrate representative embodiments and will be described in detail herein. The present invention is an exemplification or illustration of the principles of the application and is not intended to limit the broad aspect disclosed to the embodiment illustrated. In this regard, elements and limitations that are disclosed in, for example, the abstract, summary, and sections of the embodiments but not explicitly recited in the claims are not intended to be, or are inferred to be, incorporated into the claims individually or collectively. For purposes of this detailed description, the singular includes the plural and vice versa, unless specifically stated otherwise. And the terms "including" and "comprising" mean "including but not limited to". Moreover, approximating words, such as "about (about)," almost (almost), "" substantially (substantailly), "" approximately (appoximately), "and the like, may be used herein to mean" at, "" near (near), "" near (near at), "" or "within 3-5%", or "within acceptable manufacturing tolerances," or any reasonable combination thereof.
Fig. 2A is a perspective view of a printed
To reduce interference, the printed
The
The
For a four interface (two signal traces) S parameter, there are insertion (insertion term) S31 and insertion term S42 and induction (induction term) S41 and induction S32. For example, in fig. 1, the differential traces 22 may be modeled (modeling) based on the first interface 40, the second interface 42, the third interface 44, and the fourth interface 46. Based on the cold-order law (Lenz' sLaw), the inductive term has an opposite direction with respect to the insertion term. Differential output (S) of the differential signal based on a mixed mode S-parameter formuladd21) Can be expressed as:
common mode output (S) of differential signals based on mixed mode S-parameter formulacc21) Can be expressed as:
the approach of reducing the common mode output energy via the structure of the
In this case, the adjacent trace will become a new path for the return current and cause the coupling term to increase. Thus, if a differential signal flows through the differential signal traces 110, the return current path will be routed by the
wherein the content of the first and second substances,
in the above-mentioned algebraic expression, the length of the partial loop is LpathAnd the length of the gap between the two slots in the loop is Lgap. TD represents the time delay per milli-inch (mil) length of a differential signal traveling in the differential trace and the center, f is the target frequency, K1And K2Is a scaling coefficient (scaling coefficient) that depends on the physical structure of the differential trace pair, including thickness and material of the traces. In this example, the ratio isThe numbers are fitted (fitting) constants by analog values. Different Printed Circuit Board (PCB) structures will have different scaling factors. By using the above algebraic expressions, the optimal path length of the partial loop and the gap length in the partial loop can be determined to reduce the radiation at the target frequency. The determined length can then be applied in the manufacture of slots of a circuit board, such slots (slots) constituting part of the loop under the differential traces. The partial loop may have other different shapes.
Fig. 2C shows a top view of a partial loop of a different shape. Fig. 2C depicts an exemplary printed
A portion of the printed
FIG. 3 shows a diagram, whichExemplary outputs from different partial loop parameters are shown using the design methodology described previously in connection with the exemplary printed
In this example, for each curve, the target frequency is 8GHz and the Time Delay (TD) is 1.4285 x 10-13And second. In this example, exemplary micro-strip traces, such as
Having different gap lengths (L) can be calculated and verified by creating a simulation (simulation) of a 3D structure in an electronic design automation tool (EDA tool)gap) Common mode output (S)cc21) To simulate an equivalent channel model (equivalent channel model). In contrast to other shapes of etched designs, such as U-shaped voids requiring a longer path length (e.g., 440 mils)In contrast, the structure of the
FIG. 4 is a graph illustrating a comparison of curves associated with different path lengths to reduce common mode energy. Thus, fig. 4 depicts a curve 410 of a loop configuration (e.g., the configuration of the
Fig. 5 shows a graph of different path lengths and gap lengths and the resulting calculated actual and desired reduction frequencies. The actual reduction frequency calculated is based on the above-mentioned algebraic expression. The desired reduction frequency is determined by the simulation results. The table of fig. 5 shows that a gap of 4 mils and a path length of 348 mils can achieve a reduced frequency of 8GHz, which is closest to the target value. For the longer path length of 428 mils and gap length of 80 mils, the desired drop frequency is 8.8GHz, while the actual drop frequency is 8.91 GHz. Thus, the last entry reflects curve 420 in FIG. 4.
As used in this application, terms such as "component," "model," "system," and the like generally refer to a computer-related entity, either hardware (e.g., a circuit), a combination of hardware and software, or an entity associated with a operating machine that has one or more particular functions. For example, a component may be, but is not limited to being, a process running on a processor (e.g., a digital signal processor), a processor, an object, an executable, a thread of execution, a program, and/or a computer. By way of illustration, both an application running on a controller and the controller can be a component. One or more components can reside within a process and/or thread of execution and a component may be localized on one computer and/or distributed between two or more computers. Furthermore, an "apparatus" may take the form of specially designed hardware, hardware specially designed for the execution of a specific function by executing software thereon, software stored on a computer-readable medium, or a combination thereof.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Furthermore, the terms "comprising," including, "" having, "" involving, "or similar terms, as used in the specification and/or claims, are intended to cover the meanings of the terms" comprising "or" including.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
While various embodiments of the present invention have been described above, it should be understood that they have been presented by way of example only, and not limitation. Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Thus, the breadth and scope of the present invention should not be limited by any of the above-described embodiments. Instead, the scope of the invention should be determined with reference to the appended claims along with their full scope of equivalents.
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