阅读说明：本技术 一种具有高深宽比结构的半导体器件及其制造方法 (Semiconductor device with high depth-width ratio structure and manufacturing method thereof ) 是由 姜东勋 李俊杰 周娜 杨涛 李俊峰 王文武 于 2020-04-09 设计创作，主要内容包括：本申请涉及半导体的制造方法,具体是,提供半导体基底,所述半导体基底形成牺牲模层；刻蚀所述牺牲模层以形成凹槽,所述凹槽用于形成目标结构；在所述凹槽的侧壁上形成侧墙层。本申请的制造方法能够解决在高深宽比开孔工艺中所存在的开孔不充分或开孔存在弓形的问题,以及采用简单的工艺制程即可实现降低半导体结构的关键尺寸,以替代现有的采用复杂的多重图形化等工艺来控制降低关键尺寸。(The application relates to a manufacturing method of a semiconductor, in particular to a semiconductor substrate which forms a sacrificial mold layer; etching the sacrificial mold layer to form a groove, wherein the groove is used for forming a target structure; and forming a side wall layer on the side wall of the groove. The manufacturing method can solve the problems of insufficient opening or arch-shaped opening in the opening process with high depth-to-width ratio, and can reduce the critical dimension of the semiconductor structure by adopting a simple process so as to replace the prior process of adopting complex multiple patterning and the like to control and reduce the critical dimension.)

1. A method of fabricating a semiconductor structure, comprising:

providing a semiconductor substrate, wherein the semiconductor substrate forms a sacrificial mold layer;

etching the sacrificial mold layer to form a groove, wherein the groove is used for forming a target structure;

and forming a side wall on the side wall of the groove.

2. The manufacturing method according to claim 1, characterized in that:

the forming thickness of the side wall is determined by the external size of the target structure, so that the external size of the target structure is just limited by the inner wall of the side wall.

3. The manufacturing method according to claim 1, characterized in that:

the step of forming the side wall includes:

depositing a side wall material layer on the whole semiconductor substrate;

and etching the side wall layer to remove the bottom of the side wall layer.

4. The manufacturing method according to claim 1, characterized in that:

the target structure has a high aspect ratio; further, the aspect ratio is 1:20-1: 100.

5. The manufacturing method according to any one of claims 1 to 4, characterized in that:

the side wall comprises a dielectric material; further, the dielectric material includes any one or a combination of two or more of the group consisting of a nitride, an oxide, and a spin-on carbon composition.

6. The manufacturing method according to any one of claim 3, characterized in that:

and etching the side wall layer by adopting a plasma dry etching method or a chemical wet etching method.

7. The manufacturing method according to any one of claims 1 to 4, characterized in that:

the groove is a capacitor groove, and the target structure is a capacitor structure.

8. The manufacturing method according to claim 7, characterized in that:

and after the side wall is formed, forming a lower electrode on the inner wall of the side wall.

9. The manufacturing method according to claim 8, characterized in that:

and after the lower electrode is formed, removing the side wall.

10. The manufacturing method according to claim 9, characterized in that:

the method for removing the side wall comprises dry etching or wet etching.

11. The manufacturing method according to claim 9 or 10, characterized in that:

and after removing the side walls, forming a dielectric layer and an upper electrode on the inner side and the outer side of the lower electrode, wherein the lower electrode, the dielectric layer and the upper electrode form the capacitor structure.

12. The manufacturing method according to claim 8, characterized in that:

and after the lower electrode is formed, forming a dielectric layer and an upper electrode on the lower electrode, wherein the lower electrode, the dielectric layer and the upper electrode form the capacitor structure.

13. A capacitor structure, comprising:

a trench located on the semiconductor substrate;

the side wall is arranged on the inner side wall of the groove;

the lower electrode, the dielectric layer and the upper electrode are sequentially arranged on the inner side wall of the side wall and the bottom wall of the groove;

the outer side wall of the side wall is wrapped by the interlayer dielectric layer.

Technical Field

The present application relates to semiconductor devices and methods of fabricating the same, and more particularly, to a semiconductor device having a high aspect ratio structure and a method of fabricating the same.

Background

As the functions of semiconductor devices become more complex, the structures thereof become more and more diversified. Among them, the Aspect Ratio (Aspect Ratio) has become one of important parameters of device structures, and various structures have been provided in new semiconductor devices with High Aspect Ratio (High Aspect Ratio Contact, HARC), Self-aligned Contact (SAC), and the like. Due to the large aspect ratio of such structures, the process is complicated and has many difficulties and problems. For example, the opening (Open) of a high aspect ratio hole often cannot be etched sufficiently due to its large aspect ratio (Under Etch/Incomplete Etch) and thus causes an insufficient opening (Not-Open), and in order to overcome the problem of insufficient etching of the opening, the opening is overetched without causing an Over-etching (Over Etch) and thus causes a Bowing (Bowing) problem of the hole wall.

For example, in the conventional method for manufacturing a cylindrical capacitor, a high aspect ratio contact Oxide etching (HARC Oxide Etch) process is used, and in order to reduce the Critical Dimension (CD) to increase the effective usable area and the storage capacity of the capacitor, a Double Patterning (DPT) or a quadruple Patterning (quad Patterning Technology) process is further combined in the HARC Oxide Etch (HARC Oxide Etch) process. As mentioned above, in the HARC Oxide Etch (HARC Oxide Etch) process, in order to avoid the problem of insufficient opening (Not-Open), the Bowing (Bowing) of the hole wall is inevitably caused, and therefore, the dimension of the adjacent hole pitch is forced to be designed as large as possible to prevent the contact failure between adjacent holes caused by Bowing (Bowing) and bending (Twist) of the hole wall. In addition to the Double Patterning (DPT) process, the hard mask Oxide and its etching, the hard mask polysilicon and its etching, which must be used, make the process of high aspect ratio contact Oxide etching (HARC Oxide Etch) a rather complicated process.

Disclosure of Invention

The purpose of the application is realized by the following technical scheme:

in accordance with one or more embodiments, the present application also discloses a method of fabricating a semiconductor structure, characterized by:

providing a semiconductor substrate, wherein the semiconductor substrate forms a sacrificial mold layer;

etching the sacrificial mold layer to form a groove, wherein the groove is used for forming a target structure;

and forming a side wall layer on the side wall of the groove.

In accordance with one or more embodiments, the present application also discloses a capacitor structure characterized by: comprises the steps of (a) preparing a mixture of a plurality of raw materials,

a trench located on the semiconductor substrate;

the side wall is arranged on the inner side wall of the groove;

the lower electrode, the dielectric layer and the upper electrode are sequentially arranged on the inner side wall of the side wall and the bottom wall of the groove;

the outer side wall of the side wall is wrapped by the interlayer dielectric layer.

The application also discloses a semiconductor device, an electronic device and the like comprising the capacitor structure or the capacitor structure prepared by the manufacturing method according to one or more embodiments.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the embodiments of the application, or may be learned by the practice of the embodiments. The objectives and other advantages of the application may be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the application. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a schematic cross-sectional view illustrating a lower electrode layer deposited by a method of manufacturing a first embodiment of the present application;

FIG. 2 is a schematic longitudinal sectional view of a manufacturing method according to a first embodiment of the present application;

fig. 3 is a schematic longitudinal sectional view of a manufacturing method according to a second embodiment of the present application.

Detailed Description

The present application will now be described more fully hereinafter with reference to the accompanying drawings, in which embodiments of the application are shown. However, the present application is not limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the application to those skilled in the art. In the drawings, the thickness of layers and regions may be exaggerated for clarity. Like numbers refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the singular forms "a", "an" and "the" and the like include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that when an element such as a layer, region or substrate is referred to as being "on" or extending "onto" another element, it can be directly on or extend directly onto the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, there are no intervening elements present. It will also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the spirit of the present application.

Moreover, relative terms, such as "lower" or "bottom" and "upper" or "top," are used herein to describe one element's relationship to another element as illustrated in the figures. It will be understood that relative terms encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as being on the lower side of another element would then be turned over to be on the upper side of the other element. The exemplary term "lower" therefore includes both "lower" and "upper" directions, depending on the particular orientation of the figure. Likewise, if the device in one of the figures is turned over, elements described as "below" or "beneath" other elements would then be oriented above the other elements. Thus, the exemplary term "below" or "beneath.

Embodiments of the present application are described herein with reference to cross-sectional (and/or plan) views that schematically illustrate idealized embodiments of the present application. Likewise, deviations from the schematic shape due to, for example, manufacturing processes and/or tolerances, can be expected. Thus, embodiments of the present application are not to be considered as limiting the particular shapes of regions illustrated herein, but to include deviations in shapes that result, for example, from manufacturing. For example, etched areas illustrated or described as rectangles typically have rounded or curved features. Thus, the regions illustrated in the figures are schematic in nature and their shapes are not intended to illustrate the precise shape of a region of a device and are not intended to limit the scope of the present application.

Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein. It will be understood by those skilled in the art that references to a structural or functional component disposed adjacent to another component may have portions that overlap or underlie the other component.

The application discloses a semiconductor structure and a method of manufacturing the same, the semiconductor structure may include features having a high aspect ratio, which may be, for example, 1:20 to 1:100, and may include, for example, a semiconductor structure having a high aspect ratio capacitor, which may be a cylindrical capacitor, or any other schematically shaped high aspect ratio capacitor. The following embodiments are exemplified by a capacitor having a cylindrical structure, but the present application is not limited thereto, and the specific capacitor structure and process are as follows:

next, a process of manufacturing the semiconductor device and a material used in the semiconductor device according to an embodiment of the present application will be described in further detail:

the application discloses a manufacturing method of a semiconductor structure, which can be suitable for manufacturing a cylindrical Capacitor (Cylinder Capacitor) structure, but is not limited to the manufacturing method of the cylindrical Capacitor structure, and the manufacturing method is particularly suitable for etching a contact hole with a high aspect ratio.

In one embodiment of the present application, the specific process is as follows:

in the process of the present application, as shown in fig. 2a, a semiconductor substrate 100 having circuit elements such as mos (metal Oxide semiconductor) transistors may be provided, and functional components such as gates, source/drains, bit lines, etc. are formed on the semiconductor substrate 100. An interlayer insulating layer and an etch stop layer may also be formed on the semiconductor substrate.

Subsequently, an etch stop layer 200 may be formed on the semiconductor substrate 100, and a sacrificial mold layer 300 may be formed on the etch stop layer. The sacrificial mold layer may use an oxide, such as SiO, as is common₂SiOH, PSG (Phosphosilicate glass), BPSG (Borophosphosilicate glass), SiCOH, TEOS (Tetraethylorthosilicate), or a combination of two or more thereof. The sacrificial mold layer may be formed by a suitable process such as Chemical Vapor Deposition (CVD), Low Pressure Chemical Vapor Deposition (LPCVD), or Plasma Enhanced Chemical Vapor Deposition (PECVD).

Subsequently, a mask layer (not shown) may be formed on the sacrificial mold layer, and the mask layer may include a common mask material such as polysilicon (Poly-Si), doped silicon (Dope-Si), Amorphous Carbon (ACL), spin-on Silicon (SOH) layer, etc. formed using a CVD process.

The mask layer may then be photolithographically processed using conventional lithographic means to obtain a patterned mask layer.

The sacrificial layer may then be etched according to the patterned mask layer to form a cylindrical recess 400, the recess 400 forming a process space for performing subsequent deposition of a lower electrode, a dielectric layer, a top electrode, and the like. The etching process may adopt a conventional dry etching process or a wet etching process, and in order to embody the advantage that the opening distance can be reduced as much as possible, the present application may adopt an Ion Angular Distribution Function (IADF) etching method, and the occurrence of the bow problem is further reduced by pulse modulation and high-power etching.

Subsequently, the mask layer can be removed, for example, using conventional ashing processes or the like.

Subsequently, as shown in fig. 2b, a sidewall 500 may be formed on the inner sidewall of the cylindrical recess formed by the sacrificial mold layer, and at the same time, as shown in the cross-sectional view of fig. 1, the thickness h of the sidewall 500 is formed by the outer peripheral dimension of the sidewall of the lower electrode 600 of the cylindrical capacitorIt is determined that the diameter phi of the inner sidewall of the groove 400 minus the thickness h of the sidewall is exactly equal to the outer peripheral diameter of the sidewall of the cylindrical lower electrodeBy forming the sidewall 500 with a certain thickness on the inner sidewall of the trench 400, the aperture of the final deposited hole can be effectively reduced, so that when the sacrificial film layer 300 is etched and opened, the aperture size of the opened trench is Not limited to the critical size of the cylindrical capacitor, but the opened trench is selected as large as possible, as long as the requirement of the capacitance integration level and the required adjacent hole spacing are met, and the large hole is opened as much as possible, so that the problem of insufficient opening (Not-ope) caused by insufficient etching (Under etch) can be well solvedThe non-uniformity problem is finally reduced and adjusted by forming a sidewall layer with a specific thickness. Furthermore, since the critical dimension is controlled by adjusting the control of the subsequent sidewall layer formation, not by the opening dimension of the sacrificial film layer, the opening of the sacrificial film layer does not need to be formed by a Double Patterning (DPT) or Quad Patterning (QPT) Mask formation process and a subsequent Hard Mask polysilicon etching (Hard Mask Poly Etch), a Hard Mask Oxide (Hard Mask Oxide Etch), and other complicated processes, thereby resulting in a large critical dimension control in the embodiments of the present applicationGreatly simplifying the process. In the prior art, generally, when a DRAM with the size of 30-40nm is prepared, a complex multi-pattern process such as DPT (dual patterning technology) is not needed, but if a product with the size of below 30nm is prepared, the complex multi-pattern process is needed, and if the method for adjusting the size of the opening formed by forming the side wall after the opening is etched according to the application, the complex process such as the multi-pattern process is not needed even when the product with the size of below 30nm is prepared like the product with the size of 30-40 nm.

In order to ensure that the thickness of the sidewall 500 is uniform and can be accurately controlled, an Atomic Layer Deposition (ALD) process may be used. In order to ensure that the electrical properties of the subsequent process and the final product are not affected, the sidewall spacers may be made of a common dielectric material, for example, any one or a combination of two or more of the group consisting of nitride, oxide and spin-on carbon composition.

The sidewall spacers 500 may be formed by first forming a sidewall layer on the entire semiconductor substrate and then performing anisotropic etching. The anisotropic etching is mainly to remove the bottom of the undesired sidewall layer formed during the formation of the sidewall layer, which may interfere with the communication between the bottom wall of the lower electrode deposited subsequently and the lower Landing Pad (bonding Pad) and the like, and thus needs to be removed. By adopting anisotropic dry etching, the bottom of the side wall layer which is not expected can be ensured to be removed without causing loss to the side wall layer of the side wall of the groove, and proper chemical corrosive liquid can be adopted for wet etching, on the premise that the bottom of the side wall layer is ensured to be removed, and the aperture of the deposition hole can be ensured to reduce the expected size. In other alternatives, the etching of the sidewall layer is not necessary, for example, in some cases, when the sidewall layer is formed, the sidewall layer is formed only on the sidewall of the groove, and the sidewall layer is not formed on the bottom wall of the groove, i.e., the sidewall layer has no bottom structure, and thus, the sidewall layer is not necessarily etched.

After the sidewall spacer 500 structure is formed, a deposition process of a lower electrode may be performed in the capacitor hole including the sidewall spacer 500. For example, a layer of TiN may be deposited as the lower electrode 600 throughout the semiconductor structure, including within the capacitor hole, as shown in fig. 2 c. Then, the bottom electrode, for example, TiN, may be etched back, and then, dry etching or wet etching may be used to remove the materials, such as the sacrificial film 300 and the sidewall spacers 500, and in an embodiment of the present invention, wet etching is preferably used to remove the materials, such as the sacrificial film 300 and the sidewall spacers 500, as shown in fig. 2 d. For other embodiments of the invention, the sacrificial film layer can be removed by dry etching, and the side wall structure can be removed by wet etching.

Finally, as shown in fig. 2d, a dielectric layer 700 and an upper electrode 800 in the capacitor structure may be formed simultaneously inside and outside the lower electrode 600. The dielectric layer can be made of high-k dielectric material, such as ZAZ (Zr/Al)₂O3/Zr) material, and the upper electrode may be formed of doped polycrystalline silicon germanium, for example, as the electrode layer.

Another embodiment of the present application further discloses a method for manufacturing a semiconductor structure, which may be suitable for manufacturing a Concave Capacitor (Concave Capacitor) structure, wherein the method for forming a sidewall and the previous process method in this embodiment may be the same as the method for manufacturing a cylindrical Capacitor structure in the previous embodiment, and are not described herein again, and may also be performed by using a suitable alternative process, and the following description mainly refers to the process method after forming the sidewall, and specifically includes:

referring to fig. 3, after forming a sidewall spacer 500 ' structure on the inner sidewall of the trench of the interlayer dielectric layer 300 ' on the substrate 100 ', a lower electrode 600 ', a dielectric layer 700 ' and an upper electrode 800 ' may be sequentially deposited in the capacitor hole including the sidewall spacer 500 '. For example, a TiN layer may be deposited as the bottom electrode 600 ' over the entire semiconductor structure, including the capacitor hole, and then the bottom electrode 600 ' may be etched back, followed by the deposition of a dielectric layer 700 ' over the bottom electrode 600 ', which dielectric layer 700 ' may be, for example, ZAZ (Zr/Al)₂O3/Zr) material. Finally, an upper electrode material, such as doped poly-silicon germanium, is deposited over the entire semiconductor structure, including the capacitor holes, to fill the space in the capacitor holes to form the upper electrode 800'.

As shown in fig. 3, the concave capacitor manufactured by the manufacturing method of the second embodiment may include a trench embedded in the interlayer dielectric layer 300 ' on the semiconductor substrate 100 ', a sidewall 500 ' disposed on a sidewall of the trench, and a lower electrode 600 ', a dielectric layer 700 ' and an upper electrode 800 ' sequentially disposed inside the sidewall 500 '. Unlike the cylindrical capacitor structure manufactured in the first embodiment, in the concave capacitor in this embodiment, the sidewall 500 'may be not removed, but coated outside the lower electrode 600' as a part of the capacitor structure. The sidewall spacers 500 'also wrap around the interlevel dielectric layer 300' on the outer sidewalls.

In addition to the above embodiments, the manufacturing method of the present application is also applicable to other methods for manufacturing a semiconductor structure with a high aspect ratio, so as to solve the problem of insufficient opening or bow-shaped opening in the high aspect ratio opening process, and reduce the critical dimension of the semiconductor structure by using a simple process, instead of using the conventional complex multiple patterning process to control and reduce the critical dimension.

In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.

The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.