阅读说明：本技术 开关调节器及其操作方法 (Switching regulator and method of operating the same ) 是由 野见山贵弘 朴承赞 白种范 于 2020-03-10 设计创作，主要内容包括：一种被配置为根据输入电压产生电平控制的输出电压的开关调节器,所述开关调节器包括：电感器；输出电容器,被配置为基于流经所述电感器的电流来产生所述电平控制的输出电压；至少两个飞跨电容器；以及多个开关,被配置为当开关调节器在第一操作模式下操作时形成电连接,以使用所述输入电压交替地对所述至少两个飞跨电容器中的每一个飞跨电容器进行充电,以及使用所述至少两个飞跨电容器中的充电的飞跨电容器向所述电感器提供第一升压电压。(A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator comprising: an inductor; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; at least two flying capacitors; and a plurality of switches configured to form an electrical connection when the switching regulator operates in a first mode of operation to alternately charge each of the at least two flying capacitors with the input voltage and to provide a first boost voltage to the inductor using the charged flying capacitor of the at least two flying capacitors.)

1. A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator comprising:

an inductor;

an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor;

at least two flying capacitors; and

a plurality of switches configured to form an electrical connection when the switching regulator operates in a first mode of operation to:

alternately charging each of the at least two flying capacitors using the input voltage, an

Providing a first boost voltage to the inductor using a charged flying capacitor of the at least two flying capacitors.

2. The switching regulator as claimed in claim 1, wherein

The switching regulator is configured to operate in the first operation mode when a target voltage level of the level-controlled output voltage is equal to or higher than a reference voltage level.

3. The switching regulator as claimed in claim 1, wherein

The plurality of switches comprises a plurality of connecting switches connected to the at least two flying capacitors and configured to form an electrical connection to selectively apply the input voltage to at least one of the at least two flying capacitors.

4. The switching regulator as claimed in claim 3, wherein

At least one of the plurality of connection switches is configured to turn on to output current through one of a plurality of paths when the switching regulator operates in the first operating mode.

5. The switching regulator as claimed in claim 4, wherein

The plurality of paths includes a first path toward one of the at least two flying capacitors and a second path toward the inductor.

6. The switching regulator as claimed in claim 1, wherein

The at least two flying capacitors comprise a first flying capacitor and a second flying capacitor; and is

The plurality of switches are configured to form an electrical connection when the switching regulator operates in a first phase of the first mode of operation to:

connecting the inductor to the first flying capacitor, an

Charging the second flying capacitor with the input voltage in a first phase during the first mode of operation.

7. The switching regulator as claimed in claim 6, wherein

The plurality of switches are configured to form an electrical connection when the switching regulator is operated in a second stage of the first mode of operation to:

connecting the inductor to the second flying capacitor, an

Charging the first flying capacitor using the input voltage.

8. The switching regulator as claimed in claim 7, wherein

The plurality of switches are configured to form an electrical connection to provide the input voltage to the inductor through a first path when the switching regulator operates in a third phase of the first mode of operation, the first path being through a first switch of the plurality of switches connected to one end of the first flying capacitor.

9. The switching regulator as claimed in claim 8, wherein

The plurality of switches are configured to form an electrical connection to provide the input voltage to the inductor through a second path when the switching regulator operates in a fourth phase of the first mode of operation, the second path being through a second switch of the plurality of switches connected to one end of the second flying capacitor.

10. The switching regulator as claimed in claim 1, wherein

The switching regulator is configured to operate in the first operating mode or a second operating mode different from the first operating mode; and is

The plurality of switches are configured to form an electrical connection when the switching regulator operates in the second mode of operation to:

simultaneously charging the at least two flying capacitors using the input voltage, an

Providing a second boost voltage to the inductor using all of the at least two flying capacitors.

11. The switching regulator as claimed in claim 10, wherein

The switching regulator is configured to operate in the second operation mode when a target voltage level of the level-controlled output voltage is lower than a reference voltage level.

12. The switching regulator as claimed in claim 10, wherein

The plurality of switches are configured to form an electrical connection to:

connecting the inductor to the at least two flying capacitors when the switching regulator operates in a first phase of the second mode of operation, an

Charging the at least two flying capacitors with the input voltage when the switching regulator operates in a second phase of the second mode of operation.

13. The switching regulator as claimed in claim 1, wherein

The current flowing through the inductor is provided to the output capacitor and a load receiving the level controlled output voltage.

14. The switching regulator as claimed in claim 1, wherein

The output capacitor is connected to the inductor.

15. A switching regulator configured to generate a level-controlled output voltage from an input voltage, the switching regulator comprising:

an inductor;

an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor;

a first flying capacitor configured to provide a first boost voltage to the inductor;

a second flying capacitor configured to provide a second boost voltage to the inductor;

a first switching circuit connected to the first flying capacitor and configured to form an electrical connection to:

connecting the first flying capacitor to the inductor when the switching regulator operates in a first phase of a first operating mode, the first operating mode being based on an interleaved switching control scheme, an

Charging the first flying capacitor with the input voltage when the switching regulator is operating in a second phase of the first mode of operation; and

a second switching circuit connected to the second flying capacitor and configured to form an electrical connection to:

charging the second flying capacitor with the input voltage when the switching regulator operates in the first phase of the first mode of operation; and

connecting the second flying capacitor to the inductor when the switching regulator operates in the second stage of the first mode of operation.

16. The switching regulator as claimed in claim 15, wherein

The first switch circuit and the second switch circuit are connected in parallel with each other between a terminal receiving the input voltage and the inductor.

17. The switching regulator as claimed in claim 15, wherein

The first operating mode includes a first boost mode for generating the level-controlled output voltage having a voltage level equal to or higher than a reference voltage level.

18. The switching regulator as claimed in claim 15, wherein

Each of the first and second switching circuits is configured to pass a respective current through a respective path in the first mode of operation.

19. The switching regulator as claimed in claim 15, wherein

The first switching circuit is configured to form an electrical connection to generate the level-controlled output voltage based on a first current output from the first switching circuit when the switching regulator operates in the first and third phases of the first operating mode; and is

The second switching circuit is configured to form an electrical connection to charge the second flying capacitor when the switching regulator operates in the first and third phases of the first mode of operation.

20. The switching regulator as claimed in claim 19, wherein

The first switching circuit is configured to form an electrical connection to charge the first flying capacitor when the switching regulator operates in the second and fourth phases of the first mode of operation; and is

The second switching circuit is configured to form an electrical connection to generate the level-controlled output voltage based on a second current output from the second switching circuit when the switching regulator operates in the second and fourth phases of the first operating mode.

21. The switching regulator as claimed in claim 15, wherein

The switching regulator is configured to operate in the first mode of operation or a second mode of operation different from the first mode of operation, the second mode of operation being based on a synchronous switching control scheme;

the first switching circuit is configured to form an electrical connection when the switching regulator operates in the second operating mode to simultaneously perform:

connecting the first flying capacitor to the inductor, an

Charging the first flying capacitor; and is

The second switching circuit is configured to form an electrical connection when the switching regulator operates in the second operating mode to simultaneously perform:

connecting the second flying capacitor to the inductor, an

Charging the second flying capacitor.

22. The switching regulator as claimed in claim 21, wherein

The second operating mode includes a buck-boost mode and a second boost mode, each of the buck-boost mode and the second boost mode for generating the level controlled output voltage having a voltage level lower than a reference voltage level.

23. The switching regulator as claimed in claim 15, wherein

The switching regulator is configured to operate in the first operating mode or a second operating mode different from the first operating mode;

the first switching circuit is configured to form an electrical connection when the switching regulator operates in the second operating mode to simultaneously perform:

connecting the first flying capacitor to the inductor, an

Charging the first flying capacitor; and is

The second switching circuit is disabled when the switching regulator operates in the second operating mode.

24. A switching regulator configured to generate an output voltage from an input voltage, the switching regulator comprising:

an inductor;

an output capacitor configured to generate the output voltage based on a current flowing through the inductor;

a plurality of first flying capacitors; and

a first switching circuit configured to provide a first boost voltage boosted from the input voltage to the inductor in one of a buck-boost mode or a boost mode by forming an electrical connection to:

charging each of the plurality of first flying capacitors in a first phase using the input voltage, an

Connecting the plurality of first flying capacitors in series to the inductor in a second stage.

25. The switching regulator as claimed in claim 24, further comprising:

a plurality of second flying capacitors; and

a second switching circuit configured to provide a second boost voltage boosted from the input voltage to the inductor in the boost mode based on an interleaved switching control scheme by forming an electrical connection to:

charging the plurality of second flying capacitors using the input voltage in a phase different from the first phase, and

connecting the plurality of second flying capacitors in series to the inductor in a phase different from the second phase.

Technical Field

The present inventive concept relates to generation of a power supply voltage, and more particularly, to a switching regulator and an operating method thereof.

Background

A supply voltage may be generated to power the electronic component, and a level of the supply voltage provided to the electronic component may be varied to reduce power consumption of the electronic component. For example, in the case of a digital circuit that processes a digital signal, a low-level power supply voltage may be supplied when a relatively low performance is desired, and a high-level power supply voltage may be supplied when a relatively high performance is desired. Accordingly, a switching regulator generating power supply voltages of various levels may be used, and the switching regulator may rapidly change a voltage level in a limited design space and generate a power supply voltage with reduced noise. Therefore, a compact switching regulator that realizes efficient generation of power supply voltages of various levels has been studied.

Disclosure of Invention

The present inventive concept provides a switching regulator and a method of operating the same to improve reliability and efficiency of a voltage conversion operation of generating an output voltage.

According to an aspect of the inventive concept, there is provided a switching regulator configured to generate a level-controlled output voltage according to an input voltage. The switching regulator includes: an inductor; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; at least two flying capacitors; and a plurality of switches configured to form an electrical connection when the switching regulator operates in a first mode of operation to alternately charge each of the at least two flying capacitors with the input voltage and to provide a first boost voltage to the inductor using the charged flying capacitor of the at least two flying capacitors.

According to an aspect of the inventive concept, there is provided a switching regulator configured to generate a level-controlled output voltage according to an input voltage. The switching regulator includes: an inductor; an output capacitor configured to generate the level-controlled output voltage based on a current flowing through the inductor; a first flying capacitor configured to provide a first boost voltage to the inductor; a second flying capacitor configured to provide a second boost voltage to the inductor; a first switching circuit connected to the first flying capacitor and configured to form an electrical connection to: connecting the first flying capacitor to the inductor when the switching regulator operates in a first phase of a first operating mode, the first operating mode being based on an interleaved switching control scheme, and charging the first flying capacitor using the input voltage when the switching regulator operates in a second phase of the first operating mode; and a second switching circuit connected to the second flying capacitor and configured to form an electrical connection to: charging the second flying capacitor with the input voltage when the switching regulator operates in the first phase of the first mode of operation; and connecting the second flying capacitor to the inductor when the switching regulator is operating in the second stage of the first mode of operation.

According to an aspect of the inventive concept, there is provided a switching regulator configured to generate an output voltage from an input voltage. The switching regulator includes: an inductor; an output capacitor configured to generate the output voltage based on a current flowing through the inductor; a plurality of first flying capacitors; and a first switching circuit configured to provide a first boosted voltage boosted from the input voltage to the inductor in one of a buck-boost mode or a boost mode by forming an electrical connection to: charging each of the plurality of first flying capacitors with the input voltage in a first phase, and connecting the plurality of first flying capacitors in series to the inductor in a second phase.

Drawings

Some example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a block diagram of a switching regulator according to an example embodiment;

fig. 2A to 3B are schematic diagrams of a switching regulator according to an example embodiment;

fig. 4 is a circuit diagram of the switching regulator 20 according to an example embodiment;

fig. 5A to 5D are circuit diagrams of the switching regulator 20 operating in the second boost mode as the first operation mode according to example embodiments, and fig. 5E is a timing diagram illustrating an operation of the switching regulator 20 in the second boost mode according to some example embodiments, in which respective states of fig. 5A to 5D are sequentially repeated;

fig. 6A and 6B are circuit diagrams of the switching regulator 20 operating in the step-down mode as the second operation mode according to example embodiments, and fig. 6C is a timing chart showing the operation of the switching regulator 20 in the step-down mode, in which the respective states of fig. 6A and 6B are repeated;

fig. 7A to 7C are circuit diagrams of the switching regulator 20 operating in a buck-boost mode as a second operation mode according to example embodiments, and fig. 7D is a timing diagram illustrating an operation of the switching regulator 20 in the buck-boost mode according to some example embodiments, in which the respective states of fig. 7A to 7C are sequentially repeated;

fig. 8A and 8B are circuit diagrams of the switching regulator 20 operating in the first boost mode as the second operation mode according to example embodiments, and fig. 8C is a timing diagram illustrating an operation of the switching regulator 20 of fig. 8A and 8B according to some example embodiments;

fig. 9 is a circuit diagram of a switching regulator 30 including a single switching circuit according to an example embodiment;

fig. 10A and 10B are circuit diagrams of the switching regulator 30 including a single switching circuit operating in the second boosting mode according to example embodiments, and fig. 10C is a timing diagram illustrating an operation of the switching regulator 30 including a single switching circuit of fig. 10A and 10B according to some example embodiments;

fig. 11 is a circuit diagram of a switching regulator 30 including two switching circuits according to an example embodiment;

fig. 12 is a table of conditions for setting an operation mode of a switching regulator according to an example embodiment;

FIG. 13 is a flow chart of a method of operating a switching regulator according to an example embodiment;

fig. 14 is a detailed flowchart of operation S140 in fig. 13 according to an example embodiment;

FIG. 15 is a schematic diagram of a system according to an example embodiment; and

fig. 16 is a block diagram of a wireless communication device according to an example embodiment.

Detailed Description

In this specification, the turn-on of the switch may refer to a state in which both ends of the switch are electrically connected to each other, and the turn-off of the switch may refer to a state in which both ends of the switch are electrically disconnected from each other. In addition, at least two elements electrically connected to each other via a switch in an on state and/or a conductive line may be simply referred to as "connected", and at least two elements electrically connected to each other via a conductive line or the like at all times may be referred to as "coupled".

Hereinafter, embodiments will be described in detail with reference to the accompanying drawings.

Fig. 1 is a block diagram of a switching regulator 10 according to an example embodiment. The switching regulator 10 may receive an input voltage VIN through an input node 13 and output an output voltage VO through an output node 14. The output voltage VO may be used as a supply voltage for other electronic components (and/or loads).

As shown in fig. 1, switching regulator 10 may include a switching circuit 11, a controller 12, a plurality of flying capacitors (e.g., a first flying capacitor CFa and a second flying capacitor CFb), an inductor L, and/or an output capacitor CO. In some embodiments, the elements of the switching regulator 10 may be included in a single semiconductor package. In some embodiments, the switching regulator 10 may include a Printed Circuit Board (PCB), and at least two components of the switching regulator 10 may be mounted on the PCB as separate semiconductor packages. According to some example embodiments, operations described herein as being performed by the controller 12 may be performed by processing circuitry. As used in this disclosure, the term "processing circuitry" may refer to, for example, hardware comprising logic circuitry; a hardware/software combination such as a processor executing software; or a combination thereof. For example, the processing circuit may more particularly include, but is not limited to, a Central Processing Unit (CPU), an Arithmetic Logic Unit (ALU), a digital signal processor, a microcomputer, a Field Programmable Gate Array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an Application Specific Integrated Circuit (ASIC), and the like. According to some example embodiments, the operations described herein as being performed by the switching regulator 10 may be performed based on control signals generated by the controller 12.

The switching regulator 10 may refer to an electronic circuit configured to generate the output voltage VO by turning elements on or off. For example, the switching circuit 11 of the switching regulator 10 may turn on or off at least one switch included in the switching circuit 11 based on the switching control signal CS _ SW from the controller 12, and thus may control the path of the inductor current IL flowing through the inductor L. The switching regulator 10 can operate as various converters by the operation of the switching circuit 11, which will be described below.

As an example of the switching regulator 10, a Direct Current (DC) -DC converter may generate a DC voltage (e.g., an output voltage VO) from a DC voltage (e.g., an input voltage VIN). For example, a buck converter may produce an output voltage VO at a lower level than the input voltage VIN and may be referred to as a buck converter. The boost converter may generate an output voltage VO at a higher level than the input voltage VIN and may be referred to as a boost converter. Further, the boost converter may operate in multiple boost modes. For example, the boost converter may operate in a boost mode in which the ratio of the level of the input voltage VIN to the level of the output voltage VO is equal to or lower than a reference value, or the boost converter may operate in a boost mode in which the ratio of the level of the input voltage VIN to the level of the output voltage VO exceeds a reference value. A buck-boost (or boost/buck) converter may produce an output voltage VO at a lower or higher level than the input voltage VIN. In the following, the switching regulator 10 will be described primarily with reference to a buck-boost DC-DC converter that generates an output voltage in various operating modes, but it should be understood that example embodiments may be applied to different types of switching regulators 10, such as an Alternating Current (AC) converter in which the input voltage VIN is an AC voltage. According to some example embodiments, the reference value may be a design parameter determined through empirical studies.

In some embodiments, the switching regulator 10 may be set in a buck mode, a buck-boost mode, and/or one of a plurality of boost modes according to a target level of the output voltage VO. For example, the controller 12 may set the mode of the switching regulator 10 based on the input voltage VIN and the reference voltage VREF. In some embodiments, the controller 12 may place the switching regulator 10 in the buck mode when the level of the output voltage VO is less than about 90% of the input voltage VIN, the controller 12 may place the switching regulator 10 in the first boost mode (or the normal boost mode) when the level of the output voltage VO is equal to or greater than about 110% of the input voltage VIN and less than about 150% of the input voltage VIN, the controller 12 may place the switching regulator 10 in the second boost mode (or the extended boost mode) when the level of the output voltage VO is equal to or greater than about 150% of the input voltage VIN, and the controller 12 may place the switching regulator 10 in the buck-boost mode when the level of the output voltage VO is equal to or greater than about 90% of the input voltage VIN and less than greater than about 110% of the input voltage VIN. Since the switching regulator 10 supports all of the buck mode, the buck-boost mode, and the boost mode, the level of the output voltage VO can be varied within a wide range. According to some example embodiments, the reference voltage VREF may be a design parameter determined through empirical studies.

The switch circuit 11 may include a connection switch CSW. Although the connection switch CSW is implemented as an N-channel metal oxide semiconductor (NMOS) transistor in the embodiment illustrated in the drawings including fig. 1, this is only an exemplary embodiment and the inventive concept is not limited thereto. The connection switch CSW may be implemented as various semiconductor elements. Hereinafter, the connection switch CSW is a semiconductor element that can connect one end of each of the first and second flying capacitors CFa and CFb to the input node 13. The output terminal of the connection switch CSW may be branched to at least two current paths. For example, the current path may include a path of current that charges each of the first and second flying capacitors CFa and CFb and a path of the inductor current IL toward the inductor L. Although only one connection switch CSW is shown in fig. 1 for convenience of description, the switching circuit 11 may include more connection switches according to some example embodiments. According to some example embodiments, an appropriate switching control scheme may be applied to the switching circuit 11 in a particular operating mode to prevent or reduce excessive current flow in the connecting switch CSW. According to some example embodiments, an appropriate circuit configuration may be applied to the switching circuit 11 in a particular operating mode to prevent or reduce excessive current flow in the connecting switch CSW.

According to example embodiments, different switching control schemes may be used to control the switching circuit 11 according to the operation mode of the switching regulator 10, and thus the current flowing in the connection switch CSW may be prevented from exceeding a predetermined or determined level, or the occurrence of the current flowing in the connection switch CSW exceeding a predetermined or determined level may be reduced regardless of the operation mode (or the level of the output voltage VO) of the switching regulator 10. In other words, the current load on the connecting switch CSW is reduced, miniaturization of the connecting switch CSW can be achieved, design advantages of the switching regulator 10 can be brought about, and the switching regulator 10 can perform a reliable and efficient voltage conversion operation even at a high switching frequency, thereby widening the level range of the output voltage VO.

According to some embodiments, when the target level of the output voltage VO is equal to or higher than a reference level (e.g., a reference voltage level), the switching circuit 11 may be controlled by the controller 12 in a corresponding operation mode using a first switching control scheme. For example, when the target level of the output voltage VO is equal to or higher than the reference level, the controller 12 may set the switching regulator 10 in the second boost mode, and may provide the switching control signal CS _ SW generated based on the first switching control scheme to the switching circuit 11 to generate the target level of the output voltage VO. In some phases of the switching cycle, the switching circuit 11 may perform a switching operation based on the switching control signal CS _ SW, and may control the switching circuit 11 to output a current through one of a plurality of paths through the connection switch CSW. For example, the path may include a path toward each of the first and second flying capacitors CFa and CFb and a path toward the inductor L. According to some example embodiments, the reference level may be a design parameter determined through empirical studies.

According to some embodiments, when the target level of the output voltage VO is lower than the reference level, the switching circuit 11 may be controlled by the controller 12 in the corresponding operation mode using a second switching control scheme. For example, when the target level of the output voltage VO is lower than the reference level, the controller 12 may set the switching regulator 10 in the buck mode, the buck-boost mode, or the first boost mode according to the target level, and may provide the switching control signal CS _ SW generated based on the second switching control scheme to the switching circuit 11 to generate the output voltage VO of the target level. In some phases of the switching cycle, the switching circuit 11 may perform a switching operation based on the switching control signal CS _ SW, and may control the switching circuit 11 to output a current through at least two paths including the plurality of paths connecting the switch CSW.

As described above, when the target level of the output voltage VO is equal to or higher than the reference level (or when the switching regulator 10 operates in the second boost mode), the switching circuit 11 may be controlled using the first switching control scheme, thereby limiting the level of the current flowing in the connecting switch CSW. When the target level of the output voltage VO is lower than the reference level (or when the switching regulator 10 operates in the buck mode, the buck-boost mode or the first boost mode), the second switching control scheme may be used to control the switching circuit 11, since the level of the current flowing in the connecting switch CSW is not sufficient to trigger the limitation.

According to some example embodiments, the switching circuit 11 may provide the voltage boosted using the first flying capacitor CFa and the second flying capacitor CFb as the applied voltage VX to the inductor L in some phases of the switching cycle in a specific operation mode under the control of the controller 12. In some embodiments, the applied voltage VX can be about at least three times the input voltage VIN. However, this is only an example embodiment, and the inventive concept is not limited thereto. The switch circuit 11 can be connected to more flying capacitors and can supply a voltage boosted in proportion to the number of flying capacitors as the applied voltage VX to the inductor L. As described above, when the switching circuit 11 applies a voltage boosted to a high level to the inductor L in one phase of the switching cycle in a specific operation mode, the duration (or time) of the phase is reduced, and thus an important duration of the phase for charging each of the first and second flying capacitors CFa and CFb can be ensured, thereby allowing the level of the current passing through the connection switch CSW to charge each of the first and second flying capacitors CFa and CFb to be reduced. Thus, the current load on the connecting switch CSW can be reduced in the phase for charging each of the first and second flying capacitors CFa, CFb. This will be described in detail below with reference to the drawings including fig. 9.

Hereinafter, the operation of the switching regulator 10 will be described in detail.

The switching circuit 11 may receive the switch control signal CS _ SW from the controller 12 and may further include a plurality of switches that are turned on or off in response to the switch control signal CS _ SW. The switch circuit 11 may control the inductor current IL flowing through the inductor L by controlling the voltage supplied to the inductor L based on the switch control signal CS _ SW. For example, the switching circuit 11 may induce the inductor current IL in response to the switching control signal CS _ SW to charge the output capacitor CO, and may control the inductor current IL in response to the switching control signal CS _ SW to prevent the output capacitor CO from being overcharged or reduce the occurrence of overcharging of the output capacitor CO. When there is a load (e.g., load LD in fig. 4) that receives the output voltage VO of the switching regulator 10, at least a portion of the inductor current IL may be provided to the load. An example of the switch circuit 11 will be described below with reference to the drawings including fig. 4.

The inductor L and the output capacitor CO may be connected in series with each other and therefore the inductor current IL may be the same or substantially the same as the output transfer current ID when ignoring the current flow to the controller 12. The inductor current IL may depend on the voltage applied to the inductor L by the switching circuit 11 (e.g., VX in fig. 1). Here, the voltage of the node connected to the switching circuit 11 and the inductor L may be referred to as an applied voltage VX. In some embodiments, the capacitance of the output capacitor CO may be determined based on the current supplied to (or consumed by) the load connected to the output terminal 14 of the switching regulator 10. In some embodiments, the inductance of the inductor L may be determined based on the capacitance and/or switching frequency of the output capacitor CO. In some embodiments, the capacitance of the first and second flying capacitors CFa, CFb may be determined based on the current provided to the load, the switching frequency, the input voltage VIN, and/or the output voltage VO.

The controller 12 may generate the switch control signal CS _ SW based on the reference voltage VREF and the output voltage VO. For example, the controller 12 may generate a feedback voltage by dividing the output voltage VO using at least two resistors, compare the feedback voltage with the reference voltage VREF, and generate the switching control signal CS _ SW having an adjusted duty ratio such that the feedback voltage is equal to or close to the reference voltage VREF, wherein the duty ratio relates to on/off control. Accordingly, the level of the output voltage VO may be determined based on the level of the reference voltage VREF, and the level of the output voltage VO may be changed by changing the level of the reference voltage VREF. In some embodiments, to perform the above operations, the controller 12 may detect the inductor current IL or the output transfer current II) and generate the switch control signal CS _ SW based on the detected current level. In some embodiments, the controller 12 may generate the switch control signal CS _ SW based on the output voltage VO and the current of the output node 14. In some embodiments, the controller 12 may include at least one comparator and at least one logic gate.

The controller 12 may generate the switch control signal CS _ SW so that the switch circuit 11 and the first and second flying capacitors CFa and CFb connected to the switch circuit 11 function as a charge pump, and may supply the applied voltage VX boosted by the charge pump to the inductor L in one phase of the switching cycle. In some embodiments, the boost voltage may be a multiple of the input voltage VIN according to the connection between the switching circuit 11 and the first and second flying capacitors CFa, CFb. With such a configuration of the switching circuit 11, the output transfer current ID supplied to the output capacitor CO and the load can be continuously changed. With the continuous change of the output transfer current ID, the level of the output transfer current ID may be rapidly changed, and the noise of the output voltage VO may be reduced.

The output voltage VO generated by the switching regulator 10 may be used as a supply voltage to power electronic components, which may be referred to as a load of the switching regulator 10. For example, the output voltage VO may be provided to digital circuitry that processes digital signals, analog circuitry that processes analog signals, and/or Radio Frequency (RF) circuitry that processes RF signals.

Fig. 2A to 3B are schematic diagrams of a switching regulator according to an example embodiment. Specifically, fig. 2A and 2B are circuit diagrams showing the operation of the switching regulator 20 in the first operation MODE _1, and fig. 3A and 3B are circuit diagrams showing the operation of the switching regulator 20 in the second operation MODE _ 2. Hereinafter, when description is made with reference to fig. 2A to 3B, redundant description is omitted.

Referring to fig. 2A, switching regulator 20 may include a first switching circuit 21_1, a second switching circuit 21_2, a controller 22, an input node 23, an output node 24, a first flying capacitor CFa, a second flying capacitor CFb, an inductor L, and/or an output capacitor CO. First switch circuit 21_1 may include a first connection switch CSW1 and/or a plurality of switches, and may be connected to first flying capacitor CFa. First connection switch CSW1 may selectively connect one end of first flying capacitor CFa to input node 23. Second switch circuit 21_2 may include a second connection switch CSW2 and/or a plurality of switches, and may be connected to a second flying capacitor CFb. Second connection switch CSW2 may selectively connect one end of second flying capacitor CFb to input node 23. According to some example embodiments, operations described herein as being performed by the controller 22 may be performed by processing circuitry. According to some example embodiments, the operations described herein as being performed by the switching regulator 20 may be performed based on control signals generated by the controller 22.

According to an embodiment, the first and second switching circuits 21_1 and 21_2 may be connected in parallel to each other between the input node 23 and the inductor L. The controller 22 may individually control the first and second switching circuits 21_1 and 21_ 2. The first and second switching circuits 21_1 and 21_2 controlled using the interleaved switching control scheme when the switching regulator 20 operates in the first operation MODE _1 will be described below. It is assumed that the first operation MODE _1 is a MODE (for example, the second boosting MODE) set when the target level of the output voltage VO is equal to or higher than the reference level as described above. However, this is only an example embodiment, and the inventive concept is not limited thereto. The first operation MODE _1 may further include at least one of various operation MODEs including a buck-boost MODE and a first boost MODE.

In the first phase of the switching cycle, the first switching circuit 21_1 may be controlled based on the first switching control signal CS _ SW1 received from the controller 22 to pass a first current I11 through the first connection switch CSW1, wherein the first current I11 is used to supply the voltage boosted by the first flying capacitor CFa as the applied voltage VX to the inductor L. In the first phase, the second switch circuit 21_2 may be controlled to pass the second current 122 through the second connection switch CSW2 based on the second switch control signal CS _ SW2 received from the controller 22, wherein the second current I22 is used to charge the second flying capacitor CFb.

Referring to fig. 2B, in a second phase of the switching cycle, the first switching circuit 21_1 may be controlled based on the first switch control signal CS _ SW1 received from the controller 22 to pass a third current I12 through the first connection switch CSW1, wherein the third current I12 is used to charge the first flying capacitor CFa. In the second phase, the second switch circuit 21_2 may be controlled based on the second switch control signal CS _ SW2 received from the controller 22 to pass a fourth current I21 through the second connection switch CSW2, wherein the fourth current I21 is used to provide the voltage boosted by the second flying capacitor CFb as the applied voltage VX to the inductor L. As described above, the controller 22 performs the switch control such that each of the first connection switch CSW1 and the second connection switch CSW2 can pass the current (e.g., I11 and I22, or I12 and I21) through the corresponding path in the first phase and the second phase, respectively, thereby reducing the current load on each of the first connection switch CSW1 and the second connection switch CSW 2.

In an embodiment, according to the interleaved switching control scheme described with reference to fig. 2A and 2B, the phase in which the first flying capacitor CFa connected to the first switching circuit 21_1 is connected to the inductor L may be different from the phase in which the second flying capacitor CFb connected to the second switching circuit 21_2 is connected to the inductor L, and the phase in which the first flying capacitor CFa is charged using the input voltage VIN may be different from the phase in which the second flying capacitor CFb is charged using the input voltage VIN. In other words, the interleaved switching control scheme may refer to a method of controlling the first and second switching circuits 21_1 and 21_2 such that the first and second flying capacitors CFa and CFb are alternately charged using the input voltage BIN and the first and second flying capacitors CFa and CFb are alternately connected to the inductor L in different phases of the switching cycle.

The first and second switching circuits 21_1 and 21_2 controlled using the synchronous switching control scheme when the switching regulator 20 operates in the second operation MODE _2 will be described below with reference to fig. 3A and 3B. It is assumed that the second operation MODE _2 is a MODE (e.g., a buck MODE, a buck-boost MODE, or a first boost MODE) set when the target level of the output voltage VO is lower than the reference level as described above. However, this is only an example embodiment, and the inventive concept is not limited thereto. The second operation MODE _2 may include other operation MODEs than the first operation MODE _ 1.

Referring to fig. 3A, in a specific phase of the switching cycle, the first switching circuit 21_1 may be controlled to pass the first current I11 ' and the second current I12 ' through the first connection switch CSW1 based on the first switch control signal CS _ SW1 ' received from the controller 22. The first current I11 'is used to provide the input voltage VIN to the inductor L and the second current I12' is used to charge the first flying capacitor CFa. In the first phase, the second switch circuit 21_2 may be controlled to pass the third current I21 ' and the fourth current I22 ' through the second connection switch CSW2 based on the second switch control signal CS _ SW2 '. The third current I21 'is used to provide the input voltage VIN to the inductor L and the fourth current I22' is used to charge the second flying capacitor CFb. As described above, in the second operation MODE _2 in which the current load on each of the first and second connection switches CSW1 and CSW2 is not expected to be excessive, the controller 22 may perform switching control such that each of the first and second connection switches CSW1 and CSW2 may pass a current (e.g., I11 ', I12', I21 ', and I22') through a corresponding path in a stage.

The synchronous switching control scheme may refer to a method of identically or similarly controlling the first and second switching circuits 21_1 and 21_2 such that the first and second flying capacitors CFa and CFb are charged and/or connected to the inductor L in one stage.

Referring to fig. 3B, in some embodiments, when the switching regulator 20 is in the second operation MODE _2, the controller 22 may select one of the first and second switching circuits 21_1 and 21_2 and generate the output voltage VO using the selected switching circuit. Specifically, the controller 22 may select the first switch circuit 21_1 and provide the first switch control signal CS _ SW1 "to the first switch circuit 21_1, so that the first switch circuit 21_1 is controlled to pass the first current I11 'for providing the input voltage VIN to the inductor L and the second current I12' for charging the first flying capacitor CFa through the first connection switch CSW1 in a specific phase of the switching cycle. The controller 22 may disable the second switch circuit 21_2 (e.g., disconnect the second switch circuit 21_2 from the input voltage VIN and/or the inductor L) by providing the second switch control signal CS _ SW2 "to the second switch circuit 21_ 2. The switching regulator 20 may reduce power consumption by disabling the unselected switching circuits in the second operation MODE _ 2.

Fig. 4 is a block diagram of the switching regulator 20 according to an example embodiment.

Referring to fig. 4, the switching regulator 20 may include a first switching circuit 21_1, a second switching circuit 21_2, a controller 22, a first flying capacitor CFa, a second flying capacitor CFb, an inductor L, and/or an output capacitor CO. The load LD may be connected to the switching regulator 20. Redundant description that has already been given with reference to fig. 2A to 3B will be omitted. The switches shown in the drawings including fig. 4 may each have a structure that electrically connects or disconnects both ends according to a switch control signal (e.g., CS _ SW1 or CS _ SW2) supplied from the controller 22. The first switch SW1_1 of the first switch circuit 21_1 may correspond to the first connection switch CSW1 in fig. 2A, and the fifth switch SW2_1 may correspond to the second connection switch CSW2 in fig. 2A.

The first switch circuit 21_1 may include first to fourth switches SW1_1 to SW1_ 4. The first switch SW1_1 and the second switch SW1_2 may be sequentially connected in series between the input node and one end of the inductor L, and the third switch SW1_3 and the fourth switch SW1_4 may be sequentially connected in series between the input node and the ground node. The first flying capacitor CFa may have one end connected to the first switch SW1_1 and the second switch SW1_2 and one end connected to the third switch SW1_3 and the fourth switch SW1_ 4.

The second switch circuit 21_2 may include fifth to ninth switches SW2_1 to SW2_ 5. The fifth switch SW2_1 and the sixth switch SW2_2 may be sequentially connected in series between the input node and the inductor L, the seventh switch SW2_3 and the eighth switch SW2_4 may be sequentially connected in series between the input node and the ground node, and the ninth switch SW2_5 may be connected between one end of the sixth switch SW2_2 and the ground node. According to some example embodiments, as described below, the controller 22 may generate the first switch control signal CS _ SW1 and the second switch control signal CS _ SW2 such that the first flying capacitor CFa, the first switch circuit 21_1, the second flying capacitor CFb, and the second switch circuit 21_2 function as a charge pump. The controller 22 may generate the first and second switch control signals CS _ SW1 and CS _ SW2 such that the applied voltage VX boosted by the charge pump is applied to the inductor L.

In an embodiment, the controller 22 may control the first and second switching circuits 21_1 and 21_2 using different switching control schemes according to an operation mode of the switching regulator 20. In other words, the controller 22 may reduce the current load on the first switch SW1_1 of the first switch circuit 21_1 and the fifth switch SW2_1 of the second switch circuit 21_2 by limiting the current flowing in the first switch SW1_1 and the fifth switch SW2_1 in multiple phases of the switching cycle in the first operation mode (e.g., the second boost mode).

Fig. 5A to 5D are circuit diagrams of the switching regulator 20 operating in the second boost mode as the first operation mode according to example embodiments, and fig. 5E is a timing diagram illustrating an operation of the switching regulator 20 in the second boost mode according to some example embodiments, in which respective states of fig. 5A to 5D are sequentially repeated. Fig. 5A shows the switching regulator 20 in a first phase P1, fig. 5B shows the switching regulator 20 in a second phase P2, fig. 5C shows the switching regulator 20 in a third phase P3, and fig. 5D shows the switching regulator 20 in a fourth phase P4. In fig. 5A to 5D, paths through which current flows and switches in the on state are shown in bold.

Referring to fig. 5A, in the second boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1a and CS _ SW2a in the first phase P1 such that the second and third switches SW1_2 and SW1_3 of the first switch circuit 21_1 and the fifth and eighth switches SW2_1 and SW2_4 of the second switch circuit 21_2 are turned on and the other switches (e.g., the first switch SW1_1, the fourth switch SW1_4, the sixth switch SW2_2, the seventh switch SW2_3, and the ninth switch SW2_5) are turned off.

Both ends of the first flying capacitor CFa may be connected to the input node and the inductor L, respectively. The applied voltage VX boosted by the first flying capacitor CFa can be supplied to the inductor L through the second switch SW1_2 in the on state. Both ends of the second flying capacitor CFb may be connected to the input node and the ground node, respectively, and the second flying capacitor CFb may be charged with the input voltage VIN. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the third switch SW1_3, the first flying capacitor CFa, and the second switch SW1_ 2. Accordingly, as shown in fig. 5E, the inductor current IL may gradually increase in the first phase P1, and the applied voltage VX provided to the inductor L may be equal to or close to the boost voltage, e.g., equal to about twice the input voltage VIN.

Referring to fig. 5B, in the second boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1B and CS _ SW2B in the second stage P2 such that the first and second switches SW1_1 and SW1_2 of the first switch circuit 21_1 and the fifth and eighth switches SW2_1 and SW2_4 of the second switch circuit 21_2 are turned on and the other switches (e.g., the third, fourth, sixth, seventh and ninth switches SW1_3, SW1_4, SW2_2, SW2_3 and SW2_5) are turned off.

In the second phase P2, both ends of the first flying capacitor CFa may float and both ends of the second flying capacitor CFb may be connected to the input node and the ground node, respectively, as in the first phase P1, and thus the second flying capacitor CFb may be charged with the input voltage VIN. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first switch SW1_1 and the second switch SW1_2 in an on state. Accordingly, as shown in fig. 5E, the inductor current IL may gradually decrease in the second phase P2, and the applied voltage VX provided to the inductor L may be equal to or close to the input voltage VIN.

Referring to fig. 5C, in the second boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1C and CS _ SW2C in the third stage P3 such that the first and fourth switches SW1_1 and SW1_4 of the first switch circuit 21_1 and the sixth and seventh switches SW2_2 and SW2_3 of the second switch circuit 21_2 are turned on and the other switches (e.g., the second switch SW1_2, the third switch SW1_3, the fifth switch SW2_1, the eighth switch SW2_4, and the ninth switch SW2_5) are turned off.

Both ends of the first flying capacitor CFa may be connected to the input node and the ground node, respectively, and the first flying capacitor CFa may be charged with the input voltage VIN. Both ends of the second flying capacitor CFb may be connected to the input node and the inductor L, respectively, and the applied voltage VX boosted by the second flying capacitor CFb is supplied to the inductor L through the sixth switch SW2_2 in a turned-on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the seventh switch SW2_3, the second flying capacitor CFb, and the sixth switch SW2_ 2. Accordingly, as shown in fig. 5E, the inductor current IL may gradually increase in the third stage P3, and the applied voltage VX provided to the inductor L may be equal to or close to the boost voltage, e.g., equal to a voltage of about twice the input voltage VIN.

Referring to fig. 5D, in the second boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1D and CS _ SW2D in the fourth stage P4 such that the first and fourth switches SW1_1 and SW1_4 of the first switch circuit 21_1 and the fifth and sixth switches SW2_1 and SW2_2 of the second switch circuit 21_2 are turned on and the other switches (e.g., the second, third, seventh, eighth, and ninth switches SW1_2, SW1_3, SW2_3, SW2_4 and SW2_5) are turned off.

In the fourth phase P4, both ends of the first flying capacitor CFa may be connected to the input node and the ground node, respectively, as in the third phase P3, and thus the first flying capacitor CFa may be charged with the input voltage VIN. Both ends of the second flying capacitor CFb may float. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the fifth switch SW2_1 and the sixth switch SW2_2 in an on state. Therefore, as shown in fig. 5E, the inductor current IL may gradually decrease in the fourth phase P4, and the applied voltage VX supplied to the inductor L may be equal to or close to the input voltage VIN.

As described above, in the second boost mode, the controller 22 may control the first and second switching circuits 21_1 and 21_2 based on an interleaved switching control scheme such that the first and second flying capacitors CFa and CFb are alternately charged and connected to the inductor L in different phases. The operation of the switching regulator 20 shown in fig. 5A to 5D in the first to fourth phases P1 to P4 is only an example embodiment, and the inventive concept is not limited thereto. The operation of the switching regulator 20 of fig. 5B in the second stage P2 may be replaced with the operation of the switching regulator 20 of fig. 5D, and the operation of the switching regulator 20 of fig. 5D in the fourth stage P4 may be replaced with the operation of the switching regulator 20 of fig. 5B.

Fig. 6A and 6B are circuit diagrams of the switching regulator 20 operating in the step-down mode as the second operation mode according to example embodiments, and fig. 6C is a timing chart showing the operation of the switching regulator 20 in the step-down mode, in which the respective states of fig. 6A and 6B are repeated. Fig. 6A shows the switching regulator 20 in the first stage P1, and fig. 6B shows the switching regulator 20 in the second stage P2. In fig. 6A and 6B, a path through which a current flows and a switch in an on state are shown in bold.

Referring to fig. 6A, in the buck mode, the controller 22 may generate the first and second switch control signals CS _ SW1a and CS _ SW2a in the first phase P1 such that the first, second, and fourth switches SW1_1, SW1_2, and SW1_4 of the first switch circuit 21_1 and the fifth, sixth, and eighth switches SW2_1, SW2_2, and SW2_4 of the second switch circuit 21_2 are turned on, and the other switches (e.g., the third, seventh, and ninth switches SW1_3, SW2_3, and SW2_5) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the ground node, respectively. The inductor L may be connected to the input node through the first and second switching circuits 21_1 and 21_2 and thus receive the applied voltage VX corresponding to the input voltage VIN. Unlike fig. 5A to 5D, in fig. 6A, the current for charging the first flying capacitor CFa and the current flowing to the inductor L may flow through the first switch SW1_1 simultaneously or both, and the current for charging the second flying capacitor CFb and the current flowing to the inductor L may flow through the fifth switch SW2_1 simultaneously or both. Therefore, as shown in fig. 6C, the inductor current IL may gradually increase, and the applied voltage VX may be equal to or close to the input voltage VIN.

Referring to fig. 6B, in the buck mode, the controller 22 may generate the first and second switch control signals CS _ SW1B and CS _ SW2B in the second stage P2 such that the first and fourth switches SW1_1 and SW1_4 of the first switch circuit 21_1 and the fifth, eighth and ninth switches SW2_1, SW2_4 and SW2_5 of the second switch circuit 21_2 are turned on and the other switches (e.g., the second, third, sixth and seventh switches SW1_2, SW1_3, SW2_2 and SW2_3) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the ground node, respectively. The inductor L may be connected to the ground node through the second switching circuit 21_2 and thus receive the applied voltage VX corresponding to the ground voltage. Therefore, as shown in fig. 6C, the inductor current IL may gradually decrease, and the applied voltage VX may be equal to or close to the ground voltage.

Fig. 7A to 7C are circuit diagrams of the switching regulator 20 operating in a buck-boost mode as a second operation mode according to example embodiments, and fig. 7D is a timing diagram illustrating an operation of the switching regulator 20 in the buck-boost mode according to some example embodiments, in which respective states of fig. 7A to 7C are sequentially repeated. Fig. 7A shows the switching regulator 20 in a first phase P1, fig. 7B shows the switching regulator 20 in a second phase P2, and fig. 7C shows the switching regulator 20 in a third phase P3. In fig. 7A to 7C, a path through which a current flows and a switch in an on state are shown in bold.

Referring to fig. 7A, in the buck-boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1a and CS _ SW2a in the first phase P1 such that the second and third switches SW1_2 and SW1_3 of the first switch circuit 21_1 and the sixth and seventh switches SW2_2 and SW2_3 of the second switch circuit 21_2 are turned on and the other switches (e.g., the first switch SW1_1, the fourth switch SW1_4, the fifth switch SW2_1, the eighth switch SW2_4, and the ninth switch SW2_5) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the inductor L, respectively. The applied voltage VX boosted by the first flying capacitor CFa and the second flying capacitor CFb can be supplied to the inductor L through the second switch SW1_2 and the sixth switch SW2_2 in the on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first and second switching circuits 21_1 and 21_ 2. Accordingly, as shown in fig. 7D, the inductor current IL may gradually increase in the first phase P1, and the applied voltage VX supplied to the inductor L may be equal to or close to the boost voltage, e.g., equal to a voltage of about twice the input voltage VIN.

Referring to fig. 7B, in the buck-boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1B and CS _ SW2B in the second stage P2 such that the first, second, and fourth switches SW1_1, SW1_2, and SW1_4 of the first switch circuit 21_1 and the fifth, sixth, and eighth switches SW2_1, SW2_2, and SW2_4 of the second switch circuit 21_2 are turned on, and the other switches (e.g., the third, seventh, and ninth switches SW1_3, SW2_3, and SW2_5) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the ground node, respectively, and the first and second flying capacitors CFa and CFb may be charged using the input voltage VIN. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first and second switching circuits 21_1 and 21_ 2. Accordingly, as shown in fig. 7D, the inductor current IL may remain substantially constant in the second phase P2, and the applied voltage VX may be equal to or close to the input voltage VIN.

Referring to fig. 7C, in the buck-buck mode, the controller 22 may generate the first and second switch control signals CS _ SW1C and CS _ SW2C in the third stage P3 such that the first and fourth switches SW1_1 and SW1_4 of the first switch circuit 21_1 and the fifth, eighth and ninth switches SW2_1, SW2_4 and SW2_5 of the second switch circuit 21_2 are turned on and the other switches (e.g., the second, third, sixth and seventh switches SW1_2, SW1_3, SW2_2 and SW2_3) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the ground node, respectively. The inductor L may be connected to the ground node through the second switching circuit 21_2 and may receive the applied voltage VX corresponding to the ground voltage. Therefore, as shown in fig. 7D, the inductor current IL may gradually decrease, and the applied voltage VX may be equal to or close to the ground voltage.

As described above, the controller 22 can control the connection relationship of the first flying capacitor CFa and the connection relationship of the second flying capacitor CFb identically or similarly in one phase during the buck mode, and can generate the output voltage VO lower than the input voltage VIN.

Fig. 8A to 8B are circuit diagrams of the switching regulator 20 operating in the first boosting mode as the second operation mode according to example embodiments, and fig. 8C is a timing diagram illustrating an operation of the switching regulator 20 of fig. 8A and 8B according to some example embodiments. Fig. 8A shows the switching regulator 20 in the first stage P1, and fig. 8B shows the switching regulator 20 in the second stage P2. In fig. 8A and 8B, a path through which a current flows and a switch in an on state are shown in bold.

Referring to fig. 8A, in the first boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1a and CS _ SW2a in the first phase P1 such that the second and third switches SW1_2 and SW1_3 of the first switch circuit 21_1 and the sixth and seventh switches SW2_2 and SW2_3 of the second switch circuit 21_2 are turned on and the other switches (e.g., the first switch SW1_1, the fourth switch SW1_4, the fifth switch SW2_1, the eighth switch SW2_4, and the ninth switch SW2_5) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the inductor L, respectively. The applied voltage VX boosted by the first flying capacitor CFa and the second flying capacitor CFb can be supplied to the inductor L through the second switch SW1_2 and the sixth switch SW2_2 in the on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first and second switching circuits 21_1 and 21_ 2. Therefore, as shown in fig. 8C, the inductor current IL may gradually increase in the first stage P1, and the applied voltage VX supplied to the inductor L may be equal to or close to the boost voltage, e.g., equal to a voltage of about twice the input voltage VIN.

Referring to fig. 8B, in the first boost mode, the controller 22 may generate the first and second switch control signals CS _ SW1B and CS _ SW2B in the second stage P2 such that the first, second, and fourth switches SW1_1, SW1_2, and SW1_4 of the first switch circuit 21_1 and the fifth, sixth, and eighth switches SW2_1, SW2_2, and SW2_4 of the second switch circuit 21_2 are turned on, and the other switches (e.g., the third, seventh, and ninth switches SW1_3, SW2_3, and SW2_5) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the ground node, respectively, and the first and second flying capacitors CFa and CFb may be charged using the input voltage VIN. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the first and second switching circuits 21_1 and 21_ 2. Therefore, as shown in fig. 8C, the inductor current IL may gradually decrease in the second phase P2, and the applied voltage VX may be equal to or close to the input voltage VIN.

As described above with reference to fig. 6A to 8C, the controller 22 may control the first switch circuit 21_1 and the second switch circuit 21_2 based on a synchronous switch control scheme such that the connection structure of the first flying capacitor CFa is the same as or similar to that of the second flying capacitor CFb in one stage.

Although fig. 5E, 6C, 7D, and 8C show phases having the same period or similar periods in one switching cycle, this is for convenience of explanation only. The phases may have different periods from each other. For example, the period of each of the first and third stages P1 and P3 in fig. 5E may be longer than the period of the first stage P1 in fig. 8C. Accordingly, the period of each of the second and fourth stages P2 and P4 in fig. 5E may be shorter than that of the second stage P2 in fig. 8C. In other words, the period of each of the first and third stages P1 and P3 in fig. 5E (or the period of the first stage P1 in fig. 8C) may be proportional to the duty ratio, and the controller 22 may control the first and second switching circuits 21_1 and 21_2 based on the duty ratio in the second boosting mode that is greater than the duty ratio in the first boosting mode.

Fig. 9 is a circuit diagram of the switching regulator 30 according to an example embodiment.

Referring to fig. 9, switching regulator 30 may include a switching circuit 31, a controller 32, a first flying capacitor CFa, a second flying capacitor CFb, an inductor L, and/or an output capacitor CO. The load LD may be connected to the switching regulator 30. The first switch SW1 of the switch circuit 31 may correspond to the connection switch CSW in fig. 1.

The switch circuit 31 may include first to ninth switches SW1 to SW 9. The first switch SW1 and the fourth switch SW4 may be sequentially connected in series between the input node and the inductor L, and one end of each of the sixth switch SW6 to the eighth switch SW8 may be connected to the input node. The other end of the sixth switch SW6 may be connected to one end of the first flying capacitor CFa. The other end of the seventh switch SW7 may be connected to one end of the second flying capacitor CFb. The other terminal of eighth switch SW8 may be connected to the other terminal of second flying capacitor CFb. A third switch SW3 may be connected between the other end of the second flying capacitor CFb and the ground node. A second switch SW2 may be connected between one end of the first flying capacitor CFa and one end of the second flying capacitor CFb. A fifth switch SW5 may be connected between one end of the first flying capacitor CFa and the ground node. The ninth switch SW9 may be connected between one end of the inductor L and the ground node. As described below, controller 32 may generate switch control signal CS _ SW such that first flying capacitor CFa, second flying capacitor CFb, and switch circuit 31 function as a charge pump. The controller 32 may generate the switch control signal CS _ SW such that the applied voltage VX boosted by the charge pump is applied to the inductor L. According to some example embodiments, operations described herein as being performed by the controller 32 may be performed by processing circuitry. According to some example embodiments, the operations described herein as being performed by the switching regulator 30 may be performed based on control signals generated by the controller 32.

In an embodiment, controller 32 may generate switch control signal CS _ SW such that an applied voltage VX boosted to three times input voltage VIN using first and second flying capacitors CFa and CFb is applied to inductor L. However, this is only an example embodiment, and the inventive concept is not limited thereto. Switching regulator 30 may have a configuration that includes more flying capacitors and switches and allows a boost voltage (e.g., an applied voltage VX equal to N times input voltage VIN, where N is an integer equal to or greater than 4) to be applied to inductor L. Hereinafter, the description will focus on the case where the switching regulator 30 operates in the second boosting mode, but it should be understood that the switching regulator 30 may operate in various modes.

Fig. 10A and 10B are circuit diagrams of the switching regulator 30 operating in the second boost mode according to example embodiments, and fig. 10C is a timing diagram illustrating the operation of the switching regulator 30 of fig. 10A and 10B according to some example embodiments. Fig. 10A shows the switching regulator 30 in the first stage P1, and fig. 10B shows the switching regulator 30 in the second stage P2. In fig. 10A and 10B, a path through which a current flows and a switch in an on state are shown in bold.

Referring to fig. 10A, in the second boost mode, the controller 32 may generate the switch control signal CS _ SWa in the first phase P1 such that the second switch SW2, the fourth switch SW4, and the eighth switch SW8 of the switch circuit 31 are turned on and the other switches (e.g., the first switch SW1, the third switch SW3, the fifth switch SW5, the sixth switch SW6, the seventh switch SW7, and the ninth switch SW9) are turned off.

The second flying capacitor CFb and the first flying capacitor CFa may be sequentially connected in series between the input node and the inductor L. The applied voltage VX boosted by the first flying capacitor CFa and the second flying capacitor CFb can be supplied to the inductor L through the second switch SW2, the fourth switch SW4, and the eighth switch SW8 in the on state. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the switching circuit 31. Therefore, as shown in fig. 10C, the inductor current IL may gradually increase in the first stage P1, and the applied voltage VX supplied to the inductor L may be equal to or close to the boost voltage, for example, a voltage equal to about three times the input voltage VIN.

Referring to fig. 10B, in the second boosting mode, the controller 32 may generate the switch control signal CS _ SWb in the second stage P2 such that the first switch SW1, the third switch SW3, the fourth switch SW4, the fifth switch SW5, and the seventh switch SW7 of the switch circuit 31 are turned on, and the other switches (e.g., the second switch SW2, the sixth switch SW6, the eighth switch SW8, and the ninth switch SW9) are turned off.

Both ends of each of the first and second flying capacitors CFa and CFb may be connected to the input node and the ground node, respectively, and the first and second flying capacitors CFa and CFb may be charged using the input voltage VIN. The inductor current IL may flow from the input node to the output capacitor CO and the load LD through the switching circuit 31. Therefore, as shown in fig. 10C, the inductor current IL may gradually decrease, and the applied voltage VX may be equal to or close to the input voltage VIN.

As described above with reference to fig. 10A, the applied voltage VX equal to three times the input voltage VIN may be supplied to the inductor L in the first phase P1, and thus the period of the first phase P1 may be reduced. In other words, as the level of the applied voltage VX supplied to the inductor L increases in the first stage P1, the period of the first stage P1 may decrease. For example, the period of the first phase P1 in fig. 10C may be shorter than the period of each of the first phase P1 and the third phase P3 in fig. 5E. Accordingly, the period of the second phase in fig. 10C may be longer than the period of each of the second phase P2 and the fourth phase P4 in fig. 5E, and thus the charging times of the first flying capacitor CFa and the second flying capacitor CFb may be sufficiently ensured in the second phase P2 of fig. 10B. Therefore, an abnormally excessive current may be prevented from flowing into the first switch SW1, or an occurrence of an abnormally excessive current flowing into the first switch SW1 may be reduced.

Fig. 11 is a circuit diagram of the switching regulator 30 according to an example embodiment.

Referring to fig. 11, the switching regulator 30 may include a first switching circuit 31_1, a second switching circuit 31_2, a controller 32, an inductor L, an output capacitor CO, and/or first to fourth flying capacitors CFa1, CFa2, CFb1, and CFb 2. The load LD may be connected to the switching regulator 30. The first switch SW11 of the first switch circuit 31_1 and the tenth switch SW21 of the second switch circuit 31_2 may correspond to the first connection switch CSW1 and the second connection switch CSW2 in fig. 2A to 2B, respectively.

The first switch circuit 31_1 may include first to ninth switches SW11 to SW19 (e.g., SW11, SW12, SW13, SW14, SW15, SW16, SW17, SW18, and SW19) and may be connected to the first and second flying capacitors CFa1 and CFb 1. The second switch circuit 31_2 may include tenth to eighteenth switches SW21 to SW29 (e.g., SW21, SW22, SW23, SW24, SW25, SW26, SW27, SW28, and SW29) and may be connected to the third and fourth flying capacitors CFa2 and CFb 2. The structures of the first and second switch circuits 31_1 and 31_2 are the same as or similar to those of the switch circuit 31 that has been described in detail with reference to fig. 9, and therefore redundant description will be omitted.

The controller 32 may control the first and second switching circuits 31_1 and 31_2 using different switching control schemes according to the operation mode of the switching regulator 30. In an embodiment, the controller 32 may control the first and second switch circuits 31_1 and 31_2 based on an interleaved switching control scheme in the first operation mode such that the first to fourth flying capacitors CFa1, CFa2, CFb1 and CFb2 are alternately charged and connected to the inductor L in different phases. The controller 32 may control the first and second switching circuits 31_1 and 31_2 identically or similarly based on a synchronous switching control scheme in the second operation mode. Since a detailed description thereof has been given with reference to the drawings including fig. 4, redundant description will be omitted.

Fig. 12 is a table of conditions for setting an operation mode of a switching regulator according to an example embodiment. Hereinafter, for clarity, it is assumed that "a" is 0.1 and "b" is 0.5. However, this is merely an example for explanation, and "a" and "b" are not limited thereto and may be variously set.

Referring to fig. 12, when the target level of the output voltage VO is less than (1-a) times the input voltage VIN, the switching regulator may be set in the step-down mode. The switching regulator may be set in the buck-boost mode when the target level of the output voltage VO is equal to or greater than (1-a) times and less than (1+ a) times the input voltage VIN. The switching regulator may be disposed in the first boost mode when the target level of the output voltage VO is equal to or greater than (1+ a) times and less than (1+ b) times the input voltage VIN. When the target level of the output voltage VO is equal to or greater than (1+ b) times the input voltage VIN, the switching regulator may be disposed in the second boost mode.

In an embodiment, when the switching regulator is set in the second boost mode, the switching of the switching regulator may be controlled based on an interleaved switching control scheme. When the switching regulator is set in the first boost mode, the buck mode, or the buck-boost mode, the switching of the switching regulator may be controlled based on a synchronous switching control scheme. However, this is only an example embodiment, and the inventive concept is not limited thereto. When the switching regulator is set in the first boost mode, the switching of the switching regulator may be controlled based on an interleaved switching control scheme. Further, the switching regulator may be set in more various operation modes, and a variety of switching control schemes may be used to reduce the current load on the connection switch according to the operation modes.

Fig. 13 is a flow chart of a method of operating a switching regulator according to an example embodiment.

Referring to fig. 13, the switching regulator may identify a target level of an output voltage in operation S100. In operation S120, an operation mode of the switching regulator may be set based on a target level of the output voltage. In operation S140, the switching regulator may generate an output voltage by performing a voltage conversion operation based on a switching control scheme corresponding to an operation mode.

Fig. 14 is a detailed flowchart of operation S140 in fig. 13 according to an example embodiment.

Referring to fig. 14, after operation S120 (fig. 13), the switching regulator may check whether the switching regulator is set in the second boosting mode in operation S142. When the switching regulator is in the second boosting mode in operation S142 (e.g., in the case of yes), the switching regulator may perform a voltage conversion operation based on the interleaved switching control scheme in operation S144. When the switching regulator is not in the second boosting mode in operation S142 (e.g., in the case of no), the switching regulator may perform a voltage conversion operation based on the synchronous switching control scheme in operation S146.

Fig. 15 is a schematic diagram of a system 100 according to an example embodiment. System 100 may be implemented in some embodiments as a single semiconductor integrated circuit, such as a system on a chip (SoC), or may include a Printed Circuit Board (PCB) and a package mounted on the PCB in some embodiments. As shown in fig. 15, the system 100 may include first through fourth functional blocks 110-140 (e.g., the first, second, third, and fourth functional blocks 110, 120, 130, 140) and/or a Power Management Integrated Circuit (PMIC) 150.

Each of the first through fourth functional blocks 110 through 140 may operate based on power supplied from a corresponding one of first through fourth power supply voltages VDD1 through VDD4 (e.g., VDD1, VDD2, VDD3, and VDD4) output from the PMIC 150. For example, at least one of the first through fourth functional blocks 110 through 140 may include a digital circuit that processes a digital signal, such as an Application Processor (AP), or an analog circuit that processes an analog signal, such as an amplifier. At least one of the first through fourth functional blocks 110 through 140 may include a circuit, such as an analog-to-digital converter (ADC), that processes the mixed signal. Although in fig. 15 system 100 includes four functional blocks, in some embodiments, system 100 may include fewer or more functional blocks.

The PMIC 150 may generate the first to fourth power voltages VDD1 to VDD4 according to the input voltage VIN and change a level of at least one of the first to fourth power voltages VDD1 to VDD4 in response to the voltage control signal C _ V. At least one of the first through fourth functional blocks 110 through 140 may receive a power supply voltage having a level that dynamically varies with performance and power consumption of the at least one of the first through fourth functional blocks 110 through 140. For example, the first functional block 110 may include an image processor that processes image data. The first functional block 110 may receive the first power voltage VDD1 having a high level when processing video including a series of images. The first functional block 110 may receive the first power voltage VDD1 having a low level when processing a photograph including a single image. The PMIC 150 may receive the voltage control signal C _ V corresponding to the performance and power consumption of the first functional block 110, and may increase or decrease the level of the first power supply voltage VDD1 based on the voltage control signal C _ V. As described above, the method of dynamically changing the level of the power supply voltage of the functional block may be referred to as dynamic voltage scaling.

The PMIC 150 may include any of the switching regulators (e.g., switching regulator 10, switching regulator 20, and/or switching regulator 30) that have been described above with reference to the figures. According to some example embodiments, the PMIC 150 may generate the first to fourth power supply voltages VDD1 to VDD4 according to the input voltage VIN, and change a level of at least one of the first to fourth power supply voltages VDD1 to VDD4 in response to the voltage control signal C _ V using a switching regulator. Accordingly, when the first power voltage VDD1 is maintained at a certain level, the first power voltage VDD1 may have reduced noise. Since noise in the first power supply voltage VDD1 is reduced, operational reliability of the first functional block 110 and the system 100 may be improved. In addition, the level of the first power supply voltage VDD1 may be changed rapidly. In some embodiments, the first functional block 110 may stop operating while the level of the first power supply voltage VDD1 is being changed, and may resume operating after the level of the first power supply voltage VDD1 is changed. Accordingly, when the level of the first power voltage VDD1 is rapidly changed, the operation time of the first functional block 110 may be reduced. Thus, the system 100 may provide improved performance. In addition, the PMIC 150 may include elements (e.g., connection switches) having a reduced size, and thus the PMIC 150 may be easily integrated with the first through fourth functional blocks 110 through 140 in a single package.

Fig. 16 is a block diagram of a wireless communication device 200 according to an example embodiment. In particular, fig. 16 shows a User Equipment (UE) (or user terminal) powered by a battery 250. In some embodiments, the wireless communication device 200 may be included in a wireless communication system, such as a fifth generation (5G) or Long Term Evolution (LTE), using a cellular network, a Wireless Local Area Network (WLAN) system, or another wireless communication system. In the wireless communication device 200, a switching regulator according to example embodiments may be used to supply variable power to a Power Amplifier (PA) 216. As shown in fig. 16, the wireless communication device 200 may include a transceiver 210, a baseband processor 220, an antenna 230, a power circuit 240, and/or a battery 250.

The transceiver 210 may include an antenna Interface (IF) circuit 211, a receiver, and/or a transmitter. The receiver may include input circuitry 212, a Low Noise Amplifier (LNA)213, and/or Receiver (RX) circuitry 214. The transmitter may include Transmitter (TX) circuitry 215, PA 216, and/or output circuitry 217. The antenna IF circuit 211 may connect the transmitter and/or receiver to the antenna 230 according to TX mode and/or RX mode. In some embodiments, input circuit 212 may include a matching circuit or filter, LNA 213 may amplify the output signal of input circuit 212, and/or RX circuit 214 may include a mixer for down-conversion. In some embodiments, TX circuitry 215 may include a mixer for frequency upconversion, PA 216 may amplify the output signal of TX circuitry 215, and/or output circuitry 217 may include a matching circuit and/or a filter.

The baseband processor 220 may transmit and/or receive baseband signals to and/or from the transceiver 210 and may perform modulation, demodulation, encoding, and/or decoding. In some embodiments, the baseband processor 220 may be referred to as a modem. The baseband processor 220 may generate a SET signal SET for setting the average power tracking mode and/or the envelope tracking mode and/or for varying the level of the output voltage VO.

Power supply circuit 240 may receive an input voltage VIN from battery 250 and generate an output voltage VO that powers PA 216. The power supply circuit 240 may include any of the switching regulators (e.g., the switching regulator 10, the switching regulator 20, and/or the switching regulator 30) that have been described above with reference to the drawings, and may enable the level of the output voltage VO to be changed quickly and to be stabilized. According to some example embodiments, the power supply circuit 240 generates the output voltage VO from the input voltage VIN, and enables a level of the output voltage VO to be rapidly changed and maintained stable by using the switching regulator.

While the inventive concept has been particularly shown and described with reference to embodiments thereof, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.