阅读说明：本技术 用于驱动电容性负载的驱动器 (Driver for driving capacitive load ) 是由 P·库马尔 Y·达瓦赫卡 于 2019-02-13 设计创作，主要内容包括：一种电路包括第一双极结型晶体管(BJT)(Q1)和第二BJT(Q2)。第一BJT(Q1)包括第一基极、第一集电极和第一发射极。第一集电极连接到第一电源电压节点(115)。第二BJT(Q2)包括第二基极、第二集电极和第二发射极。第二集电极在输出节点(118)处连接到第一发射极。该电路还包括电容器(CI),该电容器包括第一电容器端子和第二电容器端子。第一电容器端子连接到第二BJT(Q2)的第二发射极,并且第二电容器端子连接到第二电源电压节点(116)。电流源器件(II)与电容器(CI)并联连接。(A circuit includes a first Bipolar Junction Transistor (BJT) (Q1) and a second BJT (Q2). A first BJT (Q1) includes a first base, a first collector, and a first emitter. The first collector is connected to a first supply voltage node (115). A second BJT (Q2) includes a second base, a second collector, and a second emitter. The second collector is connected to the first emitter at an output node (118). The circuit further comprises a Capacitor (CI) comprising a first capacitor terminal and a second capacitor terminal. The first capacitor terminal is connected to a second emitter of a second BJT (Q2), and the second capacitor terminal is connected to a second supply voltage node (116). The current source device (II) is connected in parallel with the Capacitor (CI).)

1. A circuit, comprising:

a first bipolar junction transistor (first BJT) comprising a first base, a first collector and a first emitter, the first collector connected to a first supply voltage node;

a second BJT comprising a second base, a second collector and a second emitter, the second collector connected to the first emitter at an output node;

a capacitor comprising a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node; and

a current source device connected in parallel with the capacitor.

2. The circuit of claim 1, wherein the first BJT is an NPN BJT.

3. The circuit of claim 1, further comprising a control circuit coupled to receive a first periodic control signal to be provided to the first base and to generate a second periodic control signal to be provided to the second base based on the received first periodic control signal, wherein the first and second periodic control signals have the same frequency but are complementary to each other.

4. The circuit of claim 3, wherein the magnitude of the current generated by the current source device fully discharges the capacitor for a period of time approximately half a period of the first periodic control signal when the second BJT is turned off.

5. The circuit of claim 3, wherein:

during a rising time of a rising edge of the first periodic control signal, the first BJT is turned on, thereby causing a charging current to flow through the first BJT to the output node; and is

When the second periodic control signal is low, the second BJT is turned off, thereby discharging the charge on the capacitor through the current source device.

6. The circuit of claim 5, further comprising a capacitive load connected to the output node, and a charging current through the first BJT flows to the capacitive load.

7. The circuit of claim 5, the second BJT being conductive during a rise time of a rising edge of the second periodic signal, thereby causing current to flow from the output node to both the capacitor and the current source device.

8. The circuit of claim 7, wherein the current source device provides a current having a magnitude that is less than a magnitude of the charging current flowing through the first BJT to the output node.

9. The circuit of claim 1, further comprising a semiconductor die, wherein the capacitor and the first BJT and the second BJT are formed on the semiconductor die.

10. The circuit of claim 9, wherein:

the capacitor is adjustable;

the circuit includes a register bank capable of storing a first value and a second value therein; and is

The circuit includes a control circuit that reads the first and second values from the register bank and adjusts the capacitor using the first and second values.

11. The circuit of claim 9, wherein:

the capacitor has a fixed capacitance value;

the circuit includes a register bank in which values can be stored; and is

The circuit includes a control circuit that reads the value from the register set and uses the value to adjust a magnitude of a voltage of a control signal to be provided to the second base.

12. A circuit, comprising:

a first bipolar junction transistor (first BJT) comprising a first base, a first collector, and a first emitter, the first collector connected to a first supply voltage node, and the first base coupled to receive a first control signal;

a second BJT comprising a second base, a second collector and a second emitter, the second collector connected to the first emitter at an output node;

a capacitor comprising a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT and the second capacitor terminal connected to a second supply voltage node;

a current source device connected in parallel with the capacitor; and

a control circuit coupled to receive the first control signal for the first base and inverted from a logic state of the first control signal to generate a second control signal for the second base.

13. The circuit of claim 12, further comprising a set of programmable registers accessible to the control circuit, the set of programmable registers being programmed with adjustment values, wherein the control circuit reads the adjustment values from the registers and adjusts the electrical characteristic of the circuit based on at least one of the adjustment values.

14. The circuit of claim 13, wherein the adjustment value comprises at least one of:

a value indicating a period of the first control signal;

a value indicative of a rise time or a fall time of the first control signal;

a value indicative of a capacitance of the capacitive load;

a value indicative of a current through the first BJT when charging the capacitive load; and

a value indicative of a peak-to-peak voltage of the first control signal.

15. The circuit of claim 13, wherein the electrical characteristic comprises at least one of:

a peak-to-peak voltage based on the second control signal;

a magnitude of a current through the current source device; and

the capacitance of the capacitor.

16. The circuit of claim 12, wherein:

when the first control signal is asserted as a first logic state and the second control is asserted as a second logic state, the first BJT is turned on to conduct current from the first power supply node to the output node, and the second BJT is turned off, and the capacitor is discharged through the current source device; and

during at least a portion of the time that the first control signal is asserted to the second logic state and the second control is asserted to the first logic state, the first BJT is turned off, the second BJT is turned on, and a discharge current flows into the output node and through the second BJT and is divided between the current source device and the capacitor.

17. A circuit, comprising:

a first bipolar junction transistor (first BJT) comprising a first base, a first collector and a first emitter, the first collector connected to a first supply voltage node;

a second BJT comprising a second base, a second collector and a second emitter, the second collector connected to the first emitter at an output node;

a current source device connected to the second emitter at a second node and configured to be coupled to a capacitor in parallel with the current source device at the second node; and

a control circuit coupled to receive a first control signal for the first base and inverted from a logic state of the first control signal to generate a second control signal for the second base.

18. The circuit of claim 17, further comprising a set of programmable registers accessible to the control circuit, the set of programmable registers being programmed with adjustment values, wherein the control circuit reads the adjustment values from the registers and adjusts the peak-to-peak voltage of the second control signal based on at least one of the adjustment values.

19. The circuit of claim 18, wherein the at least one of the adjustment values comprises a first value indicative of a peak-to-peak voltage of the first control signal, and at least another one of the adjustment values comprises a second value for adjusting the current source device.

20. The circuit of claim 18, wherein the first BJT, the second BJT, the current source device, and the control circuit are fabricated on a same semiconductor die, and the capacitor is not fabricated on the same semiconductor die.

21. The circuit of claim 17, wherein:

when the first control signal is asserted as a first logic state and the second control is asserted as a second logic state, the first BJT is turned on to conduct current from the first power supply node to the output node, and the second BJT is turned off, and the capacitor is discharged through the current source device; and

when the first control signal is asserted to the second logic state and the second control is asserted to the first logic state, the first BJT is turned off, the second BJT is turned on, and a discharge current flows into the output node and through the second BJT and the current source device.

Background

Certain types of loads are driven using driver circuits that generate relatively large pulsed currents to the load, which have capacitive input impedances (e.g., passive mixers) and require relatively high slew rate drivers for certain performance requirements. Such driver circuits should be designed for high voltage swing and high slew rate to achieve sufficient linearity and noise performance. Complementary metal oxide semiconductor field effect transistor (CMOS) drivers typically have relatively high power efficiency but lack sufficient speed performance. Bipolar Junction Transistor (BJT) drivers are typically faster than CMOS drivers, but require high current levels and therefore consume more power than CMOS drivers.

Disclosure of Invention

In one example, a circuit includes a first Bipolar Junction Transistor (BJT) including a first base, a first collector, and a first emitter, the first collector coupled to a first supply voltage node, and a second BJT including a second base, a second collector, and a second emitter, the second collector coupled to the first emitter at an output node. The circuit also includes a capacitor including a first capacitor terminal and a second capacitor terminal, the first capacitor terminal connected to the second emitter of the second BJT, and the second capacitor terminal connected to the second supply voltage node. Also included is a current source device connected in parallel with the capacitor.

In another example, a circuit includes a first BJT, a second BJT, a capacitor connected to an emitter of the second BJT and a second supply voltage node. The circuit further comprises a current source device connected in parallel with the capacitor. The control circuit is coupled to receive a first control signal for the first base and is opposite in logic state to the first control signal to generate a second control signal for the second base.

In yet another example, a circuit includes a first BJT, a second BJT, and a current source device connected to an emitter of the second BJT at a second node and configured to be coupled to a capacitor in parallel with the current source device at the second node. The control circuit is coupled to receive a first control signal for the first base and is opposite in logic state to the first control signal to generate a second control signal for the second base.

Drawings

Fig. 1 shows a driver for driving a capacitive load according to an example.

Fig. 2 provides a timing diagram illustrating the operation of the driver described herein.

FIG. 3 includes a flow chart depicting a method associated with the drive of FIG. 1.

Fig. 4 shows another example of a driver for driving a capacitive load.

FIG. 5 includes a flow chart depicting a method associated with the drive of FIG. 4.

Fig. 6 shows yet another example of a driver for driving a capacitive load.

FIG. 7 includes a flow chart depicting a method associated with the drive of FIG. 6.

Detailed Description

Disclosed examples relate to push-pull BJT drivers with capacitive boosting that support capacitive load currents with lower overall power consumption than at least some other drivers. The disclosed driver may drive a load such as a capacitive load. In one application, the load is a passive mixer, which is driven by a high slew rate square wave control signal, so that during the rising transition of the control signal of the first operating state of the driver (charging phase) the driver delivers a current pulse to the capacitive load. During the subsequent falling transition of the control signal (discharge phase), the driver receives a current pulse of similar magnitude from the load. More specifically, in one embodiment, in one operating state of the driver, the driver charges the capacitive load very quickly through the first transistor (e.g., BJT). In a subsequent operating state, the first transistor is turned off and the second transistor is turned on to rapidly discharge charge from the capacitive load through the parallel combination of the current source device and the capacitor. Part of the current from the capacitive load charges the capacitor, while the current through the current source device comprises the remainder of the current from the capacitive load. Then, when the second transistor is turned off and the first transistor is turned on, the first operating state of the driver is restored, the charge on the capacitor (previously received from the capacitive load) is discharged through the current source device, and the capacitive load is charged again through the first transistor as described above. The illustrated driver is capable of high speed operation at a high slew rate at a lower power consumption level than at least some other drivers.

Fig. 1 shows an example of a driver 100 for driving a capacitive load 150. The capacitive load 150 is represented by a capacitor CL and is also referred to herein as capacitive load CL. The capacitive load CL includes, for example, a passive mixer or other type of load whose input impedance is capacitive. The driver 100 includes transistors Q1 and Q2, a capacitor C1, a current source device I1, a control circuit 110, and a register set 120. In this example, Q1 is a Bipolar Junction Transistor (BJT), and in particular an NPN BJT. In other examples, Q1 and Q2 may be implemented using metal oxide semiconductor field effect transistors (MOS). The collector of Q1 is connected to a fixed supply Voltage (VDD) node 115. The base of Q1 is coupled to receive input control signal CTL 1. CTL1 is also provided to control circuitry 110. The emitter of Q1 is connected to the collector of Q2 at output node 118. Q1 is configured as a voltage follower, thus generating the voltage on the emitter of Q1 based on CTL1 and providing that voltage to capacitive load CL, which is coupled to driver 100 at output node 118. Q2 is also configured as a voltage follower that follows the voltage of CTL2 during the rising transition and high state of CTL 2.

In one example, register set 120 includes a single externally accessible register. In other examples, register set 120 includes two or more externally accessible registers. Register set 120 is programmable so that one or more trim values can be loaded by an external device. These adjustment values are used to adjust one or more electrical characteristics of the disclosed circuits described herein. The register set 120 is accessible to be read by the control circuit 110 for reading. In some examples, control circuitry 110 may also write to register sets.

The components of the driver 100, including Q1, Q2, C1, I1, control circuit 110, and register set 120, are formed on a common semiconductor die 102, i.e., Q1, Q2, C1, I1, control circuit 110, and register set 120 are on the same chip. In this example, the capacitive load CL is not on the same semiconductor die 102, but in other examples, the capacitive load CL is on the same semiconductor die as the driver 100.

In the example of fig. 1, Q1 is an NPN BJT, but in other examples may be a different type of transistor (e.g., a PNP BJT, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET), etc.). The control circuit 110 generates another control signal CTL2 to control the on/off state and voltage transitions of Q2. Q2 is also coupled to one terminal of a capacitor C1, and the other terminal of the capacitor C1 is connected to another fixed supply voltage node 116 (e.g., ground). The current source device I1 is coupled in parallel with C1. Sometimes, the reference numeral "I1" is used herein to refer to a current source device, while at other times to the current through the current source device. Node 125 represents the node of the emitter of interconnect Q2, capacitor C1, and current source device I1. The current source device I1 may include one or more transistors, resistors, zener diodes, and/or other circuit components, and generally causes a predetermined amount of current to flow through the current source device in the direction of the arrows.

In this example, control signals CTL1 and CTL2 generally include periodic signals (e.g., clock signals) and are complementary to each other. That is, CTL2 is logic low when CTL1 is logic high, and vice versa. Furthermore, this means that when CTL1 rises, CTL2 falls and vice versa (i.e., their transitions are also complementary). Control circuit 110 receives CTL1 and generates CTL2 that is complementary to CTL 1.

The operation of the driver of fig. 1 will now be explained with reference to the respective timing diagrams of fig. 1 and 2. The drive 100 of fig. 1 has two operating states controlled by CTL1 and CTL 2. One operating state is a charging state and occurs when CTL1 is logic high and CTL2 is logic low. The other operating state is a discharge state and occurs when CTL1 is logic low and CTL2 is logic high. Fig. 2 shows example waveforms for CTL1 and CTL 2. The period of CTL1 is denoted as T, and the rise time (and fall time) of CTL1 is denoted as Ttr. The peak-to-peak voltage of CTL1 is shown as VPP. CTL2 is a similar waveform, but its peak-to-peak voltage is proportional to VPP of CTL 1. As shown, the peak-to-peak voltage of CTL2 is β × VPP, thus β is the ratio of the peak-to-peak voltage of CTL2 to the peak-to-peak voltage of CTL 1. The cycle and rise and fall times of CTL2 are the same as those of CTL 1.

In the charging state (starting at 201), Q1 is on and Q2 is off. Because Q1 is on, the voltage on output node 118, and therefore across capacitive load CL, increases sharply toward VDD. Since the voltage across the capacitive load CL changes abruptly, a load current ILOAD flows into the CL. The magnitude of ILOAD is given by equation (1) below:

the ILOAD waveform is shown in fig. 2, and the magnitude of ILOAD during the Ttr time period is identified at 202. During the time period when Q1 is on and the voltage on output node 118 is constant without change, ILOAD is zero and CL has been charged by the sudden ILOAD pulse current.

Reference numeral 203 identifies the start of the discharge state, at which time Q2 is turned on and Q1 is turned off as shown. Q2 provides a current path for CL through the combined discharge of C1 and I1. The discharge current from CL is shown as I2 in fig. 1, and the I2 waveform is shown in fig. 2. The magnitude of I2 at 204 during the rise time Ttr of CTL2 is generally the same as the magnitude of ILOAD at 202 during the state of charge. The amount of charge delivered from the CL during the rise time of CTL2 is generally equal to the amount of charge received by the CL during the rise time of CTL 1. ILOAD current during the discharge state is indicated as a negative value at 209, indicating that the direction of ILOAD current is opposite to that shown in fig. 1 by the arrow associated with ILOAD through CL.

I2 was divided between C1 and I1. Thus, part of the charge from CL is used to charge C1, and the current through I1 represents the remaining discharge current from CL. Once CL is discharged and the rise time Ttr of CTL2 has ended, the magnitude of I2 falls to the level of I1, as indicated at 205. The voltage on node 125 is shown at 206 in fig. 2 and represents the voltage on C1 because C1 has been charged by CL.

During the next charge phase starting at 207, Q1 is turned on again to charge CL, and Q2 is turned off, as described above. When CL is charging and Q2 is off, C1 discharges its charge through current source device I1 (the charge is received by C1 from CL when Q2 was previously turned on), as indicated by current I3 in fig. 1. The magnitude of I1 is configured such that the discharge of C1 is slower than the charge and discharge of CL. The discharge rate of C1 is indicated at 208 in fig. 2 as the falling voltage of node 125. Typically, C1 discharges within a time period tdich that is approximately half of the period T of control signals CTL1 and CTL 2. "about" means plus or minus 10%.

As can be seen in fig. 2, during a portion of its period T, the I2 current through Q2 is zero, and I1 remains continuously conducting. However, the disclosed circuit consumes less power than circuits such as BJT emitter-followers, in which the current source connected to the emitter is continuously conducting and at a level higher than I1. I1 is less than the current in previous BJT emitter-follower implementations because the circuit disclosed in fig. 1 uses most of the period T to discharge C1 using I1.

The following discussion provides a mathematical relationship between several circuit parameters. Equation (1) above defines the current flowing to the CL during its charge and discharge states. The capacitance of C1 need not be the same as the capacitance of CL. The ratio of C1 to CL is denoted as α (i.e., C1 ═ α × CL). The discharge current from CL during its discharge phase is the combined current of I1 and the current to C1, i.e.:

as described above, it is expected that C1 will subsequently discharge through current source device I1 half the time T, so when C1 discharges, I1 is:

combining equations (1), (2), and (3) yields:

the product of α and β is expressed as:

where γ is the ratio of Ttr to T. Thus, I1 can be expressed as:

and, therefore, based on equation (1),

equation (5) relates α (ratio of C1 to CL), β (ratio of the peak-to-peak voltage of CTL2 to the peak-to-peak voltage of CLT 1), and γ (ratio of Ttr to T). Thus, if any two of α, β, and γ are known, a third value can be calculated.

The foregoing mathematical analysis and relationships are used in the following embodiments. Fig. 1 shows C1 implemented on the same semiconductor die 102 as Q1, Q2, current source device I1, and other components. In this example, C1 has a fixed capacitance value and is therefore known to a user of driver 100. The magnitude of I1 is adjustable under the control of control circuit 110. In one example, I1 is implemented as a set of current sources controlled by switches that can be programmed to select one or more current sources. The switches may be programmed via register set 120. The user has knowledge of the load 150 to be driven and, therefore, of the capacitance value of CL. In this way, the user can calculate α (the ratio of C1 to CL). The user also knows the timing to be used for providing the control signal CTL1 of the driver 100 and thus knows T and Ttr. The user can calculate γ (the ratio of Ttr to T). Knowing α and γ, the user is allowed to calculate β using equation (5), which indicates the peak-to-peak voltage of CTL2 to drive Q2 to be generated by control circuit 110.

Fig. 3 shows an example of a method that may be applied to the drive 100 of fig. 1. The operations in fig. 3 may be performed in the order illustrated, or in a different order. Further, the operations may be performed sequentially or two or more operations may be performed simultaneously.

At 302, the method includes programming adjustment values into register set 120 by which control circuit 110 adjusts I1. According to equation (6), I1 is a function of γ, CL, Ttr, and VPP, and γ is a function of Ttr and T. In operation 302, in one example, the adjustment value includes Ttr, T, CL, and VPP, or a value indicating Ttr, T, CL, and VPP. Based on some or all of these values, the control circuit 110 adjusts I1.

In the example of fig. 3 and other examples described below, programming values into register set 120 includes, in some examples, transmitting values from a device external to the drive to drive 100 over a wired interface. The external device may be a device on the same circuit board as the driver 100, or may be on a different circuit board.

At 304, the value of α is calculated as the ratio of C1 to CL. At 306, a value of β (Ttr/T) based on α and γ is calculated using equation (5). The value of β is then programmed into the register set 120 at 308. Finally, at 310, the method includes the control circuit adjusting the peak-to-peak voltage of CTL2 based on the adjusted values of β and the previously programmed peak-to-peak voltage of CTL 1. The control circuit may include or be coupled to a circuit that generates a voltage for driving the base of Q2. The circuit may be capable of generating a variable voltage configured by the control circuit 110. The variable voltage may be generated using a voltage divider, which may be implemented using a switched resistor or a switched capacitor.

Fig. 4 shows another example of a driver 400 for driving the capacitive load 150. The driver 400 includes transistors Q1 and Q2, a capacitor C1, a current source device I1, a control circuit 410, and a register set 415. The collector of Q1 is connected to the fixed supply voltage node 115. The base of Q1 is coupled to receive input control signal CTL1, and CTL1 is also provided to control circuit 410. The emitter of Q1 is connected to the collector of Q2 at output node 118. Capacitive load CL is coupled to driver 400 at output node 118.

The components of driver 100, including Q1, Q2, C1, I1, control circuit 410, and register set 415 are formed on a common semiconductor die 402, i.e., Q1, Q2, C1, I1, control circuit 110, and register set 415 are on the same chip. In this example, the capacitive load CL is not on the same semiconductor die 402, but in other examples, the capacitive load CL is on the same semiconductor die as the driver 400.

The control circuit 410 generates a control signal CTL2 to control the on/off state of Q2. Q2 is also coupled to one terminal of capacitor C1, and the other terminal of capacitor C1 is connected to another fixed supply voltage node 116. The current source device I1 is coupled in parallel with C1.

The example of fig. 4 is similar to the example of fig. 1. The difference between the two examples is that: in fig. 1, C1 has a fixed capacitance, but in fig. 4, C1 has a variable capacitance. In the example of fig. 4, I1 has an adjustable current magnitude, and C1 is also adjustable. In one example, C1 may be implemented as capacitors coupled in parallel, and each such capacitor may be selected by a switch controlled by control circuit 410. Each capacitor may have the same or different capacitor value as the other capacitors in the parallel capacitor bank. The operation of the drive 400 is largely as described above with reference to the drive 100.

Fig. 5 illustrates an example of a method that may be used in conjunction with the driver 400 of fig. 4. The operations in fig. 5 may be performed in the order illustrated, or in a different order. Further, the operations may be performed sequentially or two or more operations may be performed simultaneously.

At 502, the method includes programming adjustment values into register set 120 by which control circuit 110 adjusts I1. Operation 502 is largely the same as operation 302 in fig. 3. According to equation (6), I1 is a function of γ, CL, Ttr, and VPP, and γ is a function of Ttr and T. In operation 502, in one example, the adjustment values include Ttr, T, CL, and VPP. Based on some or all of these values, the control circuit 110 adjusts I1. At 504, the value of α is calculated as 1/(β (2 γ +1)), and at 506, the value of α is programmed into register set 415.

At 508, C1 is adjusted by control circuit 410 based on the values of α and CL. C1 is alpha multiplied by CL and is thus a scaled version of CL. In the example of fig. 4, the value of β is fixed (e.g., stored in a non-modifiable portion of register set 415, set by logic gates within control circuit 410, etc.), and is therefore used by control circuit 410 at 510 to adjust the peak-to-peak voltage of CTL2 based on the value of VPP programmed into register set 415 at 502.

Fig. 6 shows another example of a drive 600 similar to the drive 100 of fig. 1 or the drive 400 of fig. 1 and 4, respectively. Driver 600 of fig. 6 includes control circuit 600 to drive CTL2 to Q2 based on CTL 1. The driver 600 further includes a register set 615, and as described above, the register set 615 may be programmed with adjustment values by an external device.

Driver 600 differs from drivers 100 and 400 in that: capacitor C1 in fig. 6 is external to semiconductor die 602, which additionally includes control circuitry 610, register set 615, Q1, Q2, and current source device I1. In this example, the user selects C1 and places C1 on, for example, the same Printed Circuit Board (PCB) that may contain driver 600.

Fig. 7 illustrates an example of a method that may be used in conjunction with the driver 600 of fig. 6. The operations in fig. 7 may be performed in the order illustrated, or in a different order. Further, the operations may be performed sequentially or two or more operations may be performed simultaneously. At 702, the method includes programming adjustment values into the register set 615, by which the control circuit 610 adjusts I1. Operation 702 is largely the same as operation 302 in fig. 3. According to equation (6), I1 is a function of γ, CL, Ttr, and VPP, and γ is a function of Ttr and T. In operation 702, in one example, the adjustment values include Ttr, T, CL, and VPP. Based on some or all of these values, control circuit 410 adjusts I1. At 704, the value of α is calculated as 1/(β (2 γ +1)), where β is fixed.

At 706, the method includes selecting a value for C1 based on the values of CL and α. In one example, C1 may be calculated as the product of α and CL (C1 ═ α × CL). Then, a capacitor having an approximately calculated capacitance is mounted on the PCB together with the driver 600 and connected to the node 125 as shown in fig. 6.

Modifications may be made in the described embodiments, and other embodiments are possible, within the scope of the claims.