阅读说明：本技术 Ldmos功率放大器功率附加效率的仿真方法 (Simulation method for power added efficiency of LDMOS power amplifier ) 是由 王向展 吴锦帆 陈玉翔 唐周全 于奇 于 2020-04-24 设计创作，主要内容包括：本发明涉及LDMOS功率放大器技术。本发明解决了现有提取不同LDMOS器件结构的功率附加效率指标的仿真方法精度不高且较为复杂的缺点,提供了一种LDMOS功率放大器功率附加效率的仿真方法,其技术方案可概括为：将现有的固定偏置电压替换为固定偏置电流,而对于不同的器件结构,在固定偏置电流条件下,其端口阻抗基本不变,因而采用统一的匹配电路即可完成不同器件结构的LDMOS功率放大器的搭建。本发明的有益效果是,提升效率指标的仿真精度,有效降低了匹配电路的设计次数,适用于LDMOS功率放大器功率附加效率的仿真。(The invention relates to an LDMOS power amplifier technology. The invention solves the defects of low precision and complexity of the existing simulation method for extracting power additional efficiency indexes of different LDMOS device structures, and provides a simulation method for the power additional efficiency of an LDMOS power amplifier, wherein the technical scheme can be summarized as follows: the existing fixed bias voltage is replaced by the fixed bias current, and for different device structures, the impedance of a port of the LDMOS power amplifier is basically unchanged under the condition of the fixed bias current, so that the construction of the LDMOS power amplifiers with different device structures can be completed by adopting a uniform matching circuit. The invention has the advantages of improving the simulation precision of the efficiency index, effectively reducing the design times of the matching circuit and being suitable for the simulation of the additional power efficiency of the LDMOS power amplifier.)

The method for simulating the power added efficiency of the LDMOS power amplifier is characterized by comprising the following steps of:

step 1, obtaining data of all LDMOS devices, and building an equivalent electrical characteristic model;

step 2, determining a bias voltage corresponding to each LDMOS device under a fixed bias current according to the working bias condition of the power amplifier, and determining a working bias point of each LDMOS device;

step 3, carrying out load traction and signal source traction simulation on any LDMOS device model to determine a matching circuit, wherein all LDMOS device models adopt the matching circuit and the same bias circuit to complete the design of each power amplifier;

and 4, simulating each designed power amplifier to obtain a corresponding power added efficiency index.

2. The method for simulating power added efficiency of an LDMOS power amplifier as recited in claim 1, wherein in step 1, the LDMOS device data comprise DC output characteristic data, transfer characteristic data and small-signal S parameter data of the LDMOS devices.

3. The method for simulating the power added efficiency of the LDMOS power amplifier as recited in claim 2, wherein in the step 1, the obtaining of the data of each LDMOS device and the building of the equivalent electrical characteristic model are as follows: the method comprises the steps of obtaining data of all LDMOS devices, building a direct-current equivalent electrical characteristic model by combining direct-current output characteristic data and transfer characteristic data of the LDMOS devices through an analysis method, building an alternating-current small-signal equivalent electrical characteristic model by combining small-signal S parameter test data of the LDMOS devices, and forming an equivalent electrical characteristic model by combining the direct-current equivalent electrical characteristic model and the alternating-current small-signal equivalent electrical characteristic model.

4. The method for simulating power added efficiency of an LDMOS power amplifier as recited in claim 3,

in step 1, the analysis method comprises:

according to the threshold voltage V of LDMOS device_TGate source voltage V_GSAnd a drain-source voltage V_DSThe relationship of (a) divides the direct current characteristic into four regions:

wherein the threshold voltage V_TAnd drain-source voltage V_DSThe relationship is represented as V_T＝V_T0+γ·V_DS；

When V is_GS＜V_DSWhen the LDMOS device is in the cut-off region;

when V is_GS≥V_TAnd V is_DS＜V_GS-V_TWhen the LDMOS device is in a secondary region or a linear region, the gate-source voltage V is in the secondary region_GSClose to V_T；

When V is_GS≥V_TAnd V is_DS＞V_GS-V_TWhen the LDMOS device is in a saturation region;

when the LDMOS device is in the secondary region, the drain current I_dsqProportional to the square of the gate voltage, there are:

wherein, V_gstIs an effective gate-source voltage, V_gs1Is an intermediate variable, V_stIndicating the steepness of the turn-on of the device, V_T0、γ、V_stAnd β ofFitting the numerical value according to the direct current data of the LDMOS device to obtain the numerical value;

when the LDMOS device is in a linear region, the drain current I_dsExpressed as:

when the LDMOS device is in a saturation region, the drain current does not linearly increase along with the increase of the grid voltage, and the current formula I in the saturation region_dsExpressed as:

wherein V_gs3Expressed as:

wherein V_gs2Expressed as:

wherein, V_kExpressed as the saturation grid voltage of the device, delta, lambda and α are parameters of BSIM3 standard model, psat controls the LDMOS to enter the saturation region from the linear region, V_L、p_linFitting is carried out according to the direct current data of the LDMOS to obtain a fitting factor;

and (4) according to the formula, modeling the equivalent direct current characteristic of the device by combining direct current data of the LDMOS device.

Technical Field

The invention relates to the LDMOS power amplifier technology, in particular to a method for simulating the additional power efficiency of an LDMOS power amplifier.

Background

At present, the application of rf circuit is becoming more extensive with the development of communication technology, however, the power consumption of rf communication equipment inevitably increases with the increase of the integration level of its internal components. The power consumption of the whole equipment is mainly concentrated in the internal power amplifier unit, if the working efficiency of the power amplifier can be improved, the power consumption of the whole equipment is reduced, and the cruising ability of the battery and the service life of electronic components can be effectively enhanced. Depending on the advantages of the LDMOS power device in terms of low manufacturing cost and easy integration with CMOS process, the LDMOS power transistor has attracted attention as a leading technology of a low-band power amplifier, and thus how to improve the efficiency index of the LDMOS radio frequency power amplifier becomes a problem to be solved urgently.

Radio frequency circuit researchers often employ methods to optimize the matching circuit outside the transistor to improve the efficiency of the power amplifier. However, the LDMOS device is used as a core element of the LDMOS power amplifier, and the method does not optimize the electrical characteristics thereof, so as to substantially improve the efficiency of the power amplifier, which has certain limitations.

Optimizing the structure of the LDMOS device and improving the high-frequency characteristic of the LDMOS device is one of effective methods for improving the efficiency of the LDMOS power amplifier. In the paper "An adaptation Mode RF Double Diffused MOSFET with improved Performance", a power device researcher optimizes capacitance characteristics and small signal characteristic indexes of An LDMOS device, and improves high-frequency characteristics of the device, but neglects extraction of efficiency indexes of a power amplifier, and the LDMOS device has a problem of efficiency reduction of the radio frequency power amplifier after tape out, so that if the LDMOS device is in a design stage, the efficiency indexes of the power amplifier can be accurately and efficiently extracted, and research cost can be effectively saved.

At the present stage, the power additional efficiency indexes of different LDMOS device structures are extracted, and the adopted conventional simulation method is as follows: firstly, obtaining LDMOS device data (including direct current and alternating current small signal data and the like), carrying out equivalent electrical characteristic modeling in a radio frequency circuit simulation environment, then determining respective working bias points of the LDMOS device data under the same bias voltage condition, respectively carrying out load traction and signal source traction simulation according to different LDMOS device models, determining a matching circuit, finishing the design of a power amplifier, and finally carrying out large signal simulation to obtain power additional efficiency indexes corresponding to different device structures. For this method, since the same bias voltage is used as the bias mode, there are two problems: firstly, under the same bias voltage, the power amplifier has different bias working points due to the difference of electrical characteristics among different LDMOS device structures, so that the accuracy of power added efficiency evaluation is influenced; and secondly, aiming at different device structures, the impedance matching design needs to be carried out for multiple times according to the difference of the port impedance of the device so as to obtain the corresponding matching circuit, and the repeated matching circuit design greatly increases the workload of radio frequency circuit researchers.

Disclosure of Invention

The invention aims to solve the problems that the existing simulation method for extracting power additional efficiency indexes of different LDMOS device structures is low in precision and complex, and provides a simulation method for the power additional efficiency of an LDMOS power amplifier.

The invention solves the technical problem, adopts the technical scheme that the method for simulating the additional power efficiency of the LDMOS power amplifier is characterized by comprising the following steps of:

step 1, obtaining data of all LDMOS devices, and building an equivalent electrical characteristic model;

step 2, determining a bias voltage corresponding to each LDMOS device under a fixed bias current according to the working bias condition of the power amplifier, and determining a working bias point of each LDMOS device;

step 3, carrying out load traction and signal source traction simulation on any LDMOS device model to determine a matching circuit, wherein all LDMOS device models adopt the matching circuit and the same bias circuit to complete the design of each power amplifier;

and 4, simulating each designed power amplifier to obtain a corresponding power added efficiency index.

Specifically, in order to refine the LDMOS device data, in step 1, the LDMOS device data includes dc output characteristic data, transfer characteristic data, and small signal S parameter data of each LDMOS device.

Further, in order to solve the problem that the operation amount is large when obtaining data of each LDMOS device and building an equivalent electrical characteristic model, in step 1, obtaining data of each LDMOS device and building the equivalent electrical characteristic model means: the method comprises the steps of obtaining data of all LDMOS devices, building a direct-current equivalent electrical characteristic model by combining direct-current output characteristic data and transfer characteristic data of the LDMOS devices through an analysis method, building an alternating-current small-signal equivalent electrical characteristic model by combining small-signal S parameter test data of the LDMOS devices, and forming an equivalent electrical characteristic model by combining the direct-current equivalent electrical characteristic model and the alternating-current small-signal equivalent electrical characteristic model.

Specifically, to provide an analysis method, in step 1, the analysis method is:

according to the threshold voltage V of LDMOS device_TGate source voltage V_GSAnd a drain-source voltage V_DSThe relationship of (a) divides the direct current characteristic into four regions:

wherein the threshold voltage V_TAnd drain-source voltage V_DSThe relationship is represented as V_T＝V_T0+γ·V_DS；

When V is_GS＜V_DSWhen the LDMOS device is in the cut-off region;

when V is_GS≥V_TAnd V is_DS＜V_GS-V_TWhen the LDMOS device is in a secondary region or a linear region, the gate-source voltage V is in the secondary region_GSClose to V_T；

When V is_GS≥V_TAnd V is_DS＞V_GS-V_TWhen the LDMOS device is in a saturation region;

when the LDMOS device is in the secondary region, the drain current I_dsqProportional to the square of the gate voltage, there are:

wherein, V_gstIs an effective gate-source voltage, V_gs1Is an intermediate variable, V_stIndicating the steepness of the turn-on of the device, V_T0、γ、V_stThe numerical values of β are obtained by fitting according to the direct current data of the LDMOS device;

when the LDMOS device is in a linear region, the drain current I_dsExpressed as:

when the LDMOS device is in a saturation region, the drain current does not linearly increase along with the increase of the grid voltage, and the current formula I in the saturation region_dsExpressed as:

wherein V_gs3Expressed as:

wherein V_gs2Expressed as:

wherein, V_kExpressed as the saturation grid voltage of the device, delta, lambda and α are parameters of BSIM3 standard model, psat controls the LDMOS to enter the saturation region from the linear region, V_L、p_linFitting is carried out according to the direct current data of the LDMOS to obtain a fitting factor;

and D, performing direct current equivalent characteristic modeling by combining direct current data of the LDMOS device according to the formula.

The method has the advantages that through the method for simulating the power additional efficiency of the LDMOS power amplifier, the difference of the bias points of different LDMOS device structures can influence the efficiency simulation, and the method can be known through researching the direct current transconductance curves of different LDMOS device structures, and can effectively reduce the difference of the bias points of different power amplifiers and improve the simulation precision of efficiency indexes by taking the same bias current as a determination method of the bias points of the power amplifier; because the LDMOS device adopts the fixed bias current, the port characteristics of different LDMOS device structures are basically unchanged, the optimization times of the matching circuit can be simplified by using the same matching circuit, the radio-frequency power amplifiers built by different LDMOS device structures can be quickly obtained, and the design times of the matching circuit are effectively reduced.

Drawings

FIG. 1 is a flow chart of a method for simulating the power added efficiency of an LDMOS power amplifier according to the present invention;

FIG. 2 is a comparison graph of DC test data of the S1 device in example 1 of the present invention and the results of modeling simulation using the present invention;

FIG. 3 is a comparison graph of the test data of the small signal parameter S11 of the S1 and S2 devices in the working frequency of 100MHz to 2GHz according to the embodiment 1 of the present invention;

FIG. 4 is a comparison graph of the test data of the small signal parameter S22 of the S1 and S2 devices in the working frequency of 100MHz to 2GHz according to the embodiment 1 of the present invention;

fig. 5 is a comparison graph of the relationship between the dc power and the output power of the power amplifier constructed for the devices S1 and S2 in embodiment 1 of the present invention, when a fixed bias voltage is used as a bias mode;

fig. 6 is a comparison graph of the relationship between the dc power and the output power of the power amplifier constructed for the devices S1 and S2 in embodiment 1 of the present invention, when a fixed bias current is used as a bias mode;

fig. 7 is a comparison graph of power added efficiency and actual test data obtained by simulating an S1 device by using a conventional simulation method and the method of the present invention, respectively, in embodiment 1 of the present invention;

fig. 8 is a comparison graph of power added efficiency and actual test data obtained by simulating an S2 device by using a conventional simulation method and the method of the present invention, respectively, in embodiment 1 of the present invention;

FIG. 9 is a schematic view of the structure of the original LDMOS device in embodiment 2;

FIG. 10 is a schematic structural diagram of an improved LDMOS device in embodiment 2;

fig. 11 is a comparison graph of the relationship between the power added efficiency and the input power obtained after the simulation of the two LDMOS device structures in embodiment 2.

Detailed Description

The technical solution of the present invention is described in detail below with reference to the accompanying drawings and embodiments.

The invention relates to a method for simulating the power added efficiency of an LDMOS power amplifier, a flow chart of which is shown in figure 1, and the method comprises the following steps:

step 1, obtaining data of all LDMOS devices, and building an equivalent electrical characteristic model;

step 2, determining a bias voltage corresponding to each LDMOS device under a fixed bias current according to the working bias condition of the power amplifier, and determining a working bias point of each LDMOS device;

step 3, carrying out load traction and signal source traction simulation on any LDMOS device model to determine a matching circuit, wherein all LDMOS device models adopt the matching circuit and the same bias circuit to complete the design of each power amplifier;

and 4, simulating each designed power amplifier to obtain a corresponding power added efficiency index.

By researching S parameter test data of the device, the impedance of the port of the LDMOS power amplifier is basically unchanged under the condition of fixed bias current for different device structures, so that the construction of the LDMOS power amplifiers with different device structures can be completed by adopting a uniform matching circuit, and the design times of the matching circuit are effectively reduced.

In order to refine the LDMOS device data, in step 1, the LDMOS device data preferably includes dc output characteristic data, transfer characteristic data, small signal S parameter data, and the like of each LDMOS device.

In order to solve the problem that the operation amount is large when the data of each LDMOS device is obtained and the equivalent electrical characteristic model is built, in step 1, the obtaining of the data of each LDMOS device and the building of the equivalent electrical characteristic model may be: the method comprises the steps of obtaining data of all LDMOS devices, building a direct-current equivalent electrical characteristic model by combining direct-current output characteristic data and transfer characteristic data of the LDMOS devices through an analysis method, building an alternating-current small-signal equivalent electrical characteristic model by combining small-signal S parameter test data of the LDMOS devices, and forming an equivalent electrical characteristic model by combining the direct-current equivalent electrical characteristic model and the alternating-current small-signal equivalent electrical characteristic model.

To provide an analysis method, in step 1, the analysis method may be:

according to the threshold voltage V of LDMOS device_TGate source voltage V_GSAnd a drain-source voltage V_DSThe relationship of (a) divides the direct current characteristic into four regions:

wherein the threshold voltage V_TAnd drain-source voltage V_DSThe relationship is represented as V_T＝V_T0+γ·V_DS；

When V is_GS＜V_DSWhen the LDMOS device is in the cut-off region;

when V is_GS≥V_TAnd V is_DS＜V_GS-V_TWhen the LDMOS device is in a secondary region or a linear region, the gate-source voltage V is in the secondary region_GSClose to V_T；

When V is_GS≥V_TAnd V is_DS＞V_GS-V_TWhen the LDMOS device is in a saturation region;

when the LDMOS device is in the secondary region, the drain current I_dsqProportional to the square of the gate voltage, there are:

wherein, V_gstIs an effective gate-source voltage, V_gs1Is an intermediate variable, V_stIndicating the steepness of the turn-on of the device, V_T0、γ、V_stThe numerical values of β are obtained by fitting according to the direct current data of the LDMOS device;

when the LDMOS device is in a linear region, the drain current I_dsExpressed as:

when the LDMOS device is in a saturation region, the drain current does not linearly increase along with the increase of the grid voltage, and the current formula I in the saturation region_dsExpressed as:

wherein V_gs3Expressed as:

wherein V_gs2Expressed as:

wherein, V_kExpressed as the saturation grid voltage of the device, delta, lambda and α are parameters of BSIM3 standard model, psat controls the LDMOS to enter the saturation region from the linear region, V_L、p_linFitting is carried out according to the direct current data of the LDMOS to obtain a fitting factor;

and D, performing direct current equivalent characteristic modeling by combining direct current data of the LDMOS device according to the formula.

The method for analyzing the LDMOS power transistor direct current calculates the LDMOS power transistor direct current, greatly reduces the operation amount and further improves the operation speed while ensuring certain precision, is convenient for simulation implementation in an EDA tool, quickly obtains the influence of the LDMOS transistor direct current characteristic on the power additional efficiency of the power amplifier, and further gives a power device design worker beneficial guidance on the aspect of electrical characteristics; the LDMOS power transistor is divided according to the working state of the LDMOS power transistor, then the output current under different working states is obtained, the obtained total output current formula of the LDMOS power transistor is simple, high in accuracy and wide in application range, and the total output current formula can be directly added into simulation software of an integrated circuit to obtain a direct circuit simulation model; in addition, the selection of the static working bias points of different power amplifiers is described, and the static bias working points of the amplifiers are conveniently and quickly determined by using the fixed bias current as a method for determining the bias working points, so that the accuracy of the efficiency simulation of the power amplifiers is improved.