阅读说明：本技术 反相输出动态d触发器 (Inverted output dynamic D flip-flop ) 是由 田文博 范志军 郭海丰 杨作兴 于 2020-06-22 设计创作，主要内容包括：本公开涉及反相输出动态D触发器。提供一种反相输出动态D触发器,其特征在于,包括输入端,用以接收输入数据；输出端,用于提供输出数据来响应该输入数据；时钟信号端,用于接收时钟信号；第一锁存器,用于锁存来自输入端的输入数据并在时钟信号的控制下将输入数据反相传输；第二锁存器,用于锁存来自第一锁存器的数据并在时钟信号的控制下将第一锁存单元锁存的数据反相传输；反相器,用于反相输出从第二锁存器接收到的数据,其中所述第一锁存器、第二锁存器和反相器依次串接在输入端和输出端之间。(The present disclosure relates to an inverted output dynamic D flip-flop. An inverting output dynamic D flip-flop is provided, comprising an input terminal for receiving input data; an output for providing output data in response to the input data; the clock signal end is used for receiving a clock signal; a first latch for latching input data from the input terminal and transferring the input data in reverse phase under the control of a clock signal; the second latch is used for latching the data from the first latch and transmitting the data latched by the first latch unit in an inverted way under the control of a clock signal; and the inverter is used for inverting and outputting the data received from the second latch, wherein the first latch, the second latch and the inverter are sequentially connected between the input end and the output end in series.)

1. An inverted output dynamic D flip-flop, comprising:

an input terminal for receiving input data

An output for providing output data in response to the input data;

the clock signal end is used for receiving a clock signal;

a first latch for latching input data from the input terminal and transferring the input data in reverse phase under the control of a clock signal;

a second latch for latching the data from the first latch and transferring the data latched by the first latch in reverse phase under the control of the clock signal;

an inverter for inverting the data received from the second latch,

the first latch, the second latch and the inverter are sequentially connected in series between the input end and the output end.

2. The inverted output dynamic D flip-flop of claim 1, wherein: the first latch and the second latch are tristate inverters.

3. The inverted output dynamic D flip-flop of claim 2, wherein: the tri-state inverter further comprises a first PMOS transistor, a second PMOS transistor, a first NMOS transistor and a second NMOS transistor, wherein the first PMOS transistor, the second PMOS transistor, the first NMOS transistor and the second NMOS transistor are sequentially connected in series between a power supply and the ground.

4. The inverted output dynamic D flip-flop of claim 3, wherein: the clock signal end is used for providing a clock signal to the clock buffer, the clock signal comprises a first clock signal and a second clock signal, and the first clock signal and the second clock signal are in opposite phase.

5. The inverted output dynamic D flip-flop of claim 3, wherein: the second PMOS transistor of the first latch and the first NMOS transistor of the second latch are subjected to switch control according to the first clock signal; the first NMOS transistor of the first latch and the second PMOS transistor of the second latch are switched according to the second clock signal.

6. The inverted output dynamic D flip-flop of claim 3, wherein: the second PMOS transistor of the first latch and the second NMOS transistor of the second latch are switched according to the first clock signal; the first NMOS transistor of the first latch and the first PMOS transistor of the second latch are switched according to the second clock signal.

7. The inverted output dynamic D flip-flop of claim 3, wherein: the first PMOS transistor of the first latch and the first NMOS transistor of the second latch are switched according to the first clock signal; the second NMOS transistor of the first latch and the second PMOS transistor of the second latch are switch-controlled according to the second clock signal.

8. The inverted output dynamic D flip-flop of claim 3, wherein: the first PMOS transistor of the first latch and the second NMOS transistor of the second latch are switched according to the first clock signal; the second NMOS transistor of the first latch and the first PMOS transistor of the second latch are switched according to the second clock signal.

9. A multi-way parallel register is characterized by comprising

A plurality of input terminals for inputting data;

a plurality of output terminals for outputting data;

the clock signal end is used for receiving a clock signal;

a clock buffer for providing a clock signal to a plurality of dynamic D flip-flops after buffering the clock signal received by the clock signal terminal, the plurality of dynamic D flip-flops being connected in parallel between the plurality of input terminals and the plurality of output terminals for latching and/or reading out data under the control of the clock signal, wherein the dynamic D flip-flops are inverted output dynamic D flip-flops according to claims 1 to 8.

10. An apparatus for performing bitcoin mining algorithms comprising an inverted output dynamic D flip-flop according to any one of claims 1 to 8 or a register according to claim 9.

Technical Field

The present disclosure relates generally to an inverted output dynamic D flip-flop.

Background

Bitcoin is a virtual encrypted digital currency in the form of P2P (Peer-to-Peer), the concept of which was originally proposed by the minwis at 11/1 of 2008 and was formally born at 3/1 of 2009. The bitcoin is unique in that it is not issued by a specific currency institution, but is generated by a large number of operations according to a specific algorithm. Bitcoin transactions use a distributed database of numerous nodes throughout the P2P network to validate and record all transactions and use cryptographic designs to ensure security.

The bitcoin miners excavate the ore through the CPU product in the past, but because the ore excavation is operation-intensive application, and the difficulty is gradually increased along with the continuous improvement of the number of the ore excavation people and the equipment performance, the ore excavation by using the CPU is almost without even negative benefits. Nowadays, miners mostly start to adopt mining equipment such as application specific chips (ASICs) or Field Programmable Gate Arrays (FPGAs).

The core of the mining machine for bitcoin excavation is to obtain the reward according to the computing capability of the mining machine to calculate SHA-256. For a mining machine, chip size, chip running speed and chip power consumption are three factors which are crucial to determining the performance of the mining machine, wherein the chip size determines the chip cost, the speed of chip running determines the running speed of the mining machine, namely computational power, and the chip power consumption determines the power consumption degree, namely the mining cost. In practical applications, the most important performance index for measuring the mining machine is the power consumed by a unit computing power, i.e., a power consumption computing power ratio.

For mining, a large number of repetitive logic calculations are performed in the mining process, which requires a large number of D flip-flops, and improper selection of the D flip-flops may result in an increase in chip area, a slow operation speed, and an increase in power consumption, and finally, a power consumption calculation ratio of the mining machine may be deteriorated.

The D trigger has wide application, and can be used as register of digital signal, shift register, frequency division and waveform generator. The D flip-flop has two inputs, a data (D) and a Clock (CLK), and has an output (Q), and data can be written to or read from the D flip-flop.

Disclosure of Invention

In order to solve the above problems, the present invention provides an inverting output dynamic D flip-flop for a computing device and a parallel register composed of a plurality of parallel inverting output dynamic D flip-flops, thereby effectively reducing area and power consumption.

According to a first aspect of the present disclosure, there is provided an inverted output dynamic D flip-flop, comprising an input to receive input data; an output for providing output data in response to the input data; the clock signal end is used for receiving a clock signal; a first latch for latching input data from the input terminal and transferring the input data in reverse phase under the control of a clock signal; a second latch for latching the data from the first latch and transferring the data latched by the first latch in reverse phase under the control of the clock signal; and the inverter is used for inverting and outputting the data received from the second latch, wherein the first latch, the second latch and the inverter are sequentially connected between the input end and the output end in series.

According to a second aspect of the present disclosure, there is provided a multi-way parallel register comprising a plurality of inputs for inputting data; a plurality of output terminals for outputting data; the clock signal end is used for receiving a clock signal; and the clock buffer is used for buffering the clock signal received by the clock signal terminal and then providing the clock signal to the plurality of dynamic D flip-flops, and the plurality of dynamic D flip-flops are connected in parallel between the plurality of input terminals and the plurality of output terminals and are used for latching and/or reading data under the control of the clock signal, wherein the dynamic D flip-flops are inverted output dynamic D flip-flops as described above.

According to a third aspect of the present disclosure, there is provided an apparatus for performing a bitcoin mining algorithm, comprising an inverted output dynamic D flip-flop according to the above or a plurality of parallel registers according to the above.

Other features of the present disclosure and advantages thereof will become apparent from the following detailed description of exemplary embodiments thereof, which proceeds with reference to the accompanying drawings.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description, serve to explain the principles of the disclosure.

The present disclosure may be more clearly understood from the following detailed description, taken with reference to the accompanying drawings, in which:

FIG. 1 illustrates an inverted output dynamic D flip-flop according to one embodiment of the present invention;

FIG. 2 illustrates a clock buffer for an inverted output dynamic D flip-flop according to one embodiment of the present invention;

FIG. 3 illustrates an inverted output dynamic D flip-flop with clocking according to one embodiment of the present invention;

FIGS. 4A, 4B, 4C, and 4D respectively illustrate circuit schematic diagrams of an inverted output dynamic D flip-flop according to one embodiment of the present invention;

FIG. 5 shows a circuit timing diagram for an inverted output dynamic D flip-flop according to FIGS. 4A, 4B, 4C and 4D;

FIGS. 6A, 6B, 6C and 6D respectively show circuit schematic diagrams of an inverted output dynamic D flip-flop according to another embodiment of the present invention;

FIG. 7 shows a circuit timing diagram for an inverted output dynamic D flip-flop according to FIGS. 6A, 6B, 6C and 6D;

fig. 8 shows a multi-way parallel register consisting of multiple parallel inverting output dynamic D flip-flops.

Note that in the embodiments described below, the same reference numerals are used in common between different drawings to denote the same portions or portions having the same functions, and a repetitive description thereof will be omitted. In this specification, like reference numerals and letters are used to designate like items, and therefore, once an item is defined in one drawing, further discussion thereof is not required in subsequent drawings.

For convenience of understanding, the positions, sizes, ranges, and the like of the respective structures shown in the drawings and the like do not sometimes indicate actual positions, sizes, ranges, and the like. Therefore, the disclosed invention is not limited to the positions, dimensions, ranges, etc., disclosed in the drawings and the like. Furthermore, the figures are not necessarily to scale, some features may be exaggerated to show details of particular components.

Detailed Description

Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. It should be noted that: the relative arrangement of the components and steps, the numerical expressions, and numerical values set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

The following description of at least one exemplary embodiment is merely illustrative in nature and is in no way intended to limit the disclosure, its application, or uses. That is, the circuits and methods for implementing a hashing algorithm herein are shown by way of example to illustrate different embodiments of the circuits or methods in this disclosure and are not intended to be limiting. Those skilled in the art will appreciate that they are merely illustrative of ways that the invention may be practiced, not exhaustive.

Techniques, methods, and apparatus known to those of ordinary skill in the relevant art may not be discussed in detail but are intended to be part of the specification where appropriate.

The computing equipment for mining the virtual currency needs to perform a large amount of repeated logic computation in the mining process, which needs a large amount of D triggers to perform data storage, so that the performance of the D triggers directly affects the performance of a computing chip, including chip area, power consumption, operation speed and the like.

Compared with a static D trigger, the dynamic D trigger has the advantages that a positive feedback circuit for keeping the working state is reduced, so that the circuit structure is greatly simplified, the area of a chip is reduced, and the power consumption can be reduced. In the logic design of a computing chip, a D flip-flop with an inverted output is sometimes required to be used, and in view of the situation, the invention provides an inverted output dynamic D flip-flop. The inverted output dynamic D trigger provided by the invention can effectively reduce the chip area and the power consumption due to the omission of a primary inverter, which is very important for virtual currency computing equipment using a large number of dynamic D triggers.

FIG. 1 illustrates an inverted output dynamic D flip-flop according to one embodiment of the present invention. The inverted output dynamic D flip-flop 100 includes an input terminal 101 for receiving input data; an output 102 for providing output data in response to the input data; a clock signal terminal 103 for receiving a clock signal; a first latch 104 for latching the input data from the input terminal 101 and transferring the input data in reverse under the control of a clock signal; a second latch 105 for latching the data from the first latch 104 and transferring the latched data of the first latch 104 in reverse under the control of the clock signal; and an inverter 106 for inverting and outputting the data received from the second latch 105, wherein the first latch 104, the second latch 105 and the inverter 106 are connected in series between the input terminal 101 and the output terminal 102, and the data at the output terminal 102 is inverted from the data at the input terminal 101.

Fig. 2 shows a clock buffer for providing a clock signal for an inverted output dynamic D flip-flop. The clock buffer 200 is composed of two serially connected inverters 201 and 202, and the inverters 201 and 202 respectively generate CLKN and CLKP signals for controlling an inverted output dynamic D flip-flop. The clock buffer 200 buffers an input clock signal CK and provides inverted clock signals CLKN, CLKP, which are inverted from each other, to the inverted output dynamic D flip-flop. Only 2 inverters are shown in fig. 2, but the number of inverters is not limited to 2, and the number of inverters may be more.

Fig. 3 shows an inverted output dynamic D flip-flop 300 with clocking. As shown in fig. 3, the clock signal CK is buffered by a clock buffer 301 and then provided to an inverted output dynamic D flip-flop 300 as clock signals CLKN, CLKP.

FIG. 4A shows a circuit schematic of an inverted output dynamic D flip-flop according to one embodiment of the present invention. Inverted output dynamic D flip-flop 400 receives input data from input 401 to first latch 402, first latch 402 being a tristate inverter. The first latch 402 includes a plurality of switching elements connected in series with each other. In a specific embodiment, the first latch 402 comprises a first PMOS transistor 403, a second PMOS transistor 404, a first NMOS transistor 405, and a second NMOS transistor 406, and the first PMOS transistor 403, the second PMOS transistor 404, the first NMOS transistor 405, and the second NMOS transistor 406 are sequentially connected in series between a power supply VDD and a ground GND.

As shown in fig. 4A, the source of the first PMOS transistor 403 is connected to the power VDD, the source of the second PMOS transistor 404 is connected to the drain of the first PMOS transistor 403, the drain of the first NMOS transistor 405 is connected to the drain of the second PMOS transistor 404, the drain of the second NMOS transistor 406 is connected to the source of the first NMOS transistor 405, and the source of the second NMOS transistor 406 is connected to the ground GND. The gate of the first PMOS transistor 403 and the gate of the second NMOS transistor 406 are connected together to receive input data from the input terminal. The gate of the second PMOS transistor 404 is set to receive the clock signal CLKP and the gate of the first NMOS transistor 405 is set to receive the clock signal CLKN.

When CLKN is at a low level, CLKP is at a high level, both the second PMOS transistor 404 and the first NMOS transistor 405 are in a non-conducting state, the first latch 402 is in a high-impedance state, and data at the input terminal 401 cannot pass through the first latch 402. Since the data at the input terminal 401 cannot pass through the first latch 402, the data at the node 407 can be latched at the node 407, and the original state is maintained, thereby playing a role of data registration. When CLKN is high, CLKP is low, both the second PMOS transistor 404 and the first NMOS transistor 405 are in a conducting state, and the first latch 402 functions to invert the data at its input terminal 401, i.e., invert the data at the input terminal 401 and output it to the node 407, rewriting the data at the node 407.

Similarly, the second latch 408 is also a tristate inverter, and includes a plurality of switching elements connected in series with each other. As shown in fig. 4A, the second latch 408 includes a third PMOS transistor 409, a fourth PMOS transistor 410, a third NMOS transistor 411, and a fourth NMOS transistor 412 connected in series in this order. The third PMOS transistor 409 gate and the fourth NMOS transistor 412 gate are connected together to receive the data from the first latch 402. The gate of the fourth PMOS transistor 410 is set to receive the clock signal CLKN and the gate of the third NMOS transistor 411 is set to receive the clock signal CLKP.

When CLKN is low, CLKP is high, the fourth PMOS transistor 410 and the third NMOS transistor 411 are both in a conducting state, and the second latch 408 plays a role of inverting the data at its input terminal 401, i.e. transmitting the data at the node 407 to the node 413 in an inverted state, rewriting the data at the node 413. When CLKN is at a high level, CLKP is at a low level, second latch 408 is at a high-impedance state, and data at node 407 cannot pass through second latch 408, so that data at node 413 is latched at node 413, and remains in the original state, which plays a role of data registration.

As shown in fig. 4A, the output driving unit of the inverted output dynamic D flip-flop is an inverter 414. Inverter 414 inverts the data received from second latch 408 again for eventual transmission to output 415. Since the data undergoes a total of three inversions from the first latch, the second latch, and the inverter, the data at the inverted output dynamic D flip-flop output 415 is inverted compared to the data at the input 401.

Compared with the traditional dynamic D trigger with the inverter as the first stage, the dynamic D trigger omits an input inverter so as to change an output end into an inverted output, and the number of transistors of the dynamic D trigger is reduced from 12 to 10, so that the chip area is reduced by about 16%; and because of the reduction of one stage of inverter, the power is reduced correspondingly.

In addition, the inverted output dynamic D flip-flop omits an input end inverter and reserves an output end inverter. Such a design is of particular concern: reserving the output inverter (i.e., omitting the input inverter) may preserve the stronger drive capability of the dynamic D flip-flop to subsequent circuits than omitting the output inverter, so that the dynamic D flip-flop may drive a larger load behind it. The first stage of the inverting output dynamic D trigger is a tri-state gate circuit with a small capacitor, so that the driving difficulty is small, and a single-stage inverter is not needed for driving.

This advantageous technical effect is equally applicable to the inverted output dynamic D flip-flops shown in fig. 4B-4D, 6A-6D, below.

FIG. 4B shows a circuit schematic of an inverted output dynamic D flip-flop according to one embodiment of the present invention. Inverted output dynamic D flip-flop 400 receives input data from input 401 to first latch 402, first latch 402 being a tristate inverter. The first latch 402 includes a plurality of switching elements connected in series with each other. In a specific embodiment, the first latch 402 comprises a first PMOS transistor 403, a second PMOS transistor 404, a first NMOS transistor 405, and a second NMOS transistor 406, and the first PMOS transistor 403, the second PMOS transistor 404, the first NMOS transistor 405, and the second NMOS transistor 406 are sequentially connected in series between a power supply VDD and a ground GND.

As shown in fig. 4B, the source of the first PMOS transistor 403 is connected to the power VDD, the source of the second PMOS transistor 404 is connected to the drain of the first PMOS transistor 403, the drain of the first NMOS transistor 405 is connected to the drain of the second PMOS transistor 404, the drain of the second NMOS transistor 406 is connected to the source of the first NMOS transistor 405, and the source of the second NMOS transistor 406 is connected to the ground GND. The gate of the first PMOS transistor 403 and the gate of the second NMOS transistor 406 are connected together to receive input data from the input terminal. The gate of the second PMOS transistor 404 is set to receive the clock signal CLKP and the gate of the first NMOS transistor 405 is set to receive the clock signal CLKN.

When CLKN is at a low level, CLKP is at a high level, both the second PMOS transistor 404 and the first NMOS transistor 405 are in a non-conducting state, the first latch 402 is in a high-impedance state, and data at the input terminal 401 cannot pass through the first latch 402. Since the data at the input terminal 401 cannot pass through the first latch 402, the data at the node 407 can be latched at the node 407, and the original state is maintained, thereby playing a role of data registration. When CLKN is high, CLKP is low, both the second PMOS transistor 404 and the first NMOS transistor 405 are in a conducting state, and the first latch 402 functions to invert the data at its input terminal, i.e., invert the data at the input terminal 401 and output it to the node 407, rewriting the data at the node 407.

Similarly, the second latch 408 is also a tristate inverter, and includes a plurality of switching elements connected in series with each other. As shown in fig. 4B, the second latch 408 includes a third PMOS transistor 409, a fourth PMOS transistor 410, a third NMOS transistor 411, and a fourth NMOS transistor 412 connected in series in this order. The fourth PMOS transistor 410 gate and the third NMOS transistor 411 gate are connected together to receive the data from the first latch 402. The gate of the third PMOS transistor 409 is set to receive the clock signal CLKN and the gate of the fourth NMOS transistor 412 is set to receive the clock signal CLKP.

When CLKN is at a low level, CLKP is at a high level, the third PMOS transistor 409 and the fourth NMOS transistor 412 are both in a conducting state, and the second latch 408 plays a role of inverting data at its input end, that is, inverting data at the node 407 and transmitting the inverted data to the node 413, and rewriting the data at the node 413. When CLKN is at a high level, CLKP is at a low level, second latch 408 is at a high-impedance state, and data at node 407 cannot pass through second latch 408, so that data at node 413 is latched at node 413, and remains in the original state, which plays a role of data registration.

As shown in fig. 4B, the output driving unit of the inverted output dynamic D flip-flop is an inverter 414. Inverter 414 inverts the data received from second latch 408 again for eventual transmission to output 415. Since the data undergoes a total of three inversions from the first latch, the second latch, and the inverter, the data at the inverted output dynamic D flip-flop output 415 is inverted compared to the input.

FIG. 4C shows a circuit schematic of an inverted output dynamic D flip-flop according to one embodiment of the present invention. Inverted output dynamic D flip-flop 400 receives input data from input 401 to first latch 402, first latch 402 being a tristate inverter. The first latch 402 includes a plurality of switching elements connected in series with each other. In a specific embodiment, the first latch 402 comprises a first PMOS transistor 403, a second PMOS transistor 404, a first NMOS transistor 405, and a second NMOS transistor 406, and the first PMOS transistor 403, the second PMOS transistor 404, the first NMOS transistor 405, and the second NMOS transistor 406 are sequentially connected in series between a power supply VDD and a ground GND.

As shown in fig. 4C, the source of the first PMOS transistor 403 is connected to the power VDD, the source of the second PMOS transistor 404 is connected to the drain of the first PMOS transistor 403, the drain of the first NMOS transistor 405 is connected to the drain of the second PMOS transistor 404, the drain of the second NMOS transistor 406 is connected to the source of the first NMOS transistor 405, and the source of the second NMOS transistor 406 is connected to the ground GND. The gate of the second PMOS transistor 404 and the gate of the first NMOS transistor 405 are connected together to receive input data from the input terminal. The gate of the first PMOS transistor 403 is set to receive the clock signal CLKP and the gate of the second NMOS transistor 406 is set to receive the clock signal CLKN.

When CLKN is at a low level, CLKP is at a high level, both the first PMOS transistor 403 and the second NMOS transistor 406 are in a non-conducting state, the first latch 402 is in a high-impedance state, and data at the input terminal 401 cannot pass through the first latch 402. Since the data at the input terminal 401 cannot pass through the first latch 402, the data at the node 407 can be latched at the node 407, and the original state is maintained, thereby playing a role of data registration. When CLKN is high, CLKP is low, both the first PMOS transistor 403 and the second NMOS transistor 406 are in a conducting state, and the first latch 402 functions to invert the data at its input terminal, i.e., invert the data at the input terminal 401 and output it to the node 407, rewriting the data at the node 407.

Similarly, the second latch 408 is also a tristate inverter, and includes a plurality of switching elements connected in series with each other. As shown in fig. 4C, the second latch 408 includes a third PMOS transistor 409, a fourth PMOS transistor 410, a third NMOS transistor 411, and a fourth NMOS transistor 412 connected in series in this order. The third PMOS transistor 409 gate and the fourth NMOS transistor 412 gate are connected together to receive the data from the first latch 402. The gate of the fourth PMOS transistor 410 is set to receive the clock signal CLKN and the gate of the third NMOS transistor 411 is set to receive the clock signal CLKP.

When CLKN is at a low level, CLKP is at a high level, the fourth PMOS transistor 410 and the third NMOS transistor 411 are both in a conducting state, and the second latch 408 plays a role of inverting data at its input end, that is, inverting data at the node 407 and transmitting the inverted data to the node 413, and rewriting the data at the node 413. When CLKN is at a high level, CLKP is at a low level, second latch 408 is at a high-impedance state, and data at node 407 cannot pass through second latch 408, so that data at node 413 is latched at node 413, and remains in the original state, which plays a role of data registration.

As shown in fig. 4C, the output driving unit of the inverted output dynamic D flip-flop is an inverter 414. Inverter 414 inverts the data received from second latch 408 again for eventual transmission to output 415. Since the data undergoes a total of three inversions from the first latch, the second latch, and the inverter, the data at the inverted output dynamic D flip-flop output 415 is inverted compared to the input.

FIG. 4D shows a circuit schematic of an inverted output dynamic D flip-flop according to one embodiment of the present invention. Inverted output dynamic D flip-flop 400 receives input data from input 401 to first latch 402, first latch 402 being a tristate inverter. The first latch 402 includes a plurality of switching elements connected in series with each other. In a specific embodiment, the first latch 402 comprises a first PMOS transistor 403, a second PMOS transistor 404, a first NMOS transistor 405, and a second NMOS transistor 406, and the first PMOS transistor 403, the second PMOS transistor 404, the first NMOS transistor 405, and the second NMOS transistor 406 are sequentially connected in series between a power supply VDD and a ground GND.

As shown in fig. 4D, the source of the first PMOS transistor 403 is connected to the power VDD, the source of the second PMOS transistor 404 is connected to the drain of the first PMOS transistor 403, the drain of the first NMOS transistor 405 is connected to the drain of the second PMOS transistor 404, the drain of the second NMOS transistor 406 is connected to the source of the first NMOS transistor 405, and the source of the second NMOS transistor 406 is connected to the ground GND. The gate of the second PMOS transistor 404 and the gate of the first NMOS transistor 405 are connected together to receive input data from the input terminal. The gate of the first PMOS transistor 403 is set to receive the clock signal CLKP and the gate of the second NMOS transistor 406 is set to receive the clock signal CLKN.

When CLKN is at a low level, CLKP is at a high level, both the first PMOS transistor 403 and the second NMOS transistor 406 are in a non-conducting state, the first latch 402 is in a high-impedance state, and data at the input terminal 401 cannot pass through the first latch 402. Since the data at the input terminal 401 cannot pass through the first latch 402, the data at the node 407 can be latched at the node 407, and the original state is maintained, thereby playing a role of data registration. When CLKN is high, CLKP is low, both the first PMOS transistor 403 and the second NMOS transistor 406 are in a conducting state, and the first latch 402 functions to invert the data at its input terminal, i.e., invert the data at the input terminal 401 and output it to the node 407, rewriting the data at the node 407.

Similarly, the second latch 408 is also a tristate inverter, and includes a plurality of switching elements connected in series with each other. As shown in fig. 4D, the second latch 408 includes a third PMOS transistor 409, a fourth PMOS transistor 410, a third NMOS transistor 411, and a fourth NMOS transistor 412 connected in series in this order. The fourth PMOS transistor 410 gate and the third NMOS transistor 411 gate are connected together to receive the data from the first latch 402. The gate of the third PMOS transistor 409 is set to receive the clock signal CLKN and the gate of the fourth NMOS transistor 412 is set to receive the clock signal CLKP.

When CLKN is at a low level, CLKP is at a high level, the third PMOS transistor 409 and the fourth NMOS transistor 412 are both in a conducting state, and the second latch 408 plays a role of inverting data at its input end, that is, inverting data at the node 407 and transmitting the inverted data to the node 413, and rewriting the data at the node 413. When CLKN is at a high level, CLKP is at a low level, second latch 408 is at a high-impedance state, and data at node 407 cannot pass through second latch 408, so that data at node 413 is latched at node 413, and remains in the original state, which plays a role of data registration.

As shown in fig. 4D, the output driving unit of the inverted output dynamic D flip-flop is an inverter 414. Inverter 414 inverts the data received from second latch 408 again for eventual transmission to output 415. Since the data undergoes a total of three inversions from the first latch, the second latch, and the inverter, the data at the inverted output dynamic D flip-flop output 415 is inverted compared to the input.

The inverted output dynamic D flip-flops shown in fig. 4A-4D are all variations of the present invention except for the location of the clocked transistors in first latch 402 and second latch 408.

The following is a detailed description of the operation principle of the inverted output dynamic D flip-flop with reference to fig. 5 (fig. 5 shows the circuit timing diagram of the inverted output dynamic D flip-flop according to fig. 4A, 4B, 4C and 4D).

As shown in fig. 4A, 4B, 4C, and 4D, when CK is low, CLKP is low and CLKN is high. The transistors of the first latch 402 controlled by the clock signals CLKN and CLKP are turned on, and the first latch 402 inverts the data at its input terminal, that is, inverts the data at the input terminal 401, outputs the inverted data to the node 407, and rewrites the data at the node 407. For example, when the input data D is 0, the data at node 407 will be 1. When CLKP is at a low level and CKLN is at a high level, the transistors controlled by clock signals CLKN and CLKP in the second latch 408 are in a non-conducting state, the second latch 408 is in a high-impedance state, and the data at node 407 cannot pass through the second latch 408. The data at the node 413 can be latched in the node 413, and the data can be kept in the original state, so that the data can be registered, and the output of the dynamic D flip-flop can be kept in the original state.

Next, as shown in fig. 5, when the rising edge of CK comes, CLKP jumps to a high level and CLKN jumps to a low level. The transistors in the first latch 402 controlled by the clock signals CLKN and CLKP are in a non-conducting state, the first latch 402 assumes a high-impedance state, and data at the input cannot be held by data at the first latches 402 and 407. At this time, the transistors controlled by the clock signals CLKN, CLKP in the second latch 402 are turned on, and the second latch 408 is turned on and functions to invert the data at its input terminal, so that the data held at the node 407 is inverted and output to the node 413, and further to the output terminal 415 through the inverter 414. Therefore, when the rising edge of the clock signal CK approaches, the output state of the dynamic D flip-flop changes. Since the input data undergoes three inversions in total, the output terminal outputs the inverted data of the input terminal. Therefore, as shown in fig. 5, when the rising edge of CK approaches, when the input terminal D is 1, the output terminal QN jumps to 0; when the input terminal D is 0, the output terminal QN jumps to 1.

Falling edge active dynamic D flip-flops may also be implemented by interchanging the clock control signals of the dynamic D flip-flops (e.g., the NMOS transistor of the first latch 402 is controlled by CLKP and the PMOS transistor is controlled by CLKN; the PMOS transistor of the second latch 408 is controlled by CLKP and the NMOS transistor is controlled by CLKN). Fig. 6A, 6B, 6C, and 6D show four different variations after the clock control signals CLKP and CLKN are interchanged, respectively. Fig. 7 shows a timing diagram of the circuits shown in fig. 6A, 6B, 6C, and 6D.

As shown in fig. 6A, 6B, 6C, and 6D, when CK is high, CLKP is high and CLKN is low. The transistors of the first latch 402 controlled by the clock signals CLKN and CLKP are turned on, and the first latch 402 inverts the data at its input terminal, that is, inverts the data at the input terminal 401, outputs the inverted data to the node 407, and rewrites the data at the node 407. For example, when the input data D is 0, the data at node 407 will be 1. When CLKP is at a high level and CKLN is at a low level, the transistors controlled by clock signals CLKN and CLKP in the second latch 408 are in a non-conducting state, the second latch 408 is in a high-impedance state, and the data at node 407 cannot pass through the second latch 408. The data at the node 413 can be latched in the node 413, and the data can be kept in the original state, so that the data can be registered, and the output of the dynamic D flip-flop can be kept in the original state.

When a falling edge occurs, CLKP transitions to a low level and CLKN transitions to a high level. The transistors in the first latch 402 controlled by the clock signals CLKN and CLKP are in a non-conducting state, the first latch 402 assumes a high-impedance state, and data at the input cannot be held by data at the first latches 402 and 407. At this time, the transistors controlled by the clock signals CLKN, CLKP in the second latch 402 are turned on, and the second latch 408 is turned on and functions to invert the data at its input terminal, so that the data held at the node 407 is inverted and output to the node 413, and further to the output terminal 415 through the inverter 414. Therefore, when the falling edge of the clock signal CK approaches, the output state of the dynamic D flip-flop changes. Since the input data undergoes three inversions in total, the output terminal outputs the inverted data of the input terminal. Therefore, as shown in fig. 7, when the falling edge of CK approaches, when the input terminal D is 0, the output terminal QN jumps to 1; when the input terminal D is 1, the output terminal QN jumps to 0.

Fig. 8 shows a multi-way parallel register to which the inverted output dynamic D flip-flop according to the embodiment of the present invention is applied. As shown in fig. 8, the multiple parallel register 800 includes multiple parallel inverse output dynamic D flip-flops 801, a clock buffer 802, a clock signal terminal CK, multiple input terminals D (n) and multiple output terminals qn (n), where n represents n input/output. The multi-path input end D (n) is used for inputting data; the multi-path output end QN (n) is used for outputting data; the clock signal terminal CK is used for receiving a clock signal; a clock buffer 802 for buffering the clock signal received by the clock signal terminal CK and then providing the clock signal to a plurality of inverted output dynamic D flip-flops 801, wherein the plurality of inverted output dynamic D flip-flops 801 are connected in parallel between the multi-way input terminal D (n) and the multi-way output terminal qn (n) for latching and/or reading data under the control of the clock signal CK, and the inverted output dynamic D flip-flops 801 are the inverted output dynamic D flip-flops according to the embodiments of the present invention described in conjunction with fig. 1 to fig. 7.

Generally, the independent D flip-flop needs a clock buffer to generate clock signals with mutually inverted phases to control the clock input terminal of the D flip-flop. If a separate clock buffer is configured for each D flip-flop, the clock buffer consumes significant chip area and power consumption in applications requiring the use of multiple D flip-flops. In order to solve the problem, one clock buffer in the invention drives a plurality of dynamic D triggers simultaneously, so that the area can be effectively reduced, and the power consumption can be reduced. Compared with the traditional dynamic D trigger, the invention eliminates the first-stage inverter input by the dynamic D trigger, thereby reducing the number of transistors of each dynamic D trigger, the total chip area and the total power. Under the combined effect of the above multipoint improvements, the register claimed by the invention has the advantages of area reduction and power reduction compared with the traditional register.

The invention also provides a device for the bitcoin mining algorithm, which comprises the inverse output dynamic D trigger 400 or the multi-path parallel register 800 applying the inverse output dynamic D trigger.

In all examples shown and discussed herein, any particular value should be construed as merely illustrative, and not limiting. Thus, other examples of the exemplary embodiments may have different values.

The terms "front," "back," "top," "bottom," "over," "under," and the like in the description and in the claims, if any, are used for descriptive purposes and not necessarily for describing permanent relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure described herein are, for example, capable of operation in other orientations than those illustrated or otherwise described herein.

As used herein, the word "exemplary" means "serving as an example, instance, or illustration," and not as a "model" that is to be replicated accurately. Any implementation exemplarily described herein is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, the disclosure is not limited by any expressed or implied theory presented in the preceding technical field, background, brief summary or the detailed description.

As used herein, the term "substantially" is intended to encompass any minor variation resulting from design or manufacturing imperfections, device or component tolerances, environmental influences, and/or other factors. The word "substantially" also allows for differences from a perfect or ideal situation due to parasitic effects, noise, and other practical considerations that may exist in a practical implementation.

The above description may indicate elements or nodes or features being "connected" or "coupled" together. As used herein, unless expressly stated otherwise, "connected" means that one element/node/feature is directly connected to (or directly communicates with) another element/node/feature, either electrically, mechanically, logically, or otherwise. Similarly, unless expressly stated otherwise, "coupled" means that one element/node/feature may be mechanically, electrically, logically, or otherwise joined to another element/node/feature in a direct or indirect manner to allow for interaction, even though the two features may not be directly connected. That is, coupled is intended to include both direct and indirect joining of elements or other features, including connection with one or more intermediate elements.

It will be further understood that the terms "comprises/comprising," "includes" and/or "including," when used herein, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.

Those skilled in the art will appreciate that the boundaries between the above described operations merely illustrative. Multiple operations may be combined into a single operation, single operations may be distributed in additional operations, and operations may be performed at least partially overlapping in time. Moreover, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be altered in various other embodiments. However, other modifications, variations, and alternatives are also possible. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense.

Although some specific embodiments of the present disclosure have been described in detail by way of example, it should be understood by those skilled in the art that the foregoing examples are for purposes of illustration only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any combination without departing from the spirit and scope of the present disclosure. It will also be appreciated by those skilled in the art that various modifications may be made to the embodiments without departing from the scope and spirit of the disclosure. The scope of the present disclosure is defined by the appended claims.