阅读说明：本技术 一种高稳定可设置三角波发生器电路 (High-stability triangular wave generator circuit capable of being arranged ) 是由 周文华 魏海港 王成修 陈亚涛 翁志霞 于 2020-05-09 设计创作，主要内容包括：本发明公开了一种高稳定可设置三角波发生器电路。其包括波形比较控制回路、波形生成电路及信号整形放大回路；波形比较控制回路包括U3比较器,所述U3比较器输入反向端接地信号,输出端与NPN三极管D2基极、D1肖特基管阴极、R1其中一端相连接,R1另一端与D2三极管集电极相连并接入正电源V+,D2三极管发射极与D1肖特基管阳极并接形成控制输出。本发明全新的三角载波产生思路,通过合理的分立器件参数设计,不但能使电路改变三角波频率,且幅值大小也可调整。最主要的是其电路系统稳定性、可靠性都能自我掌控,且组合结构简单、调试十分方便。(The invention discloses a high-stability settable triangular wave generator circuit. The device comprises a waveform comparison control circuit, a waveform generation circuit and a signal shaping and amplifying circuit; the waveform comparison control loop comprises a U3 comparator, the input end of the U3 comparator is connected with a grounding signal, the output end of the U3 comparator is connected with the base electrode of an NPN triode D2, the cathode of a D1 Schottky tube and one end of R1, the other end of R1 is connected with the collector electrode of a D2 triode and is connected with a positive power supply V +, and the emitter electrode of the D2 triode and the anode of the D1 Schottky tube are connected in parallel to form control output. The novel triangular carrier wave generating idea of the invention not only enables the circuit to change the triangular wave frequency, but also enables the amplitude to be adjusted through reasonable parameter design of discrete devices. The most important is that the stability and reliability of the circuit system can be controlled by self, and the combined structure is simple and the debugging is very convenient.)

1. A high-stability settable triangular wave generator circuit is characterized in that: the device comprises a waveform comparison control circuit, a waveform generation circuit and a signal shaping and amplifying circuit;

the waveform comparison control loop comprises a U3 comparator, wherein the U3 comparator inputs a reverse end grounding signal, the output end of the U3 comparator is connected with one end of a D2 base electrode of an NPN triode, a cathode of a D1 Schottky tube and R1, the other end of R1 is connected with a collector of a D2 triode and is connected with a positive power supply V +, and an emitter of the D2 triode and an anode of the D1 Schottky tube are connected in parallel to form control output;

the waveform generation circuit comprises a resistor R2, one end of the resistor R2 is connected with one end of the resistor R5 in parallel and finally connected with the output end of the waveform comparison control circuit to form a grid mark N2, and the other end of the resistor R5 is connected with one end of an integrating capacitor C1 and the reverse input end of a JFET operational amplifier U2 to form a grid mark N3; the other end of the integrating capacitor C1 is connected with the output end of the U2 operational amplifier and one end of the R6 to form a network mark N4; finally, the other end of the R6 and the R5 are connected in series for voltage division and then integrally form an operational amplifier closed loop, and a network mark N5 formed by connecting the resistors R5 and R6 in series for voltage division is connected to the positive input end of the waveform comparator U3;

the signal shaping amplifying circuit comprises a blocking capacitor C2, one end of the blocking capacitor C2 is connected with the output end of the JFET operational amplifier U2, the other end of the blocking capacitor C2 is connected with one end of a resistor R3 in the amplifying shaping circuit, the other end of the resistor R3 is connected with one end of a resistor R4 and the inverted input end of the JFET operational amplifier U1, the forward input end of the operational amplifier U1 is directly connected with a reference zero level, and finally the output end of the operational amplifier U1 and the other end of the operational amplifier R4 form a closed loop.

2. A highly stable settable triangular wave generator circuit according to claim 1 wherein: the U1 and the U2 adopt JFET type operational amplifiers with low bias/offset current, other resistors and capacitors adopt high-precision low-temperature drift coefficient specifications, and the diode D1 adopts a Schottky tube with low forward voltage drop.

3. A highly stable settable triangular wave generator circuit according to claim 2, wherein: the final output network mark N2 of the waveform comparison control loop generates a switching function of positive and negative levels based on the positive input end of the input reference end U3; if the reference level of the positive input end of the U3 is higher than the reference zero level, the comparator drives the triode BE electrode through the pull-up resistor R1 so as to activate the NPN triode D2 and further accelerate the turning on of the rising edge of the N2 level; if it is lower than the reference zero level, the loop finally passes through schottky diode D1 to make the output of the grid N2 a negative level.

4. A highly stable settable triangular wave generator circuit according to claim 3 wherein: the output of a preceding stage circuit output mesh mark N2 of the waveform generation circuit is V +, then the circuit charges C1 through R2, when the potential of N3 exceeds the reference zero level of operational amplifier U2, the output is a negative level, and feedback integration is carried out through a C1 capacitor, at the moment, N2 is the potential of V +, and N4 is a continuously reduced negative level; when the series voltage dividing resistors R5 and R6 take set values and the N4 is reduced to the set value of the voltage dividing resistors, the potential of the N5 is lower than the reference of the comparator U3, the output N1 of the comparator is V-, the D2 triode fails, the N2 is forced to be in a V-state through the Schottky diode D1, and the alternating and continuous circulation are carried out, so that the triangular original waveform is generated.

5. A high stability settable triangular wave generator circuit according to claim 4 wherein: the triangular original waveform output network mark N4 is connected to an amplifying loop through a blocking capacitor, and the amplitude of the final triangular output waveform F _ out can be adjusted through resistance setting of R3 and R4, so that the generation of the triangular waveform is finally completed.

Technical Field

The invention relates to a high-stability settable triangular wave generator circuit, and belongs to the technical field of electric power systems.

Background

In an electric power system, a very reliable chopping technology is required for various application occasions such as inversion, frequency conversion, photovoltaic and the like, and the most core reference in the chopping technology is generally a triangular waveform, also called a carrier, so that the stability and the fineness of an output waveform of the chopping technology are very important. The conventional method is to directly purchase a waveform generator chip and arrange a small amount of resistance-capacitance components. The chips have different technical capabilities and very different integration performances, and particularly have the requirement of reliable operation in various environments for a long time, so that the chips are often broken due to uneven heating or temperature and humidity problems. The development of the modern operational amplifier technology is basically perfect, and the performance of the modern operational amplifier is very reliable and excellent as long as a brand manufacturer.

In order to overcome the defects, the basic elements are selected and reasonably configured, and self-matching is carried out by using a proper principle, so that the using effect is very obvious.

Disclosure of Invention

In view of the above, the invention provides a highly stable triangle wave generator circuit, a brand new triangle carrier generation idea, and through reasonable parameter design of discrete devices, not only can the triangle wave frequency be changed, but also the amplitude can be adjusted. The most important is that the stability and reliability of the circuit system can be controlled by self, and the combined structure is simple and the debugging is very convenient.

The invention solves the technical problems by the following technical means: a high-stability settable triangular wave generator circuit comprises a waveform comparison control circuit, a waveform generation circuit and a signal shaping and amplifying circuit;

the waveform comparison control loop comprises a U3 comparator, wherein the U3 comparator inputs a reverse end grounding signal, the output end of the U3 comparator is connected with one end of a D2 base electrode of an NPN triode, a cathode of a D1 Schottky tube and R1, the other end of R1 is connected with a collector of a D2 triode and is connected with a positive power supply V +, and an emitter of the D2 triode and an anode of the D1 Schottky tube are connected in parallel to form control output;

the waveform generation circuit comprises a resistor R2, one end of the resistor R2 is connected with one end of the resistor R5 in parallel and finally connected with the output end of the waveform comparison control circuit to form a grid mark N2, and the other end of the resistor R5 is connected with one end of an integrating capacitor C1 and the reverse input end of a JFET operational amplifier U2 to form a grid mark N3; the other end of the integrating capacitor C1 is connected with the output end of the U2 operational amplifier and one end of the R6 to form a network mark N4; finally, the other end of the R6 and the R5 are connected in series for voltage division and then integrally form an operational amplifier closed loop, and a network mark N5 formed by connecting the resistors R5 and R6 in series for voltage division is connected to the positive input end of the waveform comparator U3;

the signal shaping amplifying circuit comprises a blocking capacitor C2, one end of the blocking capacitor C2 is connected with the output end of the JFET operational amplifier U2, the other end of the blocking capacitor C2 is connected with one end of a resistor R3 in the amplifying shaping circuit, the other end of the resistor R3 is connected with one end of a resistor R4 and the inverted input end of the JFET operational amplifier U1, the forward input end of the operational amplifier U1 is directly connected with a reference zero level, and finally the output end of the operational amplifier U1 and the other end of the operational amplifier R4 form a closed loop.

The U1 and the U2 adopt JFET type operational amplifiers with low bias/offset current, other resistors and capacitors adopt high-precision low-temperature drift coefficient specifications, and the diode D1 adopts a Schottky tube with low forward voltage drop.

The final output network mark N2 of the waveform comparison control loop generates a switching function of positive and negative levels based on the positive input end of the input reference end U3; if the reference level of the positive input end of the U3 is higher than the reference zero level, the comparator drives the triode BE electrode through the pull-up resistor R1 so as to activate the NPN triode D2 and further accelerate the turning on of the rising edge of the N2 level; if it is lower than the reference zero level, the loop finally passes through schottky diode D1 to make the output of the grid N2 a negative level.

The output of a preceding stage circuit output mesh mark N2 of the waveform generation circuit is V +, then the circuit charges C1 through R2, when the potential of N3 exceeds the reference zero level of operational amplifier U2, the output is a negative level, and feedback integration is carried out through a C1 capacitor, at the moment, N2 is the potential of V +, and N4 is a continuously reduced negative level; when the series voltage dividing resistors R5 and R6 take set values and the N4 is reduced to the set value of the voltage dividing resistors, the potential of the N5 is lower than the reference of the comparator U3, the output N1 of the comparator is V-, the D2 triode fails, the N2 is forced to be in a V-state through the Schottky diode D1, and the alternating and continuous circulation are carried out, so that the triangular original waveform is generated.

The triangular original waveform output network mark N4 is connected to an amplifying loop through a blocking capacitor, and the amplitude of the final triangular output waveform F _ out can be adjusted through resistance setting of R3 and R4, so that the generation of the triangular waveform is finally completed.

The invention relates to the most central technical field of chopping of a power electronic system, and solves the technical problem of a high-stability and high-reliability triangular carrier generator provided for ensuring the PWM chopping function.

The invention has the beneficial effects that: the design idea is ingenious, the circuit structure is flexible, the heat dissipation is uniform when the devices are uniformly distributed, the parameter calculation is convenient, the requirement of batch production is met, the production and test efficiency can be obviously improved, the reliability is high, the stability is high, and the application value is wide.

Drawings

FIG. 1 is a circuit diagram of the present invention.

Detailed Description

The embodiments of the present invention will be described in further detail with reference to the following description of the drawings, but the embodiments are not intended to limit the present invention, and all similar structures and similar variations using the present invention shall be included in the scope of the present invention, and the pause numbers in the present invention shall have a relation of the same.

As shown in fig. 1, the high-stability configurable triangular wave generator circuit provided in the embodiment of the present invention includes a waveform comparison control circuit, a waveform generation circuit, and a signal shaping amplification circuit;

the waveform comparison control loop comprises a U3 comparator, wherein the U3 comparator inputs a reverse end grounding signal, the output end of the U3 comparator is connected with one end of a D2 base electrode of an NPN triode, a cathode of a D1 Schottky tube and R1, the other end of R1 is connected with a collector of a D2 triode and is connected with a positive power supply V +, and an emitter of the D2 triode and an anode of the D1 Schottky tube are connected in parallel to form control output;

the waveform generation circuit comprises a resistor R2, one end of the resistor R2 is connected with one end of the resistor R5 in parallel and finally connected with the output end of the waveform comparison control circuit to form a grid mark N2, and the other end of the resistor R5 is connected with one end of an integrating capacitor C1 and the reverse input end of a JFET operational amplifier U2 to form a grid mark N3; the other end of the integrating capacitor C1 is connected with the output end of the U2 operational amplifier and one end of the R6 to form a network mark N4; finally, the other end of the R6 and the R5 are connected in series for voltage division and then integrally form an operational amplifier closed loop, and a network mark N5 formed by connecting the resistors R5 and R6 in series for voltage division is connected to the positive input end of the waveform comparator U3;

the signal shaping amplifying circuit comprises a blocking capacitor C2, one end of the blocking capacitor C2 is connected with the output end of the JFET operational amplifier U2, the other end of the blocking capacitor C2 is connected with one end of a resistor R3 in the amplifying shaping circuit, the other end of the resistor R3 is connected with one end of a resistor R4 and the inverted input end of the JFET operational amplifier U1, the forward input end of the operational amplifier U1 is directly connected with a reference zero level, and finally the output end of the operational amplifier U1 and the other end of the operational amplifier R4 form a closed loop.

The U1 and the U2 adopt JFET type operational amplifiers with low bias/offset current, other resistors and capacitors adopt high-precision low-temperature drift coefficient specifications, and the diode D1 adopts a Schottky tube with low forward voltage drop.

The final output network mark N2 of the waveform comparison control loop generates a switching function of positive and negative levels based on the positive input end of the input reference end U3; if the reference level of the positive input end of the U3 is higher than the reference zero level, the comparator drives the triode BE electrode through the pull-up resistor R1 so as to activate the NPN triode D2 and further accelerate the turning on of the rising edge of the N2 level; if it is lower than the reference zero level, the loop finally passes through schottky diode D1 to make the output of the grid N2 a negative level.

The output of a preceding stage circuit output mesh mark N2 of the waveform generation circuit is V +, then the circuit charges C1 through R2, when the potential of N3 exceeds the reference zero level of operational amplifier U2, the output is a negative level, and feedback integration is carried out through a C1 capacitor, at the moment, N2 is the potential of V +, and N4 is a continuously reduced negative level; when the series voltage dividing resistors R5 and R6 take set values and the N4 is reduced to the set value of the voltage dividing resistors, the potential of the N5 is lower than the reference of the comparator U3, the output N1 of the comparator is V-, the D2 triode fails, the N2 is forced to be in a V-state through the Schottky diode D1, and the alternating and continuous circulation are carried out, so that the triangular original waveform is generated.

The triangular original waveform output network mark N4 is connected to an amplifying loop through a blocking capacitor, and the amplitude of the final triangular output waveform F _ out can be adjusted through resistance setting of R3 and R4, so that the generation of the triangular waveform is finally completed.

In order to ensure the high stability performance index of the circuit, U1 and U2 need to adopt JFET type operational amplifiers with low bias/offset current, other resistors and capacitors need to adopt high-precision low temperature drift coefficient specifications, and a diode D1 adopts a Schottky tube with low forward voltage drop.

The U3 comparator, the pull-up resistor R1, the Schottky diode D1 and the NPN triode D2 jointly construct a waveform comparison control loop. The reverse input end of the U3 is connected with zero potential, and the non-positive input end of the U3 receives loop signals from voltage-dividing resistors R5 and R6 in the triangular wave generation loop. The output end of the comparator is directly connected with the base electrode of a triode D2, the cathode of a D1 Schottky tube and one end of a R1 resistor; the emitter of the triode D2 is directly connected with the anode of the Schottky tube D1, and the collector of the triode D2 is connected with the other end of the R1 resistor and is connected with a positive working power supply.

One ends of the resistors R2 and R5 are connected in parallel and are connected with the output end of the waveform comparison control loop to form a net mark N2, and the other end of the resistors R2 and R5 are connected with one end of the integrating capacitor C1 and the reverse input end of the JFET operational amplifier U2 to form a net mark N3; the other end of the integrating capacitor C1 is connected with the output end of the U2 operational amplifier and one end of the R6 to form a network mark N4; and finally, the other end of the R6 is connected with the R5 in series for voltage division, and then the whole circuit forms an operational amplifier closed loop. A net mark N5 formed by serially connecting the resistors R5 and R6 for voltage division is connected to the positive input end of the waveform comparator U3. The closed loop connections are organized in this way to form a waveform formation circuit.

One end of the direct current blocking capacitor C2 is connected with the output end of the JFET operational amplifier U2, the other end of the direct current blocking capacitor C2 is connected with one end of a R3 resistor in the amplification shaping circuit, and the other end of the R3 resistor is connected with one end of a R4 resistor and the reverse input end of the JFET operational amplifier U1; and the forward input end of the U1 operational amplifier is directly connected with a reference zero level, and finally the output end of the U1 JFET operational amplifier and the other end of the R4 form a closed loop to form an amplifying and shaping circuit.

The working principle of the invention is as follows:

after the circuit is powered on, the circuit quickly self-establishes balance based on the internal characteristics of the loop. If the reference level of the forward input end of the U3 is higher than the reference zero level, the comparator U3 drives the BE electrode of the triode through the pull-up resistor R1 so as to activate the NPN triode D2, and further the rising edge of the level of the network logo N2 is accelerated to BE turned on until the highest potential is close to the V + potential; if it is lower than the reference zero level, the loop finally passes through schottky diode D1 to make the output of the grid N2 a negative level.

The JFET operational amplifier U2, the capacitor C1, the resistors R2, R5 and R6 are combined to form a triangular waveform generating circuit. If the output of the output mesh mark N2 of the preceding stage circuit is close to the V + potential, the output mesh mark N2 charges C1 through R2, when the potential of N3 exceeds the reference zero level of the operational amplifier U2, the output mesh mark N4 is at a negative level, and feedback integration is carried out through a C1 capacitor, at the moment, N2 is at a high potential, and N4 is at a continuously reduced negative level. When series voltage-dividing resistors R5 and R6 take set values and N4 is reduced to the set value of the voltage-dividing resistors, the potential of N5 is lower than the reference of a comparator U3, the output N1 of the comparator is V-, a D2 triode fails, and N2 is forced to be in a V-state through a Schottky diode D1; at the moment, N4 reaches the minimum negative potential (the negative peak value is limited by R4 and R5 parameters), N2 is the V-potential, N3 reaches the positive maximum value due to the previous charging and integration relation, the circuit starts to discharge C1 through R2, then the potentials of N4 and N2 are kept unchanged (the time is short through reasonable setting of R2 and C1 parameters), the potential of N3 is gradually reduced, when the potential reaches a value slightly smaller than the reference zero potential, the output of the JFET U2 is reversed, at the moment, the potential of N4 is gradually increased from the negative peak value, the potential of N3 is slightly lower than the zero potential (considering that N3 is the zero potential in view of the sensitivity relation of the operational amplifier), N2 is the V-potential, and the state of the comparator circuit is kept unchanged; with the feedback integration of U2 and C1 and the continuous discharge of N2 to N3 through R2, the potential of N3 is gradually smaller than zero potential and has a tendency of reduction, while the potential of N4 gradually goes out of a negative valley and rises upwards, when a positive maximum set value is reached, the N2 is still V-potential at the moment, and the N3 reaches the negative minimum peak potential through the series connection of R2 and C1; n4 and N2 are in voltage division relation through resistors R6 and R5, the potential of N5 reaches a reference condition higher than a zero reference, a comparator U3 loop starts potential inversion, N2 is a positive peak potential, at the moment, N4 is at a positive set peak potential, N2 is close to a V + potential, N3 is in a negative minimum potential state, N2 starts to charge C1 through a resistor R2, when the potential of the end of N3 is gradually raised to exceed the zero reference potential, the output polarity of an operational amplifier U2 starts to be inverted again, and the feedback integral … of C1 reciprocates and starts in cycles, so that a triangular original waveform is generated.

The JFET operational amplifier U1, the resistors R3, R4 and the capacitor C2 form a waveform shaping amplifying loop. The triangular original waveform output network mark N4 is connected into an amplifying loop through a blocking capacitor high-pass filtering, the amplitude of the final triangular output waveform F _ out can be adjusted through resistance setting of R3 and R4, and therefore the generation of the triangular waveform is finally completed.

Finally, the above embodiments are only for illustrating the technical solutions of the present invention and not for limiting, although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all of them should be covered in the claims of the present invention.