阅读说明：本技术 基于扩散忆阻器和电流传输器的随机频率三角波发生器 (Random frequency triangular wave generator based on diffusion memristor and current transmitter ) 是由 梁涛 于 2020-06-02 设计创作，主要内容包括：基于扩散忆阻器和电流传输器的随机频率三角波发生器,属于集成电路技术领域。本发明为解决现有的随机频率三角载波发生器,由于其使用随机数发生器,导致电路复杂和设计难度大的问题。本发明包括控制逻辑单元、随机延时单元、延时链单元、第一寄存器单元、第二寄存器单元、电流传输器、N个NMOS管M<Sub>1</Sub>至M<Sub>N</Sub>、电容阵列、比较器U<Sub>1</Sub>、电阻R<Sub>A</Sub>、电阻R<Sub>B</Sub>和电阻R<Sub>X</Sub>；本发明先使用电流传输器提供恒定的充放电电流,再利用时间间隔测量技术对扩散忆阻器的随机延时时间进行编码,所得到的随机温度计码用来控制充放电电容的大小,从而获得周期及频率随机变化的等幅三角波。本发明主要应用在随机PWM技术中。(Random frequency triangular wave generator based on diffusion memristor and current transmitter belongs to integrated circuit technical field. The invention aims to solve the problems of complex circuit and high design difficulty of the conventional random frequency triangular carrier wave generator due to the use of a random number generator. The invention comprises a control logic unit, a random delay unit, a delay chain unit, a first register unit, a second register unit, a current transmitter, N NMOS tubes M 1 To M N Capacitor array and comparator U 1 Resistance R A Resistance R B And a resistance R X (ii) a The constant charge-discharge current is provided by using the current transmitter, the random delay time of the diffusion memristor is encoded by using a time interval measurement technology, and the obtained random thermometer code is used for controlling the size of a charge-discharge capacitor, so that a constant-amplitude triangular wave with a period and a frequency which are randomly changed is obtained. The invention is mainly applied to the random PWM technology.)

1. The random frequency triangular wave generator based on the diffusion memristor and the current transmitter is characterized by comprising a control logic unit, a random time delay unit, a time delay chain unit, a first register unit, a second register unit, the current transmitter and N NMOS (N-channel metal oxide semiconductor) tubes M₁To M_NCapacitor array and comparator U₁Resistance R_AResistance R_BAnd a resistance R_X(ii) a Wherein the capacitor array comprises a capacitor C₀To C_N；

The control logic unit is used for generating a pulse signal V_P0And simultaneously sending the data to the random delay unit and the delay chain unit; the reset circuit is also used for generating a reset signal Rst to reset the delay chain unit; and also for generating a clock signal Clk_LClock control is carried out on the second register unit; and is also used for receiving the pulse signal V output by the random delay unit_P1(ii) a And also for receiving the comparator U₁Voltage signal V output from output terminal_Y；

The random delay unit is realized by adopting a diffusion memristor and is used for receiving a pulse signal V_P0Processing to obtain pulse signal V_P1And will pulse signal V_P1Simultaneously inputting the signals to the control logic unit and the first register unit; wherein the pulse signal V_P1And pulse signal V_P0Are equal in period, and the pulse signal V_P1And pulse signal V_P0Are coincident in time, pulse signal V_P0High level duration t_pIs a fixed value, a pulse signal V_P1High level duration t_dIs a random value, and t_d＜t_p；

The random delay time of the diffusion memristor is equal to t_d；

A delay chain unit for receiving the pulse signal V_P0Generating an N-bit thermometer code and sending the N-bit thermometer code to a first register unit;

the first register unit receives the pulse signal V_P1At its pulse signal V_P1The falling edge time of the first register unit latches the received N-bit thermometer code and sends the latched result to the second register unit;

the second register unit is based on the received clock signal Clk_LAt its clock signal Clk_LThe rising edge time of the first register unit latches the latch result output by the first register unit to obtain the N-bit thermometer code d₁To d_NAnd coding the N-bit thermometer by d₁To d_NRespectively sent to NMOS tubes M₁To M_NThe grid electrode controls the corresponding NMOS tube; wherein when d_iWhen 1, represents d_iIs at a high level; when d is_iWhen 0, represents d_iLow, i ═ 1, 2, 3 … … N;

NMOS tube M₁To M_NSource and capacitor C₀One end of each of the two ends is connected with a power ground;

NMOS tube M₁To M_NRespectively with the capacitor C₁To C_NIs connected to a capacitor C₀To C_NAnd the other end of the current transmitter, a Z port of the current transmitter and a comparator U₁Are connected simultaneously, and the voltage signal V of the connection point_CapAs a random-frequency triangular carrier signal generated by a triangular carrier generator, and a voltage signal V_CapIs a random frequency isosceles triangle wave signal with equal amplitude;

comparator U₁Non-inverting input terminal and resistor R_AAnd a resistor R_BAre connected at the same time, resistor R_BThe other end of the resistor R is connected with a power ground_AAnd the other end of the comparator U₁Voltage of the output terminal, the Y port of the current conveyor and the control logic unitSignal V_YThe input ends are connected;

x port and resistor R of current transmitter_XIs connected to a resistor R_XThe other end of the first power supply is connected with a power ground;

comparator U₁The positive voltage input end is connected with a power supply V_DDComparator U₁Negative voltage input end is connected with a power supply V_SSAnd V is_DD＝-V_SS。

2. The random frequency triangular wave generator based on the diffusion memristor and the current conveyor as claimed in claim 1, wherein the delay chain unit comprises N delay modules, and the N delay modules are cascaded in series, wherein the signal input end of the first delay module is used as the delay chain unit to receive the pulse signal V_P0An input terminal of (1);

each delay module is used for delaying the rising edge of an input signal of the delay module, and delay signal values output by the first to Nth delay modules are respectively used as first to Nth thermometer codes output by the delay chain unit;

the reset signal input end of each delay module is used for receiving a reset signal Rst, and when the reset signal Rst is at a high level, the output states of the N delay modules are reset to be 0.

3. The diffused memristor and current conveyor based random frequency triangle wave generator of claim 2, wherein the delay block comprises a not gate Y₁NOT gate Y₂NMOS transistor M_aAnd NMOS transistor M_b；

NOT gate Y₁The input end of the delay module is used as the data signal input end of the delay module;

NOT gate Y₁Of the output nand gate Y₂Is connected to the input terminal of a NOT gate Y₂Output end of the NMOS transistor M_aDrain electrode of (1) and NMOS tube M_bThe grid of the delay module is connected with the grid of the first transistor and then used as a data signal output end of the delay module;

NMOS tube M_aThe grid of the delay module is used as a reset signal input end of the delay module;

NMOS tube M_aSource electrode of and NMOS tube M_bSource electrode and NMOS transistor M_bThe drains are connected simultaneously and then connected to the power ground.

4. The diffused memristor-and-current-conveyor-based random frequency triangle wave generator of claim 1, wherein the first register cell comprises a not gate Y₃And N D flip-flops;

NOT gate Y₃As a first register unit receiving a pulse signal V_P1An input terminal of (1);

NOT gate Y₃The output end of the D flip-flop is simultaneously connected with the clock signal input ends of the N D flip-flops;

d input ends of the first to Nth D triggers are respectively used as input ends of first to Nth thermometer codes of the first register unit;

q output ends of the first to Nth D flip-flops are respectively used as output ends of the first to Nth thermometer codes of the first register unit.

5. The random frequency triangular wave generator based on the diffusion memristor and the current conveyor as claimed in claim 1, wherein the second register unit comprises N D flip-flops, and the clock signal input ends of the N D flip-flops are connected at the same time to be used as the clock signal input end of the second register unit;

d input ends of first to Nth D triggers in the second register unit are respectively used as input ends of first to Nth thermometer codes of the second register unit;

q output ends of first to Nth D flip-flops in the second register unit are respectively used as output ends of first to Nth thermometer codes of the second register unit.

6. The random frequency triangle wave generator based on diffused memristor and current conveyor of claim 1, wherein the random delay unit comprises a level shifter, a diffused memristor R_MResistance R_rComparator U₂And an and gate X1;

the input end of the level shifter is used as the input end of the random time delay unit to receive the pulse signal V_P0And the input terminal of the level shifter is connected with one input terminal of the and gate X1;

a level shifter for shifting the received pulse signal V_P0Is lowered and the obtained programming pulse signal V is applied₁Output to diffused memristor R_MOne end of (1), diffusion memristor R_MAnother terminal of (1) and a resistor R_rAnd a comparator U₂The inverting input terminals of the two-way switch are connected simultaneously; resistance R_rThe other end of the first power supply is connected with a power ground;

comparator U₂For receiving a reference voltage V_refComparator U₂Is connected to the other input of and gate X1;

the output end of the AND gate X1 is used as the output end of the random delay unit to output a pulse signal V_P1。

7. The random frequency triangular wave generator based on the diffusion memristor and the current conveyor as claimed in claim 1, wherein the control logic unit comprises a NOR gate, an AND gate X2, an AND gate X3, an XOR gate, a preset number counter and two fixed delayers, wherein the delay time of the first fixed delayer is τ₀The delay time of the second fixed delayer is 2 tau₀；

One input end of the NOR gate is used as a control logic unit for receiving the pulse signal V_P1After the other input end of the NOR gate is simultaneously connected with the input ends of the two fixed time delayers, the NOR gate is used as a control logic unit to receive a voltage signal V_YAn input terminal of (1);

the output end of the NOR gate is simultaneously connected with one input end of the AND gate X2 and one input end of the AND gate X3;

the output end of the first fixed time delay is connected with the other input end of the AND gate X2, and the output end of the second fixed time delay is connected with the other input end of the AND gate X3;

the output of AND gate X2 and one input of XOR gateTerminal connected and the output terminal of the AND gate X2 is used as the clock signal Clk output by the control logic unit_LAn output terminal of (a);

the output end of the AND gate X3 is connected with the other input end of the XOR gate, and the output end of the XOR gate is connected with the reset signal input end of the preset number counter and then serves as the output end of the control logic unit for outputting a reset signal Rst;

the clock signal input end of the preset number counter is used for receiving an external clock signal Clk;

the output end of the preset number counter is used as a control logic unit to output a pulse signal V_P0To the output terminal of (a).

Technical Field

The invention belongs to the technical field of integrated circuits.

Background

The application of the pulse width Modulation (PulseWidth Modulation) technology is very critical in power control and conversion integrated circuits such as a switching power supply and a motor drive. Conventional PWM control signals are generated by comparing a fixed frequency triangular or sawtooth carrier signal with an error signal and then utilized to control the on-time of the switching device over a fixed period to achieve a timely response to load variations. Research shows that the conventional PWM technology has a large harmonic component near the switching frequency and an integral multiple of the switching frequency, which may cause many adverse effects to the system, such as causing a great amount of electromagnetic noise interference, causing distortion of voltage and current waveforms, and even causing abnormal operation of the subsequent devices.

For the occasion that the carrier frequency must be limited to a lower frequency, the problems of electromagnetic interference and the like caused by the conventional PWM technology can be better solved by adopting the random PWM technology. The random PWM technology disperses the energy of harmonic frequency spectrum which is intensively distributed at the switching frequency and the frequency multiplication position thereof by randomly changing the carrier frequency under the premise of ensuring that the duty ratio is not changed, thereby enabling the electromagnetic noise to be approximately band-limited white noise, and greatly weakening the intensity of colored noise which is characterized by fixing the switching frequency.

In order to achieve the purpose of randomizing the switching frequency, firstly, a carrier signal with randomly changeable frequency is generated, and the random frequency triangular carrier has higher research value because the triangular wave has higher control precision relative to the sawtooth wave and can realize the function of bilateral modulation. Such a triangular carrier wave is required to be a constant-amplitude isosceles triangular wave in each period, but the period thereof is randomly changed. At present, most of the developments of the random frequency triangular carrier wave generator need to use a random number generator for providing randomly changing frequency values, which increases the complexity and design difficulty of the circuit, and therefore, the above problems need to be solved urgently.

Disclosure of Invention

The invention aims to solve the problems of complex circuit and high design difficulty caused by the use of a random number generator in the conventional random frequency triangular carrier wave generator, and provides a random frequency triangular wave generator based on a diffusion memristor and a current transmitter.

A random frequency triangular wave generator based on a diffusion memristor and a current transmitter comprises a control logic unit, a random time delay unit, a time delay chain unit, a first register unit, a second register unit, the current transmitter and N NMOS (N-channel metal oxide semiconductor) transistors M₁To M_NCapacitor array and comparator U₁Resistance R_AResistance R_BAnd a resistance R_X(ii) a Wherein the capacitor array comprises a capacitor C₀To C_N；

The control logic unit is used for generating a pulse signal V_P0And simultaneously sending the data to the random delay unit and the delay chain unit; the reset circuit is also used for generating a reset signal Rst to reset the delay chain unit; and also for generating a clock signal Clk_LClock control is carried out on the second register unit; and is also used for receiving the pulse signal V output by the random delay unit_P1(ii) a And also for receiving the comparator U₁Voltage signal V output from output terminal_Y；

The random delay unit is realized by adopting a diffusion memristor and is used for receiving a pulse signal V_P0Processing to obtain pulse signal V_P1And will pulse signal V_P1Simultaneously inputting the signals to the control logic unit and the first register unit; wherein the pulse signal V_P1And pulse signal V_P0Are equal in period, and the pulse signal V_P1And pulse signal V_P0Are coincident in time, pulse signal V_P0High level duration t_pIs a fixed value, a pulse signal V_P1High level duration t_dIs a random value, and t_d＜t_p；

The random delay time of the diffusion memristor is equal to t_d；

A delay chain unit for receiving the pulse signal V_P0Generating an N-bit thermometer code and sending the N-bit thermometer code to a first register unit;

the first register unit receives the pulse signal V_P1At its pulse signal V_P1The falling edge time of the first register unit latches the received N-bit thermometer code and sends the latched result to the second register unit;

the second register unit is based on the received clock signal Clk_LAt its clock signal Clk_LThe rising edge time of the first register unit latches the latch result output by the first register unit to obtain the N-bit thermometer code d₁To d_NAnd coding the N-bit thermometer by d₁To d_NRespectively sent to NMOS tubes M₁To M_NThe grid electrode controls the corresponding NMOS tube; wherein when d_iWhen 1, represents d_iIs at a high level; when d is_iWhen 0, represents d_iAt a low level，i＝1、2、3……N；

NMOS tube M₁To M_NSource and capacitor C₀One end of each of the two ends is connected with a power ground;

NMOS tube M₁To M_NRespectively with the capacitor C₁To C_NIs connected to a capacitor C₀To C_NAnd the other end of the current transmitter, a Z port of the current transmitter and a comparator U₁Are connected simultaneously, and the voltage signal V of the connection point_CapAs a random-frequency triangular carrier signal generated by a triangular carrier generator, and a voltage signal V_CapIs a random frequency isosceles triangle wave signal with equal amplitude;

comparator U₁Non-inverting input terminal and resistor R_AAnd a resistor R_BAre connected at the same time, resistor R_BThe other end of the resistor R is connected with a power ground_AAnd the other end of the comparator U₁Output terminal of current conveyor, Y port of current conveyor and voltage signal V of control logic unit_YThe input ends are connected;

x port and resistor R of current transmitter_XIs connected to a resistor R_XThe other end of the first power supply is connected with a power ground;

comparator U₁The positive voltage input end is connected with a power supply V_DDComparator U₁Negative voltage input end is connected with a power supply V_SSAnd V is_DD＝-V_SS。

Preferably, the delay chain unit includes N delay modules, and the N delay modules are cascaded in series, wherein a signal input end of a first delay module is used as the delay chain unit to receive the pulse signal V_P0An input terminal of (1);

each delay module is used for delaying the rising edge of an input signal of the delay module, and delay signal values output by the first to Nth delay modules are respectively used as first to Nth thermometer codes output by the delay chain unit;

the reset signal input end of each delay module is used for receiving a reset signal Rst, and when the reset signal Rst is at a high level, the output states of the N delay modules are reset to be 0.

Preferably, the delay module comprises a not gate Y₁NOT gate Y₂NMOS transistor M_aAnd NMOS transistor M_b；

NOT gate Y₁The input end of the delay module is used as the data signal input end of the delay module;

NOT gate Y₁Of the output nand gate Y₂Is connected to the input terminal of a NOT gate Y₂Output end of the NMOS transistor M_aDrain electrode of (1) and NMOS tube M_bThe grid of the delay module is connected with the grid of the first transistor and then used as a data signal output end of the delay module;

NMOS tube M_aThe grid of the delay module is used as a reset signal input end of the delay module;

NMOS tube M_aSource electrode of and NMOS tube M_bSource electrode and NMOS transistor M_bThe drains are connected simultaneously and then connected to the power ground.

Preferably, the first register unit comprises a not gate Y₃And N D flip-flops;

NOT gate Y₃As a first register unit receiving a pulse signal V_P1An input terminal of (1);

NOT gate Y₃The output end of the D flip-flop is simultaneously connected with the clock signal input ends of the N D flip-flops;

d input ends of the first to Nth D triggers are respectively used as input ends of first to Nth thermometer codes of the first register unit;

q output ends of the first to Nth D flip-flops are respectively used as output ends of the first to Nth thermometer codes of the first register unit.

Preferably, the second register unit includes N D flip-flops, and clock signal input terminals of the N D flip-flops are connected at the same time and then serve as a clock signal input terminal of the second register unit;

d input ends of first to Nth D triggers in the second register unit are respectively used as input ends of first to Nth thermometer codes of the second register unit;

q output ends of first to Nth D flip-flops in the second register unit are respectively used as output ends of first to Nth thermometer codes of the second register unit.

Preferably, the random delay unit comprises a level shifter and a diffusion memristor R_MResistance R_rComparator U₂And an and gate X1;

the input end of the level shifter is used as the input end of the random time delay unit to receive the pulse signal V_P0And the input terminal of the level shifter is connected with one input terminal of the and gate X1;

a level shifter for shifting the received pulse signal V_P0Is lowered and the obtained programming pulse signal V is applied₁Output to diffused memristor R_MOne end of (1), diffusion memristor R_MAnother terminal of (1) and a resistor R_rAnd a comparator U₂The inverting input terminals of the two-way switch are connected simultaneously; resistance R_rThe other end of the first power supply is connected with a power ground;

comparator U₂For receiving a reference voltage V_refComparator U₂Is connected to the other input of and gate X1;

the output end of the AND gate X1 is used as the output end of the random delay unit to output a pulse signal V_P1。

Preferably, the control logic unit comprises a nor gate, an and gate X2, an and gate X3, an xor gate, a preset number counter and two fixed time-delay units, wherein the delay time of the first fixed time-delay unit is tau₀The delay time of the second fixed delayer is 2 tau₀；

One input end of the NOR gate is used as a control logic unit for receiving the pulse signal V_P1After the other input end of the NOR gate is simultaneously connected with the input ends of the two fixed time delayers, the NOR gate is used as a control logic unit to receive a voltage signal V_YAn input terminal of (1);

the output end of the NOR gate is simultaneously connected with one input end of the AND gate X2 and one input end of the AND gate X3;

the output end of the first fixed time delay is connected with the other input end of the AND gate X2, and the output end of the second fixed time delay is connected with the other input end of the AND gate X3;

and gateThe output end of the X2 is connected with one input end of the exclusive-OR gate, and the output end of the AND gate X2 is used as the clock signal Clk output by the control logic unit_LAn output terminal of (a);

the output end of the AND gate X3 is connected with the other input end of the XOR gate, and the output end of the XOR gate is connected with the reset signal input end of the preset number counter and then serves as the output end of the control logic unit for outputting a reset signal Rst;

the clock signal input end of the preset number counter is used for receiving an external clock signal Clk;

the output end of the preset number counter is used as a control logic unit to output a pulse signal V_P0To the output terminal of (a).

The constant-amplitude isosceles triangle wave with randomly changed frequency can be generated, the constant charging and discharging current is provided by using the current transmitter (CCII +), the random delay time of the diffusion memristor is coded by using the time interval measurement technology, and the obtained random thermometer code is used for controlling the size of the charging and discharging capacitor, so that the constant-amplitude isosceles triangle wave with randomly changed period and frequency is obtained. Therefore, the amplitude of the generated random frequency triangular carrier signal is controlled by using the current transmitter and the diffusion memristor in combination with the peripheral circuit, so that a random frequency isosceles triangular signal with equal amplitude is obtained, and the whole circuit structure and the design difficulty are greatly reduced.

The random frequency of the triangular wave is set by using the random delay time of the diffusion memristor, so that the scale and the power consumption of a circuit are reduced; on the other hand, in recent years, the integration research of the memristor and the traditional CMOS device is rapidly advanced, and commercial products are available, so that the technology provided by the invention provides a brand new idea for realizing the integration of the random PWM technology and low power consumption.

The constant-amplitude triangular wave signal generated by the invention can be used as a carrier signal to be applied to a random PWM technology.

Drawings

FIG. 1 is a schematic structural diagram of a random frequency triangular wave generator based on a diffusion memristor and a current conveyor according to the present invention; wherein, I_ZIs the current flowing from the current conveyor to the capacitor array or the current flowing from the capacitor array to the current conveyor; i is_XIs the current flowing through the X port of the current conveyor, V_XIs the voltage at the X port of the current conveyor;

FIG. 2 is a schematic diagram of the internal structure of the delay chain unit, the first register unit and the second register unit;

FIG. 3 is a schematic diagram of a first delay module;

FIG. 4 is a schematic diagram of a random delay unit; wherein, V₁Outputting a programming pulse voltage, V, for the level shifter₂Is a resistance R_rVoltage component of V₃Is a comparator U₂The output voltage signal;

FIG. 5 is a schematic diagram of a control logic unit;

FIG. 6 is a schematic diagram of waveforms of key signals in a triangular wave generation process;

FIG. 7 is a waveform diagram of a key signal in the random delay unit shown in FIG. 4;

FIG. 8 shows Ag: SiO₂A structural schematic of a diffused memristor;

FIG. 9 is a numerical distribution diagram of random delay times of the diffusion memristors.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.

Referring to fig. 1, the random frequency triangular wave generator based on the diffusion memristor and the current transmitter according to the present embodiment is described, and includes a control logic unit, a random delay unit, and a delay chainUnit, first register unit, second register unit, current transmitter, N NMOS tubes M₁To M_NCapacitor array and comparator U₁Resistance R_AResistance R_BAnd a resistance R_X(ii) a Wherein the capacitor array comprises a capacitor C₀To C_N；

The control logic unit is used for generating a pulse signal V_P0And simultaneously sending the data to the random delay unit and the delay chain unit; the reset circuit is also used for generating a reset signal Rst to reset the delay chain unit; and also for generating a clock signal Clk_LClock control is carried out on the second register unit; and is also used for receiving the pulse signal V output by the random delay unit_P1(ii) a And also for receiving the comparator U₁Voltage signal V output from output terminal_Y；

The random delay unit is realized by adopting a diffusion memristor and is used for receiving a pulse signal V_P0Processing to obtain pulse signal V_P1And will pulse signal V_P1Simultaneously inputting the signals to the control logic unit and the first register unit; wherein the pulse signal V_P1And pulse signal V_P0Are equal in period, and the pulse signal V_P1And pulse signal V_P0Are coincident in time, pulse signal V_P0High level duration t_pIs a fixed value, a pulse signal V_P1High level duration t_dIs a random value, and t_d＜t_p；

The random delay time of the diffusion memristor is equal to t_d；

A delay chain unit for receiving the pulse signal V_P0Generating an N-bit thermometer code and sending the N-bit thermometer code to a first register unit;

the first register unit receives the pulse signal V_P1At its pulse signal V_P1The falling edge time of the first register unit latches the received N-bit thermometer code and sends the latched result to the second register unit;

the second register unit is based on the received clock signal Clk_LAt its clock signal Clk_LTo the first rising edge timeLatching the latch result output by the register unit to obtain an N-bit thermometer code d₁To d_NAnd coding the N-bit thermometer by d₁To d_NRespectively sent to NMOS tubes M₁To M_NThe grid electrode controls the corresponding NMOS tube; wherein when d_iWhen 1, represents d_iIs at a high level; when d is_iWhen 0, represents d_iLow, i ═ 1, 2, 3 … … N;

NMOS tube M₁To M_NSource and capacitor C₀One end of each of the two ends is connected with a power ground;

NMOS tube M₁To M_NRespectively with the capacitor C₁To C_NIs connected to a capacitor C₀To C_NAnd the other end of the current transmitter, a Z port of the current transmitter and a comparator U₁Are connected simultaneously, and the voltage signal V of the connection point_CapAs a random-frequency triangular carrier signal generated by a triangular carrier generator, and a voltage signal V_CapIs a random frequency isosceles triangle wave signal with equal amplitude;

comparator U₁Non-inverting input terminal and resistor R_AAnd a resistor R_BAre connected at the same time, resistor R_BThe other end of the resistor R is connected with a power ground_AAnd the other end of the comparator U₁Output terminal of current conveyor, Y port of current conveyor and voltage signal V of control logic unit_YThe input ends are connected;

x port and resistor R of current transmitter_XIs connected to a resistor R_XThe other end of the first power supply is connected with a power ground;

comparator U₁The positive voltage input end is connected with a power supply V_DDComparator U₁Negative voltage input end is connected with a power supply V_SSAnd V is_DD＝-V_SS。

In this embodiment, the input of the delay chain unit is a pulse signal V_P0And a reset signal Rst, the states of N signals output by the delay chain unit, namely the N-bit thermometer code reflects the pulse signal V of the delay chain unit_P0Delay state of rising edge.

The input and output of the first and second register units are transmitted in the form of thermometer codes. Second register unit at Clk_LLatch the input at the time of rising edge, the first register unit is at V_P1Latching and inputting at the falling edge moment, wherein the input and output signals are logic level signals; counting the code d by temperature₁～d_NFor example, d_i1 denotes d_iIs high level, d_i0 denotes d_iIs low. d₁～d_NThe logic state of (B) reflects V_P1Relative to V at the falling edge time_P0Time delay of the rising edge instant of (i.e. t)_d。

The N-bit thermometer code is characterized in that 1 and 0 are distributed in a centralized way, 1 is concentrated at the front section of the code group, 0 is concentrated at the rear section of the code group, for example, when N is 8, the thermometer code d₁～d₈Can take the value of [11100000 ]]. This encoding is very common in time interval measurement techniques. For the present invention at V_P1When the falling edge moment of the first register unit is recorded, the number of 1 in the thermometer code output by the delay chain unit latched by the first register unit is m, and m tau represents V_P1Falling edge relative to V_P0The delay time of the rising edge is m tau t_d. Due to t_dIs random, τ is deterministic, so m is a random number. τ denotes the fixed delay time of each delay module.

d₁～d_NRespectively controlling NMOS tubes M of active switches₁To M_NOn/off of d_i1 represents M_iOn, d_i0 denotes M_iCutoff, therefore, d_i1 also denotes a capacitance C_iAnd C₀Parallel connection, otherwise, if d_i0 also denotes the capacitance C_iIs disconnected and does not participate in the charging and discharging process. So that the total capacitance of the capacitor array during a charge-discharge cycle is

Wherein, the capacitor C₀To C_NAll the capacitance values of (A) are C, C_THas a charging and discharging current of I_Z，I_ZIs provided by CCII + (i.e., a current conveyor).

In a specific application, V exists according to the characteristics of the current transmitter_X＝V_Y，I_X＝I_ZThus, it can be seen that: when the capacitor array is in the process of charging, I_ZFrom the current conveyor to the capacitor array, in this case V_CapIs smaller than the comparator U₁Positive phase input terminal voltage V_TH＝V_DDR_B/(R_A+R_B) Comparator U₁Has an output voltage of V_Y＝V_DDThus, there is I_Z＝I_X＝V_DD/R_XWhen the capacitor is charged to V_CapGreater than V_TH＝V_DDR_B/(R_A+R_B) Time, comparator U₁Has an output voltage of V_Y＝V_SS＝-V_DDThus, there is I_Z＝I_X＝-V_DD/R_X，I_ZThe capacitor array begins to discharge from the capacitor array to the current conveyor, at which time the comparator U₁The positive phase input terminal voltage of_TH＝-V_DDR_B/(R_A+R_B) (ii) a When the capacitor discharges to V_CapLess than-V_DDR_B/(R_A+R_B) Time, comparator U₁Is changed back to V_Y＝V_DDThe capacitor starts to charge again; this is repeated. The charging and discharging currents on the capacitor array are equal in magnitude and are due to C_TIs relatively large and I_ZIs relatively small, so that the voltage V on the capacitor is generated during the charging and discharging processes_CapApproximately linearly varying.

To sum up, during charging, V_Capfrom-V_DDR_B/(R_A+R_B) Linearly increasing to V_DDR_B/(R_A+R_B) At time of discharge, V_CapThen by V_DDR_B/(R_A+R_B) Linear down to-V_DDR_B/(R_A+R_B) The charging and discharging time is equal, therefore, V_CapIs a constant-amplitude isosceles triangular wave signal with a period of 4C_TR_BR_X/(R_A+R_B)；d₁～d_NThe larger the number m of (1) s, the larger C_TThe larger the triangular wave period is, the longer the triangular wave period is, and the lower the frequency is; the smaller m is, C_TThe smaller, the shorter the period, the higher the frequency; due to t_dIs random, d₁～d_NThe number m of 1 s is also random, and the period of the triangular wave is random.

The diffused memristor has two characteristics: 1. the device is switched from a high-resistance state to a low-resistance state under the action of a certain voltage pulse, and a random delay time is required; 2. after the voltage pulse is removed, the device can be automatically restored to a high-resistance state from a low-resistance state, namely volatility.

The diffusion memristor is very suitable for being applied to a random pulse width modulation technology, the distribution range of random time delay can be adjusted to a required working frequency range, the distribution range is wider in a low-frequency range, the randomness is better, and the random pulse width modulation technology is mainly applied to the low-frequency range; due to volatility, the diffusion memristor does not need to erase a circuit, and the complexity of circuit design is reduced; on the other hand, the difficulty of integrating the diffusion memristor and the CMOS device is lower.

The triangular carrier generator according to the embodiment can generate a constant-amplitude isosceles triangular wave with randomly changing frequency, firstly, a current transmitter (CCII +) is used for providing constant charging and discharging current, then, a time interval measurement technology is used for coding random delay time of a diffusion memristor, and an obtained random thermometer code is used for controlling the size of a charging and discharging capacitor, so that the constant-amplitude triangular wave with randomly changing period and frequency is obtained. Therefore, the amplitude of the generated random frequency triangular carrier signal is controlled by using the current transmitter and the diffusion memristor in combination with the peripheral circuit, so that a random frequency isosceles triangular signal with equal amplitude is obtained, and the whole circuit structure and the design difficulty are greatly reduced.

The waveform of the key signal in the triangular wave generation process is given in fig. 6, where V_CapIs a constant-amplitude isosceles triangular wave signal, and the period is variable. V_P1At low level, when V_CapDischarge to below-V_TH，V_YFrom V_DDBecomes V_SSThis will result in Clk_LAppearA high level narrow pulse, Clk_LLatches the thermometer code obtained by the first register unit in the previous triangular wave generation process into the second register unit, and uses the code to control the total capacitance value of the capacitor array in the first triangular wave generation process in fig. 6. Clk_LAfter the high-level narrow pulse is ended, the Rst generates a high-level narrow pulse, the high level of the Rst resets the output state of the delay chain unit, after the reset is ended, the Rst is restored to be a low level, and then the control logic unit outputs a pulse signal V_P0，V_P0High level duration t_pIs fixed, and the random delay unit is receiving V_P0Then outputs a pulse signal V_P1，V_P1Rising edge time V of_P0Synchronous, but high level duration t_dIs random and satisfies t_d≤t_p；V_P0Input delay chain unit, pair of delay chain units V_P0Is delayed at V_P1The falling edge first register unit latches the thermometer code on the delay chain unit, which is used to set the total capacitance value of the capacitor array in the second triangular wave generation process in fig. 6. In summary, when the previous triangle wave ends, the second register unit obtains a random N-bit thermometer code d₁～d_NAnd using it to determine the period of the triangular wave currently to be generated, d₁～d_NFor the last triangular wave duration V_P1The pulse width, i.e.: for t_dIs quantized, and d₁～d_NIs constant during the current charge-discharge cycle.

Further, referring specifically to fig. 2, the delay chain unit includes N delay modules, where the N delay modules are cascaded in series, and a signal input end of a first delay module is used as the delay chain unit to receive the pulse signal V_P0An input terminal of (1);

each delay module is used for delaying the rising edge of an input signal of the delay module, and delay signal values output by the first to Nth delay modules are respectively used as first to Nth thermometer codes output by the delay chain unit;

the reset signal input end of each delay module is used for receiving a reset signal Rst, and when the reset signal Rst is at a high level, the output states of the N delay modules are reset to be 0.

In specific application, the N cascaded delay modules are sequentially a first delay module to an Nth delay module from left to right, and the signal input end of the first delay module is used as a delay chain unit to receive a pulse signal V_P0An input terminal of (1); the signal output end of the first delay module is connected with the signal input end of the second delay module, the signal output end of the second delay module is connected with the signal input end of the third delay module, … … is repeated, and the signal output end of the (N-1) th delay module is connected with the signal input end of the Nth delay module.

In the preferred embodiment, the input of the delay chain unit is a pulse signal V_P0And a reset signal Rst, wherein the delay chain unit is formed by cascading N delay modules, each delay module generates a certain delay for the rising edge of the input signal and resets the output state to 0 at the high level of the Rst, and the input of the first delay module is V_P0Then pulse signal V_P0The rising edge of the delay chain is gradually conducted in the delay chain unit, if the output of one delay module is 1, V is shown_P0Passes through the delay module and passes through the time that requires τ; if the output of one delay module is 0, V is indicated_P0The rising edge has not yet come or is passing. For example, the output of the m-th delay cell is 1 (denoted by V)_P0The delay cell that is the input is the 1 st) and the output of the m +1 th delay cell is 0, then V is considered_P0Is conducted for m tau in the delay chain, and thus, V_P1At the falling edge time, the output state of the delay chain unit reflects V_P1Relative to V_P0Random delay time t of rising edge_d。

Further, referring specifically to FIG. 3, the delay module includes a NOT gate Y₁NOT gate Y₂NMOS transistor M_aAnd NMOS transistor M_b；

NOT gate Y₁The input end of the delay module is used as the data signal input end of the delay module;

NOT gate Y₁Of the output nand gate Y₂Is connected to the input terminal of a NOT gate Y₂Output end of the NMOS transistor M_aDrain electrode of (1) and NMOS tube M_bThe grid of the delay module is connected with the grid of the first transistor and then used as a data signal output end of the delay module;

NMOS tube M_aThe grid of the delay module is used as a reset signal input end of the delay module;

NMOS tube M_aSource electrode of and NMOS tube M_bSource electrode and NMOS transistor M_bThe drains are connected simultaneously and then connected to the power ground.

In the preferred embodiment, the first delay module is used for explanation, and the NMOS transistor M_bThe high level of Rst enables NMOS transistor M to be used as MOS capacitor_aConducting to connect the NMOS transistor M_bThe charge stored on the delay module quickly drains away so that the output state of the delay module is reset to 0. V_P0The rising edge of the NMOS transistor M_bThe parasitic capacitance of the grid starts to be charged from the reset state, so the output of the delay module cannot follow V_P0The high level is immediately changed to high level, and the output reaches the high level threshold value after a delay time τ, which is determined by the design parameters of the delay unit module and can be considered as a fixed value. At the beginning of each working cycle, Rst resets the output state of the delay unit module, so that the delay unit module only has a pair V_P0Delay of the rising edge of (c). The rest N-1 delay modules in the delay chain unit have the same structure as the unit, the delay time of each delay module is tau, the reset operation is carried out by utilizing the high level of Rst, and the difference is only that the input signals of the cascade NOT gate are different.

Further, with particular reference to FIG. 2, the first register unit includes a NOT gate Y₃And N D flip-flops;

NOT gate Y₃As a first register unit receiving a pulse signal V_P1An input terminal of (1);

NOT gate Y₃The output end of the D flip-flop is simultaneously connected with the clock signal input ends of the N D flip-flops;

d input ends of the first to Nth D triggers are respectively used as input ends of first to Nth thermometer codes of the first register unit;

q output ends of the first to Nth D flip-flops are respectively used as output ends of the first to Nth thermometer codes of the first register unit.

Further, referring specifically to fig. 2, the second register unit includes N D flip-flops, and clock signal input terminals of the N D flip-flops are connected at the same time and then serve as a clock signal input terminal of the second register unit;

d input ends of first to Nth D triggers in the second register unit are respectively used as input ends of first to Nth thermometer codes of the second register unit;

q output ends of first to Nth D flip-flops in the second register unit are respectively used as output ends of first to Nth thermometer codes of the second register unit.

In the preferred embodiment of the invention, the first register unit and the second register unit are both realized by N D triggers, and the invention has simple structure and convenient realization.

Further, referring specifically to fig. 4, the random delay unit includes a level shifter, a diffusion memristor R_MResistance R_rComparator U₂And an and gate X1;

the input end of the level shifter is used as the input end of the random time delay unit to receive the pulse signal V_P0And the input terminal of the level shifter is connected with one input terminal of the and gate X1;

a level shifter for shifting the received pulse signal V_P0Is lowered and the obtained programming pulse signal V is applied₁Output to diffused memristor R_MOne end of (1), diffusion memristor R_MAnother terminal of (1) and a resistor R_rAnd a comparator U₂The inverting input terminals of the two-way switch are connected simultaneously; resistance R_rThe other end of the first power supply is connected with a power ground;

comparator U₂For receiving a reference voltage V_refComparator U₂Is connected to the other input of and gate X1;

the output of AND gate X1 is taken as randomThe output end of the delay unit outputs a pulse signal V_P1。

In the preferred embodiment, a circuit structure of the random delay unit is provided, and referring to fig. 4 specifically, the circuit parameters may be selected as follows: pulse signal V_P0Has a frequency of 1kHz and a pulse width of 300 mus, and a programming pulse voltage V is obtained by reducing the amplitude of the high level through level shifting₁，V₁Amplitude of 0.5V (0.5V for high level and 0V for low level), V_ref＝0.15V，R_rThe output waveform obtained under this condition is schematically shown in fig. 7.

The principle of operation of the random delay unit is analyzed in conjunction with FIG. 4 as follows, at pulse V₁Under the action of high level, the memristor R is diffused for a certain time_MFrom an initially high-resistance state to a low-resistance state, such that V₁Through R_MAnd R_rPartial pressure value V of₂Also increases to be higher than the comparator U at a certain time₂Reference voltage V of_refAt this moment, the comparator U₂Output voltage V of₃It is switched from high to low. Memristor R due to diffusion_MRandomness of resistance change, voltage V₂Increase to above V_refA certain random delay time t is needed to pass before_dTherefore, the comparator U₂Output voltage V of₃Is of high level duration t_d；V_P0And V₃Output V after AND operation_P1It is easy to know that the high level duration is t_dSee fig. 7.

In specific application, the diffusion memristor R_MOptionally Ag or SiO₂The diffusion memristor is realized by Ag: SiO with specific reference to figure 8₂The diffusion memristor is made of Pt/Ag/Ag SiO₂The Pt/layer stack consists of a 15nm thick bottom Pt electrode at the bottom, a 10nm Ag SiO2 blanket layer on top of a 5nm Ag metal reservoir, a 20nm Pt/30nm Au deposited layer at the top, a 30nm layer to improve the electrical contact characteristics of the pad, and a 5nm Ag reservoir to supply enough Ag atoms. According to Ag to SiO₂Whether a conductive channel formed by Ag nano particles exists in the layer or not, and the memristor can be in a low-resistance stateSwitching between high resistance states, so that Ag is SiO₂The layer may be referred to as a resistive layer. In addition, the resistance state of the memristor is volatile, and under the action of a certain voltage pulse, after a random delay time, the device is switched from a high resistance state to a low resistance state, and automatically restores to the high resistance state after the applied voltage pulse is removed, which is different from the common nonvolatile memristor. The switching of the resistance state is due to the separation of Ag nanoparticles from the Ag reservoir and in Ag SiO₂A conductive channel is formed in the layer, and the diffusion process of the Ag nano particles is a random process, so that the resistance state switching of the diffusion memristor is random, and random delay time t can be used_dThis randomness is characterized quantitatively.

Random delay time t_dDistribution of (a) and input programming pulse voltage (V)₁Is related to the amplitude of (d), t can be adjusted accordingly_dSo that t is distributed_d≤t_pIs satisfied. In FIG. 9 is given at V₁T measured at different values of (0.4 to 0.9V)_dThe higher the programming pulse voltage amplitude is, the shorter the average delay time is, and the narrower the distribution range is.

Further, referring specifically to fig. 5, the control logic unit includes a nor gate, an and gate X2, an and gate X3, an xor gate, a preset number counter, and two fixed time-delay units, wherein the delay time of the first fixed time-delay unit is τ₀The delay time of the second fixed delayer is 2 tau₀；

One input end of the NOR gate is used as a control logic unit for receiving the pulse signal V_P1After the other input end of the NOR gate is simultaneously connected with the input ends of the two fixed time delayers, the NOR gate is used as a control logic unit to receive a voltage signal V_YAn input terminal of (1);

the output end of the NOR gate is simultaneously connected with one input end of the AND gate X2 and one input end of the AND gate X3;

the output end of the first fixed time delay is connected with the other input end of the AND gate X2, and the output end of the second fixed time delay is connected with the other input end of the AND gate X3;

the output end of the AND gate X2 is connected with one input end of the exclusive-OR gate, and the output end of the AND gate X2 is used as the clock signal Clk output by the control logic unit_LAn output terminal of (a);

the output end of the AND gate X3 is connected with the other input end of the XOR gate, and the output end of the XOR gate is connected with the reset signal input end of the preset number counter and then serves as the output end of the control logic unit for outputting a reset signal Rst;

the clock signal input end of the preset number counter is used for receiving an external clock signal Clk;

the output end of the preset number counter is used as a control logic unit to output a pulse signal V_P0To the output terminal of (a).

In this embodiment, the input to the control logic is V_Y、V_P1The output is V_P0Rst and Clk_LThe function of the control logic is shown in FIG. 5 when V_P1At low level, the input voltage V_YFrom V_DDVariable V_SSMeanwhile, the output of the nor gate is changed from low to high, and the outputs of the nor gate are respectively input into and gates X2 and X3. Voltage V_YIs delayed by a time delay tau₀The obtained signal is input into an AND gate X2, and the output Clk of the AND gate X2_LWill be at a voltage V_YAfter the end of the falling edge, a period of time T₀High-level narrow pulses of (2); similarly, the output of AND gate X3 will be at V_YA time of 2 tau after the end of the falling edge₀High-level narrow pulses of (2); the two high-level narrow pulses pass through an exclusive-or gate to obtain an output reset signal Rst, and the reset signal Rst appears for a period of time tau₀And the high level narrow pulse is in the clock signal Clk_LAnd the high level narrow pulse occurs after the end. The reset signal Rst is used as a reset signal of the preset number counter, and when the reset signal Rst is reset at a high level, the reset signal Rst is at a high level end time, that is, at a reset completion time, the preset number counter starts counting the clock signal Clk, and causes the pulse signal V to be a pulse signal V_P0From low to high, with a lag of V at this time_YHas a falling edge of 2 tau₀The time of (d); when the preset number counter counts to a preset value D_pTime, pulse signal V_P0From high to low, the high level lasts for t_p＝D_pT, T is the period of the clock Clk, so T_pIs stationary.

It is noted that the random delay unit enables the pulse signal V to be pulsed_P1Following pulse signal V_P0While changing from low to high, when the pulse signal V is_P1When the level is high, the nor gate output of the control logic unit is always low, so that narrow pulses do not appear at the outputs of X2 and X3, and the clock signal Clk is high_LAnd the potential of the reset signal Rst remains unchanged; and due to the pulse signal V_P1Rising edge distance voltage signal V_YHas a falling edge of 2 tau₀Time of (1), thus V_P1Does not affect the Clk_LAnd Rst.

There is also a case, as shown in FIG. 6, when V_YIs a V_SSWhen, V_P1The NOR gate output is changed from high to low, but since the output of the random delay unit is kept low, the outputs of X2 and X3 are kept unchanged, Clk_LAnd Rst remains unaffected.

In general, the control logic unit is only at V_P1Is low level, and V_YWhen a falling edge occurs, V is enabled_P0Rst and Clk_LIs changed to start a new duty cycle, V_P0The rising edge of the random delay unit enables the random delay unit to start working; clk_LCauses the second register unit to obtain the random value d stored in the first register unit₁～d_NAnd sending the triangular wave to a capacitor array for controlling the period of the triangular wave generated currently; the high-level narrow pulse of Rst enables the output states of all delay modules in the delay chain unit to reset and clear, and the delay chain unit resets V after clearing is completed_P0Is delayed at V_P1The falling edge first register unit latches the random value of the delay chain unit, and the random value is used for controlling the period of the next triangular wave.

Although the invention herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the present invention. It is therefore to be understood that numerous modifications may be made to the illustrative embodiments and that other arrangements may be devised without departing from the spirit and scope of the present invention as defined by the appended claims. It should be understood that features described in different dependent claims and herein may be combined in ways different from those described in the original claims. It is also to be understood that features described in connection with individual embodiments may be used in other described embodiments.