Switching power supply and improvements thereof
阅读说明:本技术 开关电源及其改进 (Switching power supply and improvements thereof ) 是由 黄新年 于 2016-05-03 设计创作,主要内容包括:本发明针对开关电源及其改进。根据一个实施方式,提供了开关电源。该开关电源包括:第一电源级,其形成中间调节电压;以及第二电源级,其配置成接受中间调节电压并配置为形成调节输出电压,其中当电源启动时中间电压被设置到初始目标电平,以及其中中间调节电压在电源的稳态操作期间被设置到第二目标电平。(The present invention is directed to switching power supplies and improvements thereto. According to one embodiment, a switching power supply is provided. The switching power supply includes: a first power stage forming an intermediate regulated voltage; and a second power supply stage configured to accept the intermediate regulated voltage and configured to form a regulated output voltage, wherein the intermediate voltage is set to an initial target level when the power supply is started, and wherein the intermediate regulated voltage is set to a second target level during steady state operation of the power supply.)
1. A switching power supply comprising a power supply stage having a controller circuit configured to control switching in the power supply stage, and the controller circuit receiving its operating power from a capacitor during a start-up phase, wherein the capacitor is charged by a rectified Alternating Current (AC) signal via a transistor switch, and the controller circuit comprises a voltage regulator, wherein the controller circuit receives its operating power from the voltage regulator after the start-up phase, wherein the transistor switch is initially closed and the capacitor is charged to an initial voltage level, and the transistor switch is open when the initial voltage level is reached.
2. The switching power supply of claim 1 wherein during the startup phase, a controller circuit controls switching in the power supply stage to form a regulated voltage, and the switching stops if the voltage level on the capacitor falls below a threshold.
3. The switching power supply of claim 2 wherein when the voltage approaches the threshold, the transistor switch is closed to charge the capacitor to inhibit the voltage on the capacitor from reaching the threshold, thereby preventing the switching from being stopped.
4. The switching power supply of claim 3 wherein the power supply stage comprises a Power Factor Correction (PFC) stage that forms an intermediate regulated voltage, and wherein the switching power supply further comprises a DC-to-DC converter, and wherein the DC-to-DC converter is configured to accept the intermediate regulated voltage, and wherein an output of the DC-to-DC converter powers the voltage regulator.
5. The switching power supply of claim 4 wherein the initial voltage level is about 15.3 to 15.5 volts, and wherein the threshold is about 10.0 volts.
6. The switching power supply of claim 5 wherein said transistor switch is closed when the voltage on said capacitor reaches 11.0 volts.
7. The switching power supply of claim 1, wherein the current used to charge the capacitor is controlled by a depletion mode MOSFET.
Technical Field
The present invention relates to the field of switching power supplies.
Background
An off-line power supply (off-line power supply) receives power from an Alternating Current (AC) source and provides a voltage regulated Direct Current (DC) output that may be used to power a load. An exemplary offline power supply includes a Power Factor Correction (PFC) stage and a DC-to-DC converter stage. The PFC stage receives the AC input signal, performs rectification, and maintains current drawn from the AC source substantially in phase with the AC voltage so that the power supply appears as a resistive load to the AC source. The DC-to-DC converter stage receives the rectified output of the PFC stage and generates a voltage regulated DC output that may be used to power a load. The rectified output of the PFC stage is typically at a higher voltage and more loosely regulated than the output of the DC-to-DC stage.
It is desirable to provide an improved switching power supply.
Disclosure of Invention
The present invention is directed to switching power supplies and improvements thereto. According to one embodiment, a switching power supply is provided. The switching power supply includes: a first power stage forming an intermediate regulated voltage; and a second power supply stage configured to accept the intermediate regulated voltage and configured to form a regulated output voltage, wherein the intermediate voltage is set to an initial target level when the power supply is started, and wherein the intermediate regulated voltage is set to a second target level during steady state operation of the power supply.
The initial target level may be higher than the second target level. The intermediate voltage may be set to a third target level in a light load state. The third target level may be lower than the second target level. The second target level may be about 380 volts DC. The first power supply stage may be a power factor correction stage and the second power supply stage may be a DC-to-DC converter stage. The initial target level may be reached by drawing current from the feedback voltage node. The switched current source may be coupled to the feedback voltage node. The switching current source may be controlled by comparing the soft-start voltage ramp to a reference voltage, and may be disabled when the soft-start voltage ramp reaches a reference level.
According to another embodiment, a switching power supply is provided. The switching power supply comprises a power supply stage having a controller circuit, the controller circuit comprising a voltage regulator, wherein during a startup phase of the switching power supply the voltage regulator forms a first regulated output for powering the controller circuit, and wherein after the startup phase the first regulated output is coupled to a second voltage source, the second voltage source being regulated at a higher level than the first regulated output, thereby disabling the voltage regulator.
The first regulated output may be coupled to a second voltage source via a diode. The controller circuit may control switching in a power supply for generating the second voltage source. The second voltage source may provide power to the controller circuit after the start-up phase. The switching power supply may also include a Power Factor Correction (PFC) stage that forms an intermediate regulated voltage. The power supply stage may include a DC-to-DC converter. The DC-to-DC converter may be configured to accept the intermediate regulated voltage. The output of the DC-to-DC converter may comprise the second voltage source. The voltage regulator may receive power from the PFC stage. The PFC stage may include a main inductor. Electrical energy may be provided to the voltage regulator by a current induced in a second inductor that is inductively coupled to the main inductor.
According to another embodiment, a switching power supply is provided. The switching power supply includes a power supply stage having a controller circuit that receives power from a capacitor during a startup phase, wherein the capacitor is charged by a rectified Alternating Current (AC) signal via a transistor switch, and the controller circuit includes a voltage regulator, wherein the controller circuit receives power from the voltage regulator after the startup phase.
The transistor switch may be initially closed. The capacitor may be charged to an initial voltage level, and the transistor switch may be turned off when the initial voltage level is reached. During the startup phase, the controller circuit may control switching in the power supply stage to form the regulated voltage. The switching may stop if the voltage level on the capacitor falls below a threshold. When the voltage approaches the threshold, the transistor switch may be closed to charge the capacitor and inhibit the voltage on the capacitor from reaching the threshold, thereby preventing switching from being stopped.
The power supply stage may include a Power Factor Correction (PFC) stage that forms an intermediate regulated voltage. The switching power supply may further include a DC-to-DC converter. The DC-to-DC converter may be configured to accept the intermediate regulated voltage. The output of the DC-to-DC converter may provide power to the voltage regulator. The initial voltage level may be about 15.3 to 15.5 volts and the threshold may be about 10.0 volts. When the voltage on the capacitor reaches 11.0 volts, the transistor switch may be closed. The transistor switch may be a depletion mode MOSFET.
According to one embodiment, a switching power supply is provided. The switching power supply includes: a first power supply stage forming an intermediate regulated voltage, the first power supply stage including a first controller circuit for controlling switching in the first power supply stage for forming the intermediate regulated voltage, wherein the intermediate voltage is set to an initial target level when the power supply is started, and wherein the intermediate regulated voltage is set to a second target level during steady state operation of the power supply, and wherein the controller circuit receives power from a capacitor during a start-up phase, wherein the capacitor is initially charged by a rectified Alternating Current (AC) signal via a transistor switch, and wherein the transistor switch is closed unless a voltage on the capacitor is near a threshold; and a second power supply stage configured to accept the intermediate regulated voltage and configured to form a power supply output voltage, the second power supply stage comprising a controller circuit for controlling switching in the second power supply stage, and the controller circuit of the second power supply stage comprising a voltage regulator, wherein during a startup phase of the switching power supply, the voltage regulator forms a first regulated output for powering the controller circuit of the second power supply stage, and wherein after the startup phase, the first regulated output is coupled to the power supply output voltage, the power supply output voltage being regulated at a higher level than the first regulated output, thereby disabling the voltage regulator.
According to another embodiment, a switching power supply is provided. The switching power supply includes: a first power stage forming an intermediate regulated voltage; and a second power supply stage configured to accept the intermediate regulated voltage and configured to form a regulated output voltage. The first power supply stage monitors an error signal representing a difference between the intermediate regulated voltage and a desired level of the intermediate regulated voltage to detect a light load condition. When the error signal falls below a first threshold, the first power supply stage enters a first power saving mode in which the switching frequency in the first power supply stage is reduced. When the error signal falls below a second threshold, the first power supply stage enters a second power saving mode in which switching in the first power supply stage is performed in bursts.
The bias circuit providing operating power to the first power supply stage may provide reduced current between switching bursts in the second power saving mode. The error signal may be representative of the input power provided to the first power supply stage. The switching frequency may be reduced from 67.5kHz to 50kHz in the first power saving mode. The first power supply stage may remain in the first power saving mode until the error signal rises above the first threshold by a hysteresis margin. The second threshold may be lower than the first threshold. When the error signal remains below the second threshold, switching in the first power supply stage is stopped. The switching power supply may include an optocoupler that provides a control signal from the first power supply stage to the second power supply stage, the control signal for enabling and disabling switching in the second power supply stage. The current in the optocoupler may disable switching in the second power supply, and the lack of current in the optocoupler may enable switching in the second power supply stage.
According to another embodiment, a switching power supply is provided. The switching power supply includes: a first power stage forming an intermediate regulated voltage; and a second power supply stage configured to accept the intermediate regulated voltage and configured to form a regulated output voltage. A signal representative of the output current of the second power supply stage is monitored to detect a light load condition. A signal representative of the output current of the second power supply stage is also monitored to detect an overcurrent condition.
When a light load condition is detected, the second power stage may enter a power saving mode in which switching is performed in bursts. A feedback signal representative of the output voltage of the second power supply stage may be monitored in a power saving mode of operation, and when the feedback signal falls below a threshold, switching may be enabled until the feedback signal rises above the threshold by a hysteresis margin. The switching in the second power supply stage may be performed in the power saving mode with a constant switching frequency. When not in the power saving mode, switching in the second power supply stage may be performed according to frequency modulation. In the power saving mode, the output voltage may be adjusted by changing the duration of the switching bursts compared to the period between bursts. The constant switching frequency may be user selectable. The constant switching frequency may be user selectable by a reference voltage. A signal representative of the output current of the second power supply stage may traverse a first path that averages the output current and detects a light load condition. A signal representative of the output current of the second power supply stage may traverse a second path for overcurrent protection. The path for the signal representing the output current of the second power supply stage may have a user selectable first pole and a user selectable second pole for frequency compensation. The level of output current required to enter the power saving mode may be user selectable.
These and other embodiments are described herein.
Drawings
The present invention is described with respect to certain exemplary embodiments thereof and with reference to the accompanying drawings, in which:
FIG. 1 shows a block schematic diagram of a two-stage offline power supply according to an embodiment of the present invention;
FIG. 2 shows a schematic diagram of a power factor correction circuit according to an embodiment of the invention;
FIG. 3 shows a block schematic diagram of a controller of a power factor correction circuit according to an embodiment of the invention;
fig. 4 (including fig. 4A, 4B, 4C and 4D) shows a detailed schematic diagram of a PFC converter and PFC controller according to an embodiment of the present invention;
fig. 5 shows a schematic diagram of a resonant switching converter according to an embodiment of the invention;
FIG. 6 illustrates a voltage regulator of a power supply controller according to an embodiment of the present invention;
FIG. 7 (including FIGS. 7A, 7B, 7C and 7D) shows a detailed schematic diagram of a DC to DC converter and a DC to DC converter controller according to an embodiment of the invention;
FIG. 8 (including FIGS. 8A, 8B, 8C, and 8D) shows a schematic diagram of a DC to DC converter transformer circuit according to an embodiment of the invention; and
FIG. 9 shows a schematic diagram of a circuit for activating an under-voltage-lockout switch, according to an embodiment of the invention.
Detailed Description
The present invention is directed to an improved switching power supply. According to embodiments of the present invention, an improved auxiliary power supply is provided. The DC output of the switching power supply may be used as an auxiliary power supply for supplying power to the control circuit of the switching power supply. For example, in an offline two-stage switching power supply, one or more auxiliary DC outputs of the DC-to-DC converter stage may provide power to the control circuitry of the PFC stage and the control circuitry of the DC-to-DC converter stage.
When the switching power supply is started, the PFC stage needs to generate its rectified output voltage V before the DC output can be used as an auxiliary power supplyDCAnd the DC-to-DC converter needs to generate the DC output. The auxiliary power may be provided by an inductor coupled to the PFC main inductor during a start-up period before the DC output of the DC-to-DC converter stage is available to provide the auxiliary power. In particular, at the start of switching in the PFC stage, the switching current through the PFC main inductor may be used to induce a current in the coupled inductor which may be used to generate the auxiliary power. However, in some instances, switching in the PFC stage may stop prematurely. For example, when the AC input voltage applied to the PFC stage is unexpectedly high, this may cause the PFC stage to stop switching before sufficient auxiliary power is generated by the coupled inductor. This situation may occur if the AC input is above a target level set for the DC output of the PFC stage. The resulting lack of auxiliary power may cause the entire switching power converter to shut down. For example, in the case where the target level of the PFC output stage is 380 volts and the AC input voltage is higher than 380 volts, this may result in the switching power supply not being able to start operating.
According to one embodiment of the invention, the target level V of the PFC stage outputDCIs temporarily set to a level above its steady state target level. For example, the steady state target level of the PFC stage output may be 380 volts DC. At start-up of the switching power supply, the target level may be set to an elevated level above 380 volts. For example, the initial elevated level may be 440 volts. If the AC input voltage is above 380 volts DC but below 440 volts DC, the switching power supply may be expected to successfully begin operation.The boosted target level is preferably set to a level above the expected range of AC input voltages. Once the power supply is started and running, the target level of the PFC output may return to its steady state level. In this example, the level may return to 380 volts.
As described above, the PFC stage output may be configured for two different target levels: one for starting the power supply and one for steady state operation. In another embodiment, the PFC stage may be configured for one or more additional target levels. For example, in light load conditions, the PFC stage may operate more efficiently if its output voltage level is adjusted downward. For example, for light load conditions, the PFC may be configured for a third target level that is lower than the first target level. This may also be the target level for a "full load" condition when the steady state target level is 380 volts DC. However, under light load conditions, the target level may be reduced to approximately 342 volts DC.
According to an embodiment of the present invention, a power saving mode of operation is provided for a Power Factor Correction (PFC) stage of a switching power supply. The power saving mode of operation is entered in a light load condition. The light load condition can be sensed by monitoring the signal VEAO, which is indicative of the actual level V at the output voltageDCAnd a desired level of the output voltage. Thus, the level of VEAO may also represent the input power to the PFC stage. In a first power saving mode of operation of the PFC stage, the switching frequency of the PFC stage is reduced (e.g., from 67.5kHz to 30 kHz). In a second power saving mode of operation of the PFC stage, the PFC stage enters a "burst" or "kick" mode of operation in which switching is stopped between bursts of switching. Further, the bias circuit supplying operating power to the PFC stage may provide a reduced current to the controller circuit of the PFC stage when the switching is stopped in the second power saving mode of operation. The first power saving mode of operation is preferably entered when the level of VEAO falls below a first threshold (e.g., 0.75 volts). The PFC stage preferably stays in the first power saving mode of operation unless the level of VEAO rises above the first threshold by a hysteresis margin (e.g., 0.25 volts). When the level of VEAO falls below a second threshold (e.g., 0.5 volts) lower than the first threshold, it is preferable to go to the second thresholdA power saving mode of operation.
When the level of VEAO falls below the second threshold, the switching stops until the level of VEAO rises above the second threshold; thus, when the level of VEAO rises above and falls below the second threshold, the switching is performed in bursts.
According to one embodiment of the invention, a power saving mode of operation is provided for a DC-to-DC converter stage of a switching power supply. A power saving mode of operation of the DC-to-DC converter stage is entered in a light load condition. The light load condition may be sensed by monitoring a signal IPLIMIT representing the output current of the DC-to-DC converter stage. The instantaneous level of IPLIMIT represents the output current of the DC-to-DC stage, while the average level of IPLIMIT represents the output power of the DC-to-DC stage. The instantaneous level of IPLIMIT is preferably monitored to detect an overcurrent condition, while the average level of IPLIMIT is also monitored to detect a light load condition.
In a power saving mode of operation of the DC-to-DC converter stage, a DC-to-DC converter "burst" or "jerk" mode of operation is enabled. When in the shoot mode, the feedback signal VFB representing the output voltage of the DC-to-DC converter stage falls below a threshold value (e.g., 2.495 volts), switching of the DC-to-DC converter stage is enabled. When the feedback signal rises above the threshold by a hysteresis margin (e.g., 0.01 volts), then switching is disabled; thus, when the level of VFB rises above and falls below the threshold, the switching is performed in bursts. Furthermore, frequency modulation is preferably used to regulate the output voltage when the DC-to-DC converter is not in a shoot through mode. When the DC-to-DC converter is in the shoot mode, the switching frequency is preferably kept constant during a switching burst. Thus, the output voltage is regulated by varying the duration of the switching bursts (compared to the period between bursts when the switching is stopped). The constant switching frequency used during a switching burst is preferably user selectable when the DC-to-DC converter stage is in a jerk mode. For example, in case the DC-to-DC converter stage is a resonant converter, the rush mode switching frequency may be set at: a resonant frequency; twice the resonant frequency; or three times the resonant frequency.
Fig. 1 shows a block schematic diagram of a two-stage offline power supply 100 according to an embodiment of the present invention. As shown in FIG. 1, a Power Factor Correction (PFC)
The
Fig. 2 shows a schematic diagram of a Power Factor Correction (PFC)
Resistor RACIs coupled to a voltage sense input of
The output voltage sense signal VFB is provided by a resistor R having a first terminal and a second terminalAForm the first terminal coupled to the output voltage VDCThe second terminal is coupled to a resistor RBThe first terminal of (1). Resistor RBMay be coupled to a ground node. Resistor RAAnd RBForming a voltage divider in which the signal VFB is present across a resistor RAAnd RBFormed at a node therebetween. The signal VFB represents the output voltage VDC。
Inductor L1Inductively coupled to a main PFC inductor LA. As described above, switch QAAnd QBMake current flow in the inductor LAAnd (3) medium flow. This is also at capacitor L1A current is induced in the inductor. This induced current is supplied by diode D1And D2Rectifying and supplying capacitor C21、C22、C23And C24To form the DC auxiliary
Fig. 3 shows a schematic block diagram of the
In an embodiment, a reference voltage of 2.5 volts corresponds to the PFC output VDCAnd a reference voltage of 2.25 volts corresponds to the PFC output VDCTo a target level of 342 volts DC. Obviously, different levels may be selected, for example by changing the reference voltage level.
As shown in fig. 3, the feedback signal VFB at the first input terminal of the transconductance error amplifier GMv is also coupled to a controllable or switched current source. More specifically, feedback signal VFB is coupled to switch S1The first terminal of (1). Switch S1Is coupled to a current source I1The first terminal of (1). Current source I1Is coupled to the ground node. When the switch S1When closed, current passes through a current source I1Which lowers the voltage level of VFB. This voltage drop is due to the current drawn through the feedback resistor RA(FIG. 2). As a result, the PFC output VDCThe target level of (2) is increased. Current source I1May be activated at power-up and deactivated during steady state operation.
Switch S1Can be activated by the signal BF as described in more detail in connection with fig. 4. Signal BF preferably closes switch S1And thereby activates the current source I at power-up1. The signal BF also preferably opens the switch S1And thereby disable the current source I during steady state operation of the power supply1。
In one embodiment, VDCTo 440 volts during start-up. In this example, RAMay be 6.0 megaohms, and the current source I1May be 10 microamperes; in this case, for VDCThe increase in (c) is 60 volts (6.0M Ω X10uA ═ 60 volts). Obviously, V may be selectedDCDifferent levels of (c). For example, R may be selectedAAnd I1Different values of (a). As anotherIn a specific example, RACan be set to 20M omega so that V is pairedDCAn increase of 200 volts (20.0M Ω X10uA — 200 volts); in this case, VDCMay be 580 volts (380 volts +200 volts-580 volts).
The comparator PIN determines whether the
When the output of the comparator PIN is a logic high voltage (heavy load), the reference voltage coupled to the error amplifier GMv is 2.5 volts, which results in an output voltage VDCIs regulated at about 380 volts DC. When the output of the comparator PIN is a logic low voltage (light load), the reference voltage coupled to the error amplifier GMv is preferably 2.25 volts, which results in an output voltage VDCIs regulated at about 342 volts DC. Thus, depending on the load, V regulated by the
The
The output of the
The output of amplifier GMi is coupled to compensation circuit 118. The signal IEAO is formed at the output of the amplifier GMi. The signal IEAO represents the error signal VEAO and the input voltage and current to the PFC stage. The signal IEAO is coupled to a first input of the comparator PFCcomp. The output of the
The output of the comparator PFCcomp is coupled to a driver/logic block 124 comprising driver and logic circuit elements for forming a PFC switching signal PFCOUT. Generating a PFC switching signal to regulate a PFC output voltage V according to Pulse Width Modulation (PWM)DC. It is apparent that the PFC function and control of the switching in the
Signal IAC is coupled to a first input of comparator acomp, while a reference voltage of 0.5 volts is coupled to a second input of comparator acomp. The comparator Accomp generates at its output a signal ACOFF indicating whether the input voltage falls below a minimum threshold. Logic 126 combines signal ACOFF with the signal at the output of comparator PIN to form signal R light load ("remember light load"). Signal R light load is a logic signal that indicates the state of signal IAC when signal IAC is above its lowest threshold and saves its state whenever signal IAC falls below its lowest threshold as detected by comparator acomp. In other words, logic 126 remembers (by keeping signal R in a light-loaded state) whether power converter 100 is in a light-loaded state or a heavy-loaded state when the AC input signal is lost.
The light load of signal R is used to adjust the level of the threshold voltage applied to the power gate comparator PGcomp. More specifically, a first input of comparator PGcomp is coupled to receive feedback signal VFB. The second input of comparator PGcomp is coupled to receive a first reference voltage of 2.3 volts and the third input is coupled to receive a second reference voltage. The level of the second reference voltage changes according to the level of the light load of the signal R. More specifically, when the light load of R indicates that the power converter 100 is in a heavy load state at the time of loss of the AC input signal, the reference voltage PGTHL is coupled to the third input of the comparator; also, when R light load indicates that the power converter 100 is in a light load condition when the AC input signal is lost, the reference voltage PGTHL-150mV is coupled to the third input of the comparator. The level of PGTHL may be set to 2.0 volts such that the second reference voltage is 2.0 or 1.85 volts according to the level of R light load.
The output of comparator PGcomp is coupled to DC-to-DC converter 104 (fig. 3) to selectively disable switching in DC-to-DC converter 104 via signal PGB (also shown in fig. 3). More specifically, the level of VFB is low and begins to rise just as the PFC stage starts. When the level of VFB is below 2.3 volts, the level of PGB is a logic high voltage, which disables switching in the DC-to-DC converter. Once the level of VFB exceeds the level of the first reference voltage (e.g., 2.3 volts), this causes the level of PGB to change to a logic low voltage, which enables switching in the DC-to-DC converter. Then, for the level of PGB to change to the logic high voltage again, the level of VFB needs to fall below the level of the second reference voltage. The level of the second reference voltage may be equal to 2.0 volts (PGTHL) or 1.85 volts (PGTHL-150Mv), depending on the level of the R light load.
Thus, switching in a DC-to-DC converter is disabled under different conditions depending on the state of the load at the time of loss of line voltage. More specifically, when the power converter 100 is operating in a heavy load state, the level of VFB is regulated to 2.5 volts, and the second reference voltage at the comparator PGcomp is 2.0 volts. If the AC line voltage is later lost, the level of VFB will begin to drop; in this case, it would need to drop from 2.5 volts to 2.0 volts before the output of comparator PGcomp causes signal PGB to disable switching in the DC-to-DC converter. However, when the power converter 100 is operating in a light load condition, the level of VFB is regulated to 2.25 volts, and the second reference voltage at the comparator PGcomp may be 1.85 volts. If the AC line voltage is later lost, the level of VFB will begin to drop; in this case, it would need to drop from 2.25 volts to 1.85 volts before the output of comparator PGcomp causes signal PGB to disable switching in the DC-to-DC converter. In this way, the holding time of the power loss in the heavy load state is controlled differently from the holding time of the power loss in the light load state. Because the hold times are controlled differently, differences in the manner in which the power supply operates under light or heavy loads can be compensated for so that the hold times have the desired duration. The disabling of the switching may be performed such that the hold time is approximately the same for light and heavy loads. This is because the time required for the level of VFB to drop from 2.5 volts to 2.0 volts under heavy load conditions is expected to be approximately the same as the time required for the level of VFB to drop from 2.25 volts to 1.85 volts under light load conditions. Alternatively, the disabling of the switching may be performed such that the hold times are different for light and heavy loads.
Fig. 4 (including fig. 4A, 4B, 4C, and 4D) shows a detailed schematic diagram of a PFC converter and a PFC controller according to an embodiment of the present invention. Fig. 4 shows a circuit that can be used to generate the signal BF as described above in connection with fig. 3. When the switching power supply is started, as shown in FIG. 4, by using the current source I2Capacitor C15Charges to generate the soft start signal ISOFT. More specifically, switch S2And S3Initially closed. When the reference voltage Vref rises to a predetermined level, the switch S2And (5) disconnecting. When the AC input voltage is detected, the switch S3And (5) disconnecting. When the switch S2And S3At the time of disconnection, at the capacitor C15The voltage across the terminals rises slowly. Albeit at C15The voltage at both ends rises, but switch S1Kept closed by a comparator DISBF which outputs V from PFCDCTo its higher initial level for start-up (e.g., 440 volts DC). When in the capacitor C15When the voltage across the terminals rises to 7.5 volts, the comparator DISBF turns off the switch S1Which isOutputs the PFC to VDCTo its lower steady state level (e.g., 380 volts DC). The comparator DISBF preferably has a hysteresis in order to prevent oscillations in the signal BF.
A first "ultra light load" detector/
A second "ultra light load" detector/
Further, when the switching is stopped in the second power saving mode of operation, the
The second power saving mode of operation is preferably entered when the level of VEAO falls below a second threshold, which is lower than the first threshold. When the level of VEAO falls below the second threshold, the switching stops until the level of VEAO rises above the second threshold. Thus, when the level of VEAO rises above and falls below the second threshold, the switching is performed in bursts.
Also shown in fig. 4 is an
Fig. 5 shows a schematic diagram of a
An energy storage element is coupled to the intermediate node. Specifically, as shown in fig. 5, the inductor LrIs coupled to the intermediate node. Inductor LrIs coupled to the capacitor CrThe first terminal of (1). Energy storage element LrAnd CrForming a series resonant tank. The resonant tank is charged with energy by raising and lowering the voltage VIN at the intermediate node. Capacitor CrIs coupled to the transformer T1A first terminal of the primary winding. Transformer T1Is coupled to the ground node. Transformer T1Is coupled to a transistor switch Q3The first terminal of (1). Transformer T1Is coupled to the transistor switch Q4The first terminal of (1). Transistor switch Q3And transistor switch Q4Is coupled to the ground node. Each transistor switch Q3And Q4Is coupled to the
Transformer T1Is coupled to the capacitor COThe first terminal of (1). Capacitor COIs coupled to the ground node. Output voltage VOIn the capacitor COTwo ends are formed. The load 154 may be coupled to the capacitor COTwo ends for receiving output voltage VO. Output voltage VOOr a voltage representative of the output voltage, is fed back to the
Regulating transistor switch Q1And Q2Will adjust the impedance of the resonant tank and thus the amount of power delivered to the load 154. More specifically, decreasing the switching frequency tends to increase the power delivered to the load 154. Increasing the switching frequency tends to decrease the power delivered to the load 154. By monitoring the output voltage V via the feedback path 156OThe
When the electric energy passes through the transformer T1Passes through the transformer T when delivered to the load 1541The current of the secondary winding of (a) alternates in direction. Transistor switch Q3And Q4Synchronous rectification is performed. This causes the transistor to switch Q via the controller 1543And Q4Switched on and off at appropriate times so that current flows through each switch Q in only one direction3And Q4To be implemented. Typically, when a transistor switches Q4When disconnected, the transistor switch Q3And (4) switching on. Similarly, when the transistor switches Q3When disconnected, the transistor switch Q4And (4) switching on. Synchronous rectification ensures that power is delivered to the load 154 and prevents reverse current flow, which may be reflected to the resonant tank. Such reverse currents can lead to unwanted oscillations, intractable behavior and equipment failure.
Coupled to the primary PFC inductor L as described hereinAInductor L of1For generating auxiliary electrical energy during start-up (see, e.g., fig. 2 and 4). This power is used to operate the control circuitry of the power supply, such as the DC to
FIG. 6 illustrates a voltage regulator of a power supply controller according to one embodiment of the invention. As shown in fig. 6, the DC-to-
During start-up, power for the
In an example, the output 131 of the DC-to-DC converter 104 is regulated at 12.0 volts or higher, while the
Fig. 7 (including fig. 7A, 7B, 7C, and 7D) shows a detailed schematic diagram of a DC-to-DC converter and a DC-to-DC converter controller according to an embodiment of the invention. Fig. 8 (including fig. 8A, 8B, 8C, and 8D) illustrates a DC to DC converter transformer circuit according to an embodiment of the invention. Fig. 7 and 8 illustrate the
Referring to fig. 8, the output V from the PFCDCThrough the switch Q of the DC-to-DC converter stage 1041And Q2Is converted by the DC-to-DC converter stage 104 into a regulated output VO. The resulting current in the transformer T1 generates the
The power supply is activated by applying an AC source to an AC input of the power supply. Power is then drawn from the bridge rectifier 110 (fig. 2 and 4) of the
Fig. 7 and 8 additionally show details of the power saving mode of operation of the DC-to-DC converter stage 104. More specifically, fig. 7 shows that a signal IPLIMIT representing the output current of the DC-to-DC converter stage is coupled to a detector/comparator 160 to detect a light load condition. When the level of IPLIMIT falls below a threshold (e.g., 50mV), this indicates a light load condition. This threshold value may preferably be selected to 75mV, 100mV or some other value, for example by laser trimming. Comparator 160 preferably functions with hysteresis to avoid repeatedly enabling and disabling the power saving mode of operation when the level of IPLIMIT fluctuates slightly. Thus, when the level of IPLIMIT rises above the threshold by a hysteresis margin, this indicates that the DC-to-DC converter stage is no longer in a light load condition. The output of comparator 160 is coupled to a kick mode logic 162 to enable a "burst" or "kick" mode of operation in such light load conditions.
Furthermore, the comparator 164 preferably compares a feedback signal VFB, which is representative of the output voltage of the DC-to-DC converter stage, with a threshold (e.g., 2.495 volts) with hysteresis to produce a signal BURST at its output. Thus, when the "shoot through" mode is enabled by comparator 160 and feedback signal VFB falls below a threshold (e.g., 2.495 volts), switching of the DC-to-DC converter stage is enabled by comparator 164 and shoot through mode logic 162. The signal BURST generated by the comparator 164 is active and switching is enabled. When the feedback signal VFB rises above the threshold by a hysteresis margin (e.g., 0.01 volts), the signal BURST is inactive and switching is disabled. When the level of VFB falls below the threshold (and signal BURST is activated) and rises above the threshold (and signal BURST is deactivated), the switching is thus performed in BURSTs.
Furthermore, frequency modulation is preferably used to regulate the output voltage when the DC-to-DC converter is not in a shoot through mode. When the DC-to-DC converter is in the shoot mode, the switching frequency is preferably kept constant during the switching burst. The output voltage is therefore regulated by varying the duration of the switching BURSTs (signal BURST is active) compared to the period between BURSTs when the switching is stopped (signal BURST is inactive).
The constant switching frequency used during a switching burst is preferably user selectable when the DC-to-DC converter stage is in a jerk mode. This is accomplished by coupling a reference voltage to the shoot through input of the DC-to-
Also shown in fig. 7 is a comparator 166 that compares the level of IPLIMIT with a reference voltage (e.g., 5.5 volts) for overcurrent protection. Specifically, when the level of IPLIMIT is above this threshold, this indicates an overcurrent condition. In this case, comparator 166 activates a "fault" signal. The fault signal may be communicated to the
As described above, when IPLIMIT falls below a low threshold (e.g., 50mV), this indicates a light load condition, and the DC-to-
The output current of a DC-to-DC converter stage tends to be unstable. Therefore, it is desirable to smooth or average the level of the output current for sensing the light load state. It is also desirable to sense the instantaneous output current for detecting an overcurrent condition.
Fig. 8 shows a load sense and peak
The
Capacitor C45 provides a first pole for frequency compensation of signal IPLIMIT. The
FIG. 9 illustrates a method for activating M according to an embodiment of the present inventionUVLOSchematic diagram of the circuit of (1). This circuitry may be included in PFC controller 108 (fig. 4). As shown in fig. 9,
When VCC is below 10.0 volts, the UVLO signal prevents switching in the PFC stage until VCC rises to 15.5 volts. Thus, if VCC falls at 15.5 volts, MUVLOIs activated, which tends to increase VCC and thereby helps prevent VCC from falling below 10.0 volts.
As described herein, switching in the PFC stage generates a DC auxiliary supply voltage Vaux1 that may be used by the
The foregoing detailed description of the invention is provided for the purpose of illustration and is not intended to be exhaustive or to limit the invention to the disclosed embodiments. Accordingly, the scope of the invention is defined by the appended claims.
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