阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 河野洋志 大桥辉之 古川大 于 2019-07-10 设计创作，主要内容包括：实施方式提供能够降低导通电阻的半导体装置。实施方式的半导体装置,具备：第一电极、第二电极、碳化硅层、和与第二碳化硅区域对置的栅极电极。碳化硅层具有：第1导电型的第一碳化硅区域,设在第一电极与第二电极之间,具有第一面和第二面；第一碳化硅区域与第一面之间的第2导电型的第二碳化硅区域；第一碳化硅区域与第一面之间的、与第二碳化硅区域分离的第2导电型的第三碳化硅区域；第二碳化硅区域与第一面之间的、与第一电极相接的第1导电型的第四碳化硅区域、第二碳化硅区域与第三碳化硅区域之间的、第1导电型杂质浓度比第一碳化硅区域高的第1导电型的第五碳化硅区域；以及第五碳化硅区域与第一面之间的、与第一电极相接的第2导电型的第六碳化硅区域。(Embodiments provide a semiconductor device capable of reducing on-resistance. The semiconductor device of the embodiment includes: a first electrode, a second electrode, a silicon carbide layer, and a gate electrode facing the second silicon carbide region. The silicon carbide layer has: a first silicon carbide region of the 1 st conductivity type provided between the first electrode and the second electrode, and having a first surface and a second surface; a second silicon carbide region of conductivity type 2 between the first silicon carbide region and the first face; a third silicon carbide region of conductivity type 2 between the first silicon carbide region and the first face and separated from the second silicon carbide region; a fourth silicon carbide region of the 1 st conductivity type between the second silicon carbide region and the first surface and in contact with the first electrode, and a fifth silicon carbide region of the 1 st conductivity type having a higher impurity concentration of the 1 st conductivity type than the first silicon carbide region between the second silicon carbide region and the third silicon carbide region; and a sixth silicon carbide region of the 2 nd conductivity type in contact with the first electrode between the fifth silicon carbide region and the first surface.)

1. A semiconductor device, comprising:

a first electrode;

a second electrode; and

a silicon carbide layer provided between the first electrode and the second electrode, and having a first surface on the first electrode side and a second surface on the second electrode side;

the silicon carbide layer includes:

a first silicon carbide region of a 1 st conductivity type;

a second silicon carbide region of a 2 nd conductivity type provided between the first silicon carbide region and the first surface;

a third silicon carbide region of the 2 nd conductivity type provided between the first silicon carbide region and the first surface and separated from the second silicon carbide region;

a fourth silicon carbide region of the 1 st conductivity type provided between the second silicon carbide region and the first surface and in contact with the first electrode;

a fifth silicon carbide region of the 1 st conductivity type provided between the second silicon carbide region and the third silicon carbide region, the impurity concentration of the 1 st conductivity type being higher than that of the first silicon carbide region; and

a sixth silicon carbide region of the 2 nd conductivity type provided between the fifth silicon carbide region and the first surface and in contact with the first electrode,

the semiconductor device further includes:

a gate electrode facing the second silicon carbide region; and

and a gate insulating layer provided between the gate electrode and the second silicon carbide region.

2. The semiconductor device according to claim 1,

the silicon carbide layer has a seventh silicon carbide region of the 2 nd conductivity type,

and a seventh silicon carbide region provided between the fifth silicon carbide region and the first surface and between the sixth silicon carbide region and the second silicon carbide region, in contact with the first electrode, and having a lower impurity concentration of the 2 nd conductivity type than the sixth silicon carbide region.

3. The semiconductor device according to claim 1,

the silicon carbide layer has an eighth silicon carbide region of the 1 st conductivity type,

and an eighth silicon carbide region provided between the fifth silicon carbide region and the first surface and between the sixth silicon carbide region and the second silicon carbide region, and in contact with the first electrode.

4. The semiconductor device according to any one of claims 1 to 3,

a first portion of the first electrode in contact with the fourth silicon carbide region and a second portion of the first electrode in contact with the sixth silicon carbide region are made of the same material.

5. The semiconductor device according to any one of claims 1 to 3,

the sixth silicon carbide region has a higher impurity concentration of the second conductivity type 2 than a portion of the second silicon carbide region that faces the gate electrode.

6. The semiconductor device according to any one of claims 1 to 3,

the boundary between the fifth silicon carbide region and the sixth silicon carbide region is spaced apart from the first surface by a distance of 50nm to 200 nm.

7. The semiconductor device according to any one of claims 1 to 3,

the silicon carbide layer has a ninth silicon carbide region of the 1 st conductivity type,

the ninth silicon carbide region is provided between the fifth silicon carbide region and the second silicon carbide region, and the impurity concentration of the 1 st conductivity type impurity is higher than that of the fifth silicon carbide region.

8. The semiconductor device according to any one of claims 1 to 3,

the silicon carbide layer has a tenth silicon carbide region of the 2 nd conductivity type,

and a tenth silicon carbide region provided between the second silicon carbide region and the first surface, in contact with the first electrode, and having a higher impurity concentration of the 2 nd conductivity type than the second silicon carbide region.

9. The semiconductor device according to any one of claims 1 to 3,

a part of the second silicon carbide region is in contact with the first surface, and the part is opposed to the gate electrode.

Technical Field

Embodiments of the present invention relate to a semiconductor device.

Background

Silicon carbide is expected as a material for next-generation semiconductor devices. Silicon carbide has good physical properties such as a band gap of 3 times, a breakdown field strength of about 10 times, and a thermal conductivity of about 3 times as compared with silicon. By utilizing this characteristic, for example, a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) which has a high withstand voltage, a low loss, and can operate at a high temperature can be realized.

A vertical MOSFET using silicon carbide includes a pn junction diode (body diode) as a built-in diode. For example, a MOSFET is used as a switching element connected to an inductive load. In this case, when the MOSFET is turned off, the reflux current can also flow by using the body diode.

However, when a return current flows through a body diode that performs a bipolar operation, a stacking fault grows in the silicon carbide layer due to the recombination energy of carriers, and there is a problem that the on-resistance of the MOSFET increases. The increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

For example, by providing a Schottky Barrier Diode (SBD) that operates in a unipolar mode as an internal Diode in a MOSFET, stacking defects in a silicon carbide layer can be suppressed. When the SBD is provided in the MOSFET, the formation of the SBD hinders the miniaturization of the MOSFET, and the on-resistance of the MOSFET may increase.

Disclosure of Invention

The invention provides a semiconductor device capable of reducing on-resistance.

Drawings

Fig. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment.

Fig. 2 is a schematic plan view of the semiconductor device of the first embodiment.

Fig. 3 is an equivalent circuit diagram of the semiconductor device of the first embodiment.

Fig. 4 is an explanatory diagram of the operation and effect of the semiconductor device of the first embodiment.

Fig. 5 (a) and (b) are explanatory views of the operation and effect of the semiconductor device of the first embodiment.

Fig. 6 is an explanatory view of the operation and effect of the semiconductor device of the first embodiment.

Fig. 7 is a schematic cross-sectional view of a semiconductor device of a second embodiment.

Fig. 8 is a schematic cross-sectional view of a semiconductor device of a third embodiment.

Fig. 9 is a schematic cross-sectional view of a semiconductor device according to a fourth embodiment.

Fig. 10 is a schematic sectional view of a semiconductor device according to a fifth embodiment.

The semiconductor device of the embodiment includes: a first electrode; a second electrode; a silicon carbide layer provided between the first electrode and the second electrode, and having a first surface on the first electrode side and a second surface on the second electrode side; a gate electrode facing a second silicon carbide region described later; and a gate insulating layer provided between the gate electrode and a second silicon carbide region described later. The silicon carbide layer includes: a first silicon carbide region of a 1 st conductivity type; a second silicon carbide region of a 2 nd conductivity type provided between the first silicon carbide region and the first surface; a third silicon carbide region of the 2 nd conductivity type provided between the first silicon carbide region and the first surface and separated from the second silicon carbide region; a fourth silicon carbide region of the 1 st conductivity type provided between the second silicon carbide region and the first surface and in contact with the first electrode; a fifth silicon carbide region of the 1 st conductivity type provided between the second silicon carbide region and the third silicon carbide region, the impurity concentration of the 1 st conductivity type being higher than that of the first silicon carbide region; and a sixth silicon carbide region of the 2 nd conductivity type provided between the fifth silicon carbide region and the first surface and in contact with the first electrode.