阅读说明：本技术 时钟展频方法和时钟展频电路 (Clock frequency spreading method and clock frequency spreading circuit ) 是由 湛伟 马淑彬 夏明刚 罗春林 丛伟林 于 2020-05-12 设计创作，主要内容包括：时钟展频方法和时钟展频电路,涉及电子技术。本发明的时钟展频电路包括：N相位时钟产生电路；相位偏移叠加电路,以N相位时钟产生电路的输出信号作为输入信号,其控制端与相位选择控制电路连接,用于对选定的两路输入信号进行相位偏移叠加处理；相位偏移叠加电路具有输出端和逻辑运算模块,所述逻辑运算模块用于对两个参考时钟进行逻辑运算以获得输出时钟；相位选择控制电路,用于选择N相位时钟产生电路的输出信号作为相位偏移叠加电路的偏移叠加信号源。本发明的电路相对传统的基于PLL产生展频时钟的电路更简单,可以完全独立于PLL模块。(A clock spread spectrum method and a clock spread spectrum circuit relate to the electronic technology. The clock spread spectrum circuit of the present invention includes: an N-phase clock generating circuit; the phase deviation superposition circuit takes the output signal of the N-phase clock generation circuit as an input signal, and the control end of the phase deviation superposition circuit is connected with the phase selection control circuit and is used for carrying out phase deviation superposition processing on the two selected paths of input signals; the phase offset superposition circuit is provided with an output end and a logic operation module, wherein the logic operation module is used for carrying out logic operation on two reference clocks to obtain an output clock; and the phase selection control circuit is used for selecting the output signal of the N-phase clock generation circuit as an offset superposition signal source of the phase offset superposition circuit. Compared with the traditional circuit for generating the spread spectrum clock based on the PLL, the circuit of the invention is simpler and can be completely independent of the PLL module.)

1. A method of clock spreading, comprising the steps of:

1) generating N paths of offset clock signals P (1) -P (N) with equal phase difference by performing phase offset on an input clock signal, wherein the phase difference between a k path of offset clock signal P (k) and a k +1 path of offset clock signal P (k +1) is a preset value delta P, and the phase difference between the N path of offset clock signal and a 1 path of offset clock signal is also a preset value delta P, k is 1,2,. N-1; n is an integer greater than 3;

2) setting a step value a, and selecting a path of offset clock signal P (x) as a starting signal, wherein the sequence number x is any positive integer not greater than N;

3) generating an output clock at a first frequency, comprising the sub-steps of:

(3.1) performing a logic operation on the offset clock signal P (x) and the offset clock signal P (x + a) to obtain an output clock, so that a specific transition edge of the offset clock signal P (x) corresponds to a signal edge of a current pulse of the output clock;

(3.2) taking x + a as the x value in the next logical operation, and then returning to the step (3.1);

4) generating an output clock at a second frequency, comprising the sub-steps of:

(4.1) changing the value of the step value a;

(4.2) performing a logic operation on the offset clock signal P (x) and the offset clock signal P (x + a) to obtain an output clock, so that a specific transition edge of the offset clock signal P (x) corresponds to a signal edge of a current pulse of the output clock;

(4.3) taking x + a as the x value in the next logical operation, and then returning to the step (4.2); in each step, x and x + a are cycled by N as counting period.

2. The clock spreading method according to claim 1, further comprising the step 5): and adjusting the duty ratio of the output clock signal.

3. A clock spreading circuit using the clock spreading method of claim 1, comprising:

the N phase clock generating circuit is used for providing N paths of output signals to the phase offset superposition circuit, wherein the Nth path of output signals are clock signals based on N-1 phase offset quantities of the input clock, and N is an integer larger than 3;

the phase deviation superposition circuit takes the output signal of the N-phase clock generation circuit as an input signal, and the control end of the phase deviation superposition circuit is connected with the phase selection control circuit and is used for carrying out phase deviation superposition processing on the two selected paths of input signals; the phase offset superposition circuit is provided with an output end and a logic operation module, wherein the logic operation module is used for carrying out logic operation on two reference clocks to obtain an output clock;

and the phase selection control circuit is used for selecting the output signal of the N-phase clock generation circuit as an offset superposition signal source of the phase offset superposition circuit.

4. The clock spreading circuit of claim 3 further comprising a duty cycle adjustment circuit having an input coupled to an output of the phase shift superposition circuit.

Technical Field

The present invention relates to electronic technology.

Background

The Spread Spectrum Clock (SSC) is mainly used to reduce Electromagnetic interference (EMI).

The energy of the fixed frequency clock is concentrated at the fixed frequency point. The frequency of the spread spectrum clock varies periodically with time so that the electromagnetic radiation of the spread spectrum clock is spread over the frequency band of the spread spectrum. Thus, the electromagnetic radiation of a spread spectrum clock is greatly reduced compared to a fixed frequency clock.

Electromagnetic radiation can cause interference to other electronic devices, affecting normal communications and functions. For some electronic products, especially consumer electronic products, industry organizations such as Federal Communications Commission (FCC) and european union have established standards for electromagnetic radiation, and limit the amount of electromagnetic radiation that can be generated by electronic systems. For the electronic products which do not reach the standard, corresponding authentication cannot be obtained, and the electronic products cannot be sold in the target market.

The "spread spectrum phase-locked loop control circuit" of chinese patent CN203014779U discloses a first prior art, and the circuit mainly comprises the following components as shown in fig. 1. The traditional PLL without the function of generating a spread spectrum clock consists of a phase comparator, a charge pump, a filter, a voltage control oscillation circuit and a frequency divider.

The above-mentioned patents, as well as other currently commonly used spread spectrum generating circuits, are based on a conventional phase-locked loop (PLL) circuit structure. The frequency divider of the phase-locked loop is controlled by using a triangular wave generator and a modulator, so that the frequency dividing ratio is changed along with the time period, and the purpose of generating a spread spectrum clock is achieved.

Disclosure of Invention

The invention provides a spread spectrum clock circuit and a clock spread spectrum method, which are completely independent of a PLL module and have simple structures.

The technical scheme adopted by the invention for solving the technical problem is that the clock frequency spreading method is characterized by comprising the following steps:

1) generating N paths of offset clock signals P (1) -P (N) with equal phase difference by performing phase offset on an input clock signal, wherein the phase difference between a k path of offset clock signal P (k) and a k +1 path of offset clock signal P (k +1) is a preset value delta P, and the phase difference between the N path of offset clock signal and a 1 path of offset clock signal is also a preset value delta P, k is 1,2,. N-1; n is an integer greater than 3;

2) setting a step value a, and selecting a path of offset clock signal P (x) as a starting signal, wherein the sequence number x is any positive integer not greater than N;

3) generating an output clock at a first frequency, comprising the sub-steps of:

(3.1) performing a logic operation on the offset clock signal P (x) and the offset clock signal P (x + a) to obtain an output clock, so that a specific transition edge of the offset clock signal P (x) corresponds to a signal edge of a current pulse of the output clock;

(3.2) taking x + a as the x value in the next logical operation, and then returning to the step (3.1);

4) generating an output clock at a second frequency, comprising the sub-steps of:

(4.1) changing the value of the step value a;

(4.2) performing a logic operation on the offset clock signal P (x) and the offset clock signal P (x + a) to obtain an output clock, so that a specific transition edge of the offset clock signal P (x) corresponds to a signal edge of a current pulse of the output clock;

(4.3) taking x + a as the x value in the next logical operation, and then returning to the step (4.2); in each step, x and x + a are cycled by N as counting period. (x% N as the value of x in the next logical operation if x is greater than N; x + a)% N as the value of x in the next logical operation if x + a is greater than N;)

Further comprising step 5): and adjusting the duty ratio of the output clock signal.

The invention also provides a clock spread spectrum circuit adopting the clock spread spectrum method, which is characterized by comprising the following steps:

the N phase clock generating circuit is used for providing N paths of output signals to the phase offset superposition circuit, wherein the Nth path of output signals are clock signals based on N-1 phase offset quantities of the input clock, and N is an integer larger than 3;

the phase deviation superposition circuit takes the output signal of the N-phase clock generation circuit as an input signal, and the control end of the phase deviation superposition circuit is connected with the phase selection control circuit and is used for carrying out phase deviation superposition processing on the two selected paths of input signals; the phase offset superposition circuit is provided with an output end and a logic operation module, wherein the logic operation module is used for carrying out logic operation on two reference clocks to obtain an output clock;

and the phase selection control circuit is used for selecting the output signal of the N-phase clock generation circuit as an offset superposition signal source of the phase offset superposition circuit.

The input end of the duty ratio adjusting circuit is connected with the output end of the phase deviation superposition circuit.

The specific transition edge is one of a rising edge or a falling edge, that is, only the rising edge is taken as the specific transition edge, or only the falling edge is taken as the specific transition edge.

The signal edge is one of a rising edge or a falling edge, that is, only the rising edge is the signal edge, or only the falling edge is the signal edge.

The circuit of the invention is simpler than the traditional circuit which generates a spread spectrum clock based on PLL.

The circuit of the invention can be completely independent of the PLL module. The input clock of the circuit can be provided by a PLL module integrated in the chip, other clock generation modules integrated in the chip, an off-chip crystal oscillator, an off-chip clock chip, and the like. Therefore, the circuit has better portability. The circuit of the invention does not need to change the PLL circuit, thus being suitable for integrating with Intellectual Property (IP) cores such as purchased PLL and the like.

Drawings

Fig. 1 is a schematic diagram of a comparison document.

Fig. 2 is a circuit diagram of the present invention.

FIG. 3 is a diagram illustrating a clock pulse mapping relationship according to the present invention.

Fig. 4 is a schematic diagram of the present invention for generating an output clock signal having a frequency f 1.

FIG. 5 is a schematic diagram of the present invention for cycle selection of equal phase difference offset clock signals.

FIG. 6 is a diagram illustrating the relationship between clock frequencies according to the present invention.

Detailed Description

See FIGS. 1-3.

A method of clock spreading, comprising the steps of:

1) generating N paths of offset clock signals P (1) -P (N) with equal phase difference by performing phase offset on an input clock signal, wherein the phase difference between a k path of offset clock signal P (k) and a k +1 path of offset clock signal P (k +1) is a preset value delta P, and the phase difference between the N path of offset clock signal and a 1 path of offset clock signal is also a preset value delta P, k is 1,2,. N-1; n is an integer greater than 3;

2) setting a step value a, and selecting a path of offset clock signal P (x) as a starting signal, wherein the sequence number x is any positive integer not greater than N;

3) generating an output clock at a first frequency, comprising the sub-steps of:

(3.1) performing a logic operation on the offset clock signal P (x) and the offset clock signal P (x + a) to obtain an output clock, so that a specific transition edge of the offset clock signal P (x) corresponds to a signal edge of a current pulse of the output clock;

(3.2) taking x + a as the x value in the next logical operation, and then returning to the step (3.1);

4) generating an output clock at a second frequency, comprising the sub-steps of:

(4.1) changing the value of the step value a;

(4.2) performing a logic operation on the offset clock signal P (x) and the offset clock signal P (x + a) to obtain an output clock, so that a specific transition edge of the offset clock signal P (x) corresponds to a signal edge of a current pulse of the output clock;

(4.3) taking x + a as the x value in the next logical operation, and then returning to the step (4.2);

in each step, x and x + a are cycled by taking N as a counting period, that is, if x is larger than N, x% N is taken as the value of x in the next logic operation; if x + a is greater than N, (x + a)% N is used as the value of x in the next logical operation. x% N represents the remainder of x divided by N,% represents the remainder.

Further comprising step 5): and adjusting the duty ratio of the output clock signal.

The invention also provides a clock spread spectrum circuit adopting the clock spread spectrum method, which is characterized by comprising the following steps:

the N phase clock generating circuit is used for providing N paths of output signals to the phase offset superposition circuit, wherein the Nth path of output signals are clock signals based on N-1 phase offset quantities of the input clock, and N is an integer larger than 3;

the phase deviation superposition circuit takes the output signal of the N-phase clock generation circuit as an input signal, and the control end of the phase deviation superposition circuit is connected with the phase selection control circuit and is used for carrying out phase deviation superposition processing on the two selected paths of input signals; the phase offset superposition circuit is provided with an output end and a logic operation module, wherein the logic operation module is used for carrying out logic operation on two reference clocks to obtain an output clock;

and the phase selection control circuit is used for selecting the output signal of the N-phase clock generation circuit as an offset superposition signal source of the phase offset superposition circuit.

The input end of the duty ratio adjusting circuit is connected with the output end of the phase deviation superposition circuit.

The specific transition edge is one of a rising edge or a falling edge, that is, only the rising edge is taken as the specific transition edge, or only the falling edge is taken as the specific transition edge.

The specific transition edge is one of a rising edge or a falling edge, that is, only the rising edge is taken as the specific transition edge, or only the falling edge is taken as the specific transition edge.