阅读说明：本技术 一种用于电压比较型高速模数转换器的温度计码解码电路 (Thermometer code decoding circuit for voltage comparison type high-speed analog-to-digital converter ) 是由 王春娥 周磊 白雪飞 于 2020-05-28 设计创作，主要内容包括：本发明公开了一种用于电压比较型高速模数转换器的温度计码解码电路,主要包括气泡消除电路和基于只读存储器ROM结构的位置码解码电路。电压比较网络的寄存器组输出n位温度计码Q[n-1..0]；温度计码解码电路的气泡消除电路的输入为n位温度计码Q[n-1..0],输出为n位的T[n-1..0]；温度计解码电路的位置码解码电路的输入为n位的T[n-1..0],输出为k位采样值S[k-1..0]。(The invention discloses a thermometer code decoding circuit for a voltage comparison type high-speed analog-to-digital converter, which mainly comprises a bubble elimination circuit and a position code decoding circuit based on a Read Only Memory (ROM) structure. The register group of the voltage comparison network outputs n-bit thermometer codes Q [ n-1..0 ]; the input of a bubble eliminating circuit of the thermometer code decoding circuit is n thermometer codes Q [ n-1..0], and the output is n T [ n-1..0 ]; the input of the position code decoding circuit of the thermometer decoding circuit is T [ n-1..0] of n bits, and the output is k-bit sampling value S [ k-1..0 ].)

1. A thermometer code decoding circuit for a voltage comparison type high-speed analog-to-digital converter, the voltage comparison type high-speed analog-to-digital converter comprises a voltage comparison network, and the thermometer code decoding circuit is characterized by comprising a bubble elimination circuit and a position code decoding circuit, wherein a register group of the voltage comparison network outputs an n-bit thermometer code Q [ n-1..0]](ii) a The input of the bubble elimination circuit is an n-bit thermometer code Q [ n-1..0]]And the output is T [ n-1..0] of n bits](ii) a The input of the position code decoding circuit is T [ n-1..0] of n bits]The output is k-bit sampling value S [ k-1..0]]，2^k-1≤n≤2^k；

The relation between the input and the output of the bubble elimination circuit satisfies:

the relationship between the input and the output of the position code decoding circuit satisfies:

S[k-1..0]＝Bin[x]，x＝max{i|_T[i]＝1}，0≤i＜n；

wherein Bin [ x ]]Representing a k-bit binary number corresponding to the decimal number x; max { i |_T[i]＝1Means solving for T [ n-1..0]]The position value of 1 for the first time from the highest bit to the lowest bit.

2. A thermometer code decoding circuit for a voltage comparison type high speed analog to digital converter as claimed in claim 1, the voltage comparison network is characterized by comprising n resistors R0-Rn-1, n operational amplifiers O0-On-1 and n D triggers Q0-Qn-1, wherein a reference voltage Vref + and a negative reference voltage Vref-are respectively loaded at two ends of a circuit formed by connecting the resistors R0-Rn-1 in series according to the numbering sequence, the positive phase input ends of the operational amplifiers O0-On-1 are respectively connected with a conversion signal Vin, the negative phase input end of the operational amplifier On-1 is connected with the negative reference voltage Vref-, the negative phase input end of the operational amplifier Ot is connected with a common end of a resistor Rt and a resistor Rt +1, and t belongs to {0, 1, n-2}, and the output ends of the operational amplifiers O0-On-1 are respectively connected with the D triggers Q0-Qn-1 input ends.

3. The thermometer code decoding circuit for a voltage comparison type high speed analog to digital converter as claimed in claim 2, wherein the bubble eliminating circuit is constituted by n exclusive ors X0 to Xn-1, two input terminals of the exclusive or Xn-1 are respectively connected to the ground and the output terminal of the D flip-flop Qn-1, two input terminals of the exclusive or Xj are respectively connected to the output terminal of the D flip-flop Qj and the output terminal of the D flip-flop Qj +1, and j ∈ {0, 1., n-2 }.

4. The thermometer code decoding circuit for a voltage comparison type high speed analog to digital converter as claimed in claim 1, wherein the position code decoding circuit comprises n memory cells and n normally closed switches, the ith switch SW_iBetween the ith memory cell and the (i-1) th memory cell bus; t [ i ]]Controlling the enable terminal of the ith memory cell and the ith switch SW_iWhen T [ i ]]When equal to 0, the ith switch SW_iClosing, and outputting a high-impedance state by the ith storage unit; when T [ i ]]When 1, the ith switch SW_iIs disconnected at T [ n-1.. i + 1]]In which there is no high level, i.e. the (i + 1) th switch SW_i+1To the (n-1) th switch SW_n-1All closed, the storage content Bin [ i ] of the ith storage unit]Output to S [ k-1..0] via the ith memory cell bus]。

Technical Field

The invention relates to a thermometer code decoding circuit for a voltage comparison type high-speed analog-to-digital converter, and belongs to the field of thermometer code decoder circuits.

Background

The voltage comparison type high-speed analog-to-digital converter is composed of a voltage comparison network and a thermometer code decoding circuit, wherein the thermometer code decoding circuit comprises a bubble elimination circuit and a position code decoding circuit. In a voltage comparison type high-speed analog-to-digital converter having only one output register group, theoretically, a signal V to be converted_inOutputting thermometer code Q [ n-1..0] in the form of '11110000' or '00001111' after inputting voltage comparison network](ii) a The thermometer code Q outputs One-Shot code T [ n-1 ] of the shape of 00010000 or 00001000 after passing through the bubble elimination circuit..0](ii) a The One-Shot code T can output binary position code D [ k-1..0] of 100 or 011 after being processed by the position code decoder]. In fact, as the sampling frequency increases, V_inThe spacing between active clock edges of the working clock clk from the output register set of the voltage comparison analog-to-digital converter becomes smaller and smaller. When the time interval is small enough to violate the time sequence constraints of the setup time and the hold time of the output trigger group of the voltage comparison type analog-to-digital converter, some triggers in the output trigger group of the voltage comparison type analog-to-digital converter can output wrong sampling data because of being in a metastable state. For example, theoretical output "011", actually "101"; theoretical output "100", actual output "110".

A two-stage register set is arranged in the pipelined voltage comparison type high-speed analog-to-digital converter, and besides the output register set, a one-stage register set is added at the output of the voltage comparison network. The metastable state phenomenon can occur at the output Q [ n-1..0] of the output register bank of the voltage comparator network]In (1). For example, Q [ n-1..0]]Theoretically, the output of '11110000' is actually output '11101000' or '11001000', even '11010100' and the like; theoretical output "00001111", actual output "00010111", and the like. The combinations of "1001", "10101" and "101" that affect consecutive "1" or consecutive "0" are referred to as output bubble phenomena caused by register metastability. In addition, the maximum delay t of the thermometer code decoding circuit between the output register group of the voltage comparator network and the output register group of the analog-to-digital converter_tmDetermines the maximum working frequency f of the voltage comparison type analog-to-digital converter_{clk_max}：

Therefore, the method for realizing the bubble elimination circuit and the position code decoding circuit with uniform structural distribution and short delay path is the key for reducing the maximum delay of the thermometer code decoding circuit and also the key for improving the maximum working frequency of the voltage comparison type analog-to-digital converter.

Disclosure of Invention

The invention aims to provide a thermometer code decoding circuit for a voltage comparison type high-speed analog-to-digital converter.

The invention adopts the following technical scheme for solving the technical problems:

a thermometer code decoding circuit for a voltage comparison type high-speed analog-to-digital converter includes a voltage comparison network. The thermometer code decoding circuit comprises a bubble eliminating circuit and a position code decoding circuit, wherein a register group of a voltage comparison network outputs an n-bit thermometer code Q [ n-1..0]](ii) a The input of the bubble elimination circuit is an n-bit thermometer code Q [ n-1..0]]And the output is T [ n-1..0] of n bits](ii) a The input of the position code decoding circuit is T [ n-1..0] of n bits]The output is k-bit sampling value S [ k-1..0]]，2^k-1≤n≤2^k；

The relation between the input and the output of the bubble elimination circuit satisfies:

the relationship between the input and the output of the position code decoding circuit satisfies:

S[k-1..0]＝Bin[x]，x＝max{i|_T[i]＝1}，0≤i＜n；

wherein Bin [ x ]]Representing a k-bit binary number corresponding to the decimal number x; max { i |_T[i]＝1Means solving for T [ n-1..0]]The position value of 1 for the first time from the highest bit to the lowest bit.

Furthermore, the voltage comparison network is composed of n resistors R0 to Rn-1, n operational amplifiers O0 to On-1 and n D flip-flops Q0 to Qn-1, a reference voltage Vref + and a negative reference voltage Vref-are respectively loaded at two ends of a circuit formed by connecting the resistors R0 to Rn-1 in series according to the numbering sequence, the positive phase input ends of the operational amplifiers O0 to On-1 are respectively connected with a signal Vin to be converted, the negative phase input end of the operational amplifier On-1 is connected with the negative reference voltage Vref-, the negative phase input end of the operational amplifier Ot is connected with a common end of the resistor Rt and the resistor Rt +1, t belongs to {0, 1, n-2}, and the output ends of the operational amplifiers O0 to On-1 are respectively connected with the D flip-flops Q0 to the D input ends of the Qn-1.

Furthermore, the bubble elimination circuit is composed of n exclusive ors X0 to Xn-1, two input ends of the exclusive or Xn-1 are respectively grounded and connected with an output end of the D trigger Qn-1, two input ends of the exclusive or Xj are respectively connected with an output end of the D trigger Qj and an output end of the D trigger Qj +1, and j belongs to {0, 1., n-2 }.

Further, the position code decoding circuit comprises n storage units and n normally closed switches, an ith switch SW_iBetween the ith memory cell and the (i-1) th memory cell bus; t [ i ]]Controlling the enable terminal of the ith memory cell and the ith switch SW_iWhen T [ i ]]When equal to 0, the ith switch SW_iClosing, and outputting a high-impedance state by the ith storage unit; when T [ i ]]When 1, the ith switch SW_iIs disconnected at T [ n-1.. i + 1]]In which there is no high level, i.e. the (i + 1) th switch SW_i+1To the (n-1) th switch SW_n-1All closed, the storage content Bin [ i ] of the ith storage unit]Output to S [ k-1..0] via the ith memory cell bus]。

Compared with the prior art, the invention adopting the technical scheme has the following technical effects:

1. the bubble problem in any type of thermometer code can be handled;

2. the path delay from Q [ m ] to T [ m ] of a bubble eliminating circuit in the thermometer code decoding circuit is consistent and is an exclusive-OR gate delay, which is beneficial to inhibiting burrs in the output of the bubble eliminating circuit;

3. the thermometer code decoding circuit can realize the decoding of two types of thermometer codes, namely high-order full factory low-order full '0' or high-order full '0' low-order full '1';

4. the control of the switching of all the three-state gates and the tubes for the indication of the storage of '0' in the position code decoding circuit of the thermometer decoding circuit is effected simultaneously, which results in the sampling values S [ k-1..0]]The acquisition of (2) is not changed by different sampling values, and is not changed by the change of sampling bit number k. I.e. maximum path delay t of thermometer decoding circuit₂Independent of the size of the sampling value and the sampling precision (k), all are：t₂One inverter delay + one exclusive-or gate delay + one tri-state gate delay is favorable for realizing a high-precision (large k value) voltage comparison type high-speed analog-to-digital converter;

5. theoretically, the maximum operating frequency of the thermometer code decoding circuit is as follows:wherein max { } denotes taking the maximum value, t₂Delaying the maximum path of the thermometer code decoding circuit; t is t_coOutputting delay for an output register of a thermometer code decoder; t is t_opThe delay time from input to output of the voltage comparison network operational amplifier;

6. the output Tm of the bubble eliminating circuit in the thermometer code decoding circuit is only determined by qm-1 and qm, the circuit structure is simple, and the layout and wiring can be favorably carried out by using design software;

7. the position decoding circuit of the thermometer code decoding circuit is simple in structure and beneficial to layout and wiring by using design software.

Drawings

FIG. 1 is a circuit configuration of a pipelined analog-to-digital converter with 2-stage register sets, where 1.1 is a voltage signal V at a sampling point_in(ii) a 1.2 is a voltage comparison network, which is generally composed of a linear resistance network and a comparator group; 1.3 is the n-bit thermometer code output Q [ n-1..0] of the voltage comparison network](ii) a 1.4 is a bubble elimination circuit, and 1.5 is the output T [ n-1..0] of an n-bit bubble elimination circuit](ii) a 1.6 is a position code decoding circuit; 1.7 is the k-bit output sampling value D [ k-1..0] of the position code decoding circuit](ii) a 1.8 is the operating clock clk of the high speed analog to digital converter; 1.9 is the output enable signal of the high speed analog to digital converter

The low level is active;

fig. 2 is a schematic circuit diagram of the present invention when n is 8 and k is 3;

FIG. 3 is a schematic diagram of a circuit for decoding a position code based on a ROM structure, wherein 1.6.1 is the (i + 2) th normally closed switch; 1.6.2 is a bus; 1.6.3 is the ith storage unit hung on the bus; 1.6.4 is the storage element enable terminal EN.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.

It will be understood by those skilled in the art that, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the prior art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The technical scheme of the invention is further explained in detail by combining the attached drawings:

the invention provides a thermometer code decoding circuit aiming at a two-stage pipelined voltage comparison type high-speed analog-to-digital converter, which mainly comprises a bubble eliminating circuit and a position code decoding circuit based on a Read Only Memory (ROM) structure. As shown in FIG. 1, a register bank of a voltage comparison network outputs an n-bit thermometer code Q [ n-1..0 ]; the input of a bubble eliminating circuit of the thermometer code decoding circuit is n thermometer codes Q [ n-1..0], and the output is n T [ n-1..0 ]; the input of the position code decoding circuit of the thermometer decoding circuit is T [ n-1..0] of n bits, and the output is k-bit sampling value S [ k-1..0 ]. The relation between k and n is required to satisfy:

2^k-1≤n≤2^k。

for the bubble elimination circuit, the relationship between the input and the output thereof satisfies:

for a position code decoding circuit based on a ROM structure, the relationship between the input and the output thereof satisfies:

S[k-1..0]＝Bin[x]，x＝max{i|_T[i]＝1}，0≤i＜n

wherein Bin (x) represents a k-bit binary number corresponding to the decimal number x; max { i |_T[i]＝1Means solving for T [ n-1..0]]The position value of 1 for the first time from the highest bit to the lowest bit.

The voltage comparison network is composed of n resistors R0 to Rn-1, n operational amplifiers O0 to On-1 and n D triggers Q0 to Qn-1, a reference voltage Vref + and a negative reference voltage Vref-are respectively loaded at two ends of a circuit formed by connecting the resistors R0 to Rn-1 in series according to the numbering sequence, positive phase input ends of the operational amplifiers O0 to On-1 are respectively connected with a signal Vin to be converted, an inverted phase input end of the operational amplifier On-1 is connected with the negative reference voltage Vref-, an inverted phase input end of the operational amplifier Ot is connected with a common end of a resistor Rt and the resistor Rt +1, t belongs to {0, 1., n-2}, an inverted phase input end of the operational amplifier On-1 is connected with the negative reference voltage Vref-, and output ends of the operational amplifier O0 to On-1 are respectively connected with D input ends of the D triggers Q0 to Qn-1.

The bubble elimination circuit is composed of n exclusive ors X0-Xn-1, two input ends of the exclusive or Xn-1 are respectively grounded and connected with an output end of the D trigger Qn-1, two input ends of the exclusive or Xj are respectively connected with an output end of the D trigger Qj and an output end of the D trigger Qj +1, and j belongs to {0, 1., n-2 }.

A schematic diagram of a circuit for decoding a position code based on a ROM structure is shown in fig. 3, in which: the normally closed switch is opened at high level, and the storage content of the ith storage unit is Bin [ i](i is a k-bit binary number corresponding to the i), the enable terminal EN is effective when being in high level, otherwise, a high-impedance state is output. Ith switch SW_iBetween the ith memory cell and the i-1 st memory cell bus]Controlling EN enabling end of ith storage unit and ith switch SW_i. When T [ i ]]When equal to 0, SW_iClosing, and outputting a high-impedance state by the ith storage unit; when T [ i ]]When 1, SW_iIs disconnected at T [ n-1.. i + 1]]In the absence of high level, i.e. SW_i+1To SW_n-1All are closedUnder the condition, the content Bin [ i ] of the ith memory cell]Through the bus to S [ k-1..0]]. As can be seen, only the content of the memory location corresponding to the highest bit 1 in T will be sent to S [ k-1..0]]。

And taking n as 8, k as 3, wherein the output of the voltage comparison network of the high-speed analog-to-digital converter is Q, the output of the bubble elimination circuit in the thermometer code decoding circuit is T, the output of the position code decoding circuit of the thermometer code decoding circuit is S, and the input and the output of the bubble elimination circuit are given under the condition of different bubbles. As shown in fig. 2, the thermometer code decoding circuit includes resistors R0 to R7, comparators O0 to O7, D flip-flops Q0 to Q10, exclusive ors X0 to X7, inverters N0 to N6, three-state gates T00 to T06, T10 to T16 and T20 to T26, MOS transistors S00, S01, S02, S03, S10, S11, S14, S15, S20, S22, S24, S26, SV0, SV1, and SV 2.

Signals to be converted are respectively input from positive phase input ends of comparators O0 to O7, positive reference voltage Vref + and negative reference voltage Vref-are respectively loaded at two ends of a circuit formed by connecting resistors R0 to R7 in series in a numbering sequence, a common end of a resistor R0 and a resistor R1 is connected with an inverted input end of a comparator O0, a common end of a resistor R1 and a resistor R2 is connected with an inverted input end of a comparator O1, a common end of a resistor R2 and a resistor R3 is connected with an inverted input end of a comparator O2, a common end of a resistor R3 and a resistor R4 is connected with an inverted input end of a comparator O3, a common end of a resistor R4 and a resistor R5 is connected with an inverted input end of a comparator O4, a common end of a resistor R5 and a resistor R6 is connected with an inverted input end of a comparator O5, a common end of a resistor R6 and a resistor R7 are connected with an inverted input end of a comparator O6, a negative phase reference voltage Vref-6 is connected with an inverted, the output ends of the comparators O0-O7 are respectively connected with the input ends of the D flip-flops Q0-Q7.

An output terminal of a D flip-flop Q0 is connected to one input terminal of an exclusive-or X0, output terminals of D flip-flop Q1 are connected to the other input terminal of the exclusive-or X0 and one input terminal of the exclusive-or X1, output terminals of D flip-flop Q2 are connected to the other input terminal of the exclusive-or X1 and one input terminal of the exclusive-or X2, output terminals of D flip-flop Q3 are connected to the other input terminal of the exclusive-or X2 and one input terminal of the exclusive-or X3, output terminals of D flip-flop Q4 are connected to the other input terminal of the exclusive-or X3 and one input terminal of the exclusive-or X4, output terminals of D flip-flop Q5 are connected to the other input terminal of the exclusive-or X4 and one input terminal of the exclusive-or X5, output terminals of D flip-flop Q6 are connected to the other input terminal of the exclusive-or X5 and one input terminal of the exclusive-or X6, output terminals of D flip-flop Q7 are connected to the other input terminal of, the other input of the xor X7 is connected to ground.

The output end of an exclusive-or X0 is connected to the input end of an inverter N0, the output end of an exclusive-or X1 is connected to the input end of an inverter N1 and the gate of a MOS transistor S26, the output end of an exclusive-or X2 is connected to the input end of an inverter N2 and the gate of a MOS transistor S15, the output end of an exclusive-or X3 is connected to the input end of an inverter N3, the gate of a MOS transistor S14 and the gate of a MOS transistor S24, the output end of an exclusive-or X4 is connected to the input end of an inverter N4 and the gate of a MOS transistor S03, the output end of an exclusive-or X5 is connected to the input end of an inverter N5, the gate of a MOS transistor S02 and the gate of a MOS transistor S22, the output end of an exclusive-or X22 is connected to the input end of an inverter N22, the gate of a MOS transistor S22 and the gate of a MOS transistor S22.

The output end of an inverter N0 is respectively connected with the control enabling ends of the three-state gates T00, T10 and T20, the output end of an inverter N1 is respectively connected with the control enabling ends of the three-state gates T01, T11 and T21, the output end of an inverter N2 is respectively connected with the control enabling ends of the three-state gates T02, T12 and T22, the output end of an inverter N3 is respectively connected with the control enabling ends of the three-state gates T03, T13 and T23, the output end of an inverter N4 is respectively connected with the control enabling ends of the three-state gates T04, T14 and T24, the output end of an inverter N5 is respectively connected with the control enabling ends of the three-state gates T05, T15 and T25, and the output end of the inverter N6 is respectively connected with the control enabling ends of the three-state gates T06, T16 and T26.

The sources of the MOS transistors S00, S01, S02, S03, S10, S11, S14, S15, S20, S22, S24, S26 are grounded, the drains of the MOS transistors S00, S10, S20 are connected to the inputs of the tri-state gates T06, T16, T26, the drain of the MOS transistor S01 is connected to the output of the tri-state gate T06 and the input of the tri-state gate T05, the drain of the MOS transistor S11 is connected to the output of the tri-state gate T11 and the input of the tri-state gate T11, the output of the tri-state gate T11 is connected to the input of the tri-state gate T11, the drain of the MOS transistor S11 is connected to the output of the tri-state gate T11, the drain of the tri-state gate T11 is connected to the output of the tri-state gate T11, the output terminal of the tri-state gate T24 is connected to the input terminal of the tri-state gate T23, the output terminal of the tri-state gate T03 is connected to the input terminal of the tri-state gate T02, the drain of the MOS transistor S14 is connected to the output terminal of the tri-state gate T13 and the input terminal of the tri-state gate T12, the drain of the MOS transistor S24 is connected to the output terminal of the tri-state gate T23 and the input terminal of the tri-state gate T22, the output terminal of the tri-state gate T02 is connected to the input terminal of the tri-state gate T01, the drain of the MOS transistor S15 is connected to the output terminal of the tri-state gate T12 and the input terminal of the tri-state gate T11, the output terminal of the tri-state gate T22 is connected to the input terminal of the tri-state gate T21, the output terminal of the tri-state gate T01 is connected to the input terminal of the tri-state gate T00, the output terminal of the tri-state gate T00 is connected to the input terminal of the tri-state gate T00, the drain, the output end of the tri-state gate T10 is respectively connected with the drain of the MOS transistor SV1 and the input end of the D flip-flop Q9, and the output end of the tri-state gate T20 is respectively connected with the drain of the MOS transistor SV2 and the input end of the D flip-flop Q10.

The sources of the MOS tubes SV0, SV1 and SV2 are respectively connected with a voltage source VCC, and the gates of the MOS tubes SV0, SV1 and SV2 are respectively connected with the enabling ends of the analog-to-digital converters.

For thermometer codes shaped as all '1' high bits and all '0' low bits, as shown in table 1.

TABLE 1 thermometer code

For thermometer codes shaped as all '0' high and all '1' low, as shown in table 2.

TABLE 2 thermometer code

Taking Q [7..0]The operating principle of the circuit schematic is explained with reference to "11101100". Q [7.. 0]]Obtaining T [7.. 0] after the exclusive OR operation of an exclusive OR group X0-X7]＝“00110100”。T[5]When inverted by the inverter N2, the tri-state gates T02, T12 and T22 are controlled to be in an off state, and T [4.. 0] is cut off]Is paired with output D [2..0]]The effect of the output; and T [7 ]]After 0 is inverted by an inverter N0, tri-state gates T01, T11 and T21 are in a conducting state; t6]Inverting through inverter N1 results in tri-state gates T02, T12 and T22 being in a conductive state. At the enable end of the analog-to-digital converter

At this time, the tubes SV0, SV1, and SV2 are turned on, and the inputs D of the output register groups Q10, Q9, and Q8 are in a pull-up state. T6]At '0', the tube S26 is in the off state; t5]At 1, the pipe S15 is in a conducting state, the input D of the register Q9 is pulled low to low, the inputs D of the registers Q10 and Q8 are pulled high to high, and the final output S [2..0]]＝“101”。

Each row of the rom in the schematic circuit diagram represents a memory cell whose contents are controlled by the pipes Sx, with the pipe place representing a memory '0' and the pipe-free place representing a memory '1'. A tri-state gate Tx is connected in series between adjacent memory unit bits. The 1 of the highest m-bit in T [ n-1..0] represents the m-bit position of the highest bit in Q [ n-1..0] where the first 01 or 10 change occurs. Even if any air bubble exists in Q [ m-1..0], the influence on S [2..0] is eliminated because T [ m ] is equal to 1 and the tri-state gate group is controlled after inversion by a subsequent inverter.

The maximum operating frequency of the thermometer code decoding circuit is as follows:

wherein max { } denotes taking the maximum value, t₂For maximum path delay, t, of the thermometer code decoding circuit₂One inverter delay + one xor gate delay + one tristate gate delay; t is t_coOutputting a delay for an output register of the thermometer code decoder; t is t_opThe delay time from input to output of the voltage comparison network op-amp.

The above description is only an embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can understand that the modifications or substitutions within the technical scope of the present invention are included in the scope of the present invention, and therefore, the scope of the present invention should be subject to the protection scope of the claims.