阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 冯荣杰 于 2020-04-29 设计创作，主要内容包括：本申请公开了一种半导体器件及其制造方法。该半导体器件包括：衬底；外延层,位于衬底上；绝缘层,位于外延层上；轻掺杂区,位于外延层中；以及导电层,位于绝缘层中,通过引线与轻掺杂区连接。该半导体器件通过设置轻掺杂区和导电层,减小了耗尽线的弯曲程度,进一步减小了耗尽线终端的弯曲程度,延长了耗尽线的长度,从而减小了场强,进而达到了提高半导体器件耐压程度的目的。(The application discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate; an epitaxial layer on the substrate; the insulating layer is positioned on the epitaxial layer; the lightly doped region is positioned in the epitaxial layer; and the conducting layer is positioned in the insulating layer and is connected with the lightly doped region through a lead. The semiconductor device reduces the bending degree of the depletion line by arranging the light doped region and the conducting layer, further reduces the bending degree of the terminal of the depletion line, prolongs the length of the depletion line, reduces the field intensity and further achieves the purpose of improving the withstand voltage degree of the semiconductor device.)

1. A semiconductor device, comprising:

a substrate;

an epitaxial layer on the substrate;

the insulating layer is positioned on the epitaxial layer;

the lightly doped region is positioned in the epitaxial layer; and

and the conducting layer is positioned in the insulating layer and is connected with the lightly doped region through a lead.

2. The semiconductor device of claim 1, further comprising an isolation region in the epitaxial layer extending from the upper surface of the epitaxial layer to the upper surface of the substrate, the isolation region surrounding at least a portion of the lightly doped region,

wherein the insulating layer has a plurality of first contact holes,

the lightly doped region comprises a first lightly doped region which extends from the inner part of the isolation region to the epitaxial layer in a transverse direction and exceeds the isolation region by a first preset length; the conducting layer comprises a first conducting layer which is positioned in the insulating layer and transversely exceeds the first lightly doped region by a third preset length; the lead wire comprises a first lead wire, and the first lead wire is connected with the first lightly doped region through the first contact hole.

3. The semiconductor device according to claim 1, further comprising:

the base region is positioned in the epitaxial layer, and the isolation region surrounds the base region; and

and the emitter region is positioned in the base region.

4. The semiconductor device of claim 3, wherein the lightly doped region further comprises a second lightly doped region extending laterally into the epitaxial layer from an interior of the base region, the second lightly doped region extending a second predetermined length beyond the base region.

5. The semiconductor device of claim 4, wherein the conductive layer further comprises a second conductive layer in the insulating layer laterally beyond the second lightly doped region by a third predetermined length.

6. The semiconductor device according to claim 5, further comprising:

a buried layer located in the substrate and extending into the epitaxial layer; and

and the contact region is positioned between the first lightly doped region and the second lightly doped region, extends from the upper surface of the epitaxial layer to the buried layer, and is at least positioned on one side of the base region.

7. The semiconductor device according to claim 4, wherein a range of doping concentrations of the base region includes: 1E16/cm^-3To 1E20/cm^-3。

8. The semiconductor device of claim 4, wherein the junction depth of the base region ranges from: 0.5um to 10 um.

9. The semiconductor device according to claim 4, wherein a doping concentration of the lightly doped region is 1 to 3 orders of magnitude lower than a doping concentration of the base region.

10. The semiconductor device according to claim 4, wherein a junction depth of the lightly doped region ranges from 30% to 85% of a junction depth of the base region.

11. The semiconductor device of claim 4, wherein the range of second predetermined lengths comprises: the junction depth of the base region is 0.3 to 2 times.

12. The semiconductor device according to claim 5, wherein the insulating layer comprises:

the first insulating layer is positioned on the upper surface of the epitaxial layer;

a second insulating layer on the first insulating layer; and

a third insulating layer on the second insulating layer,

the first conductive layer and the second conductive layer are located on the second insulating layer, and the third insulating layer covers the first conductive layer and the second conductive layer.

13. The semiconductor device according to claim 12, wherein the lead further comprises:

the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the first contact hole;

the third lead is positioned on the surface of the second insulating layer, is connected with the second lightly doped region through the first contact hole and is in an integral structure with the second conducting layer; and

and the fourth lead is positioned on the surface of the second insulating layer and is connected with the emission region through the first contact hole.

14. The semiconductor device according to claim 13, wherein a material of the first conductive layer and the second conductive layer comprises a metal,

the thickness range of the first conductive layer and the second conductive layer comprises: 0.2um to 2 um.

15. The semiconductor device according to claim 13, wherein the second wire functions as a collector, the third wire functions as a base, and the fourth wire functions as an emitter.

16. The semiconductor device according to claim 2, further comprising:

an emitter region located in the epitaxial layer; and

a collector region in the epitaxial layer and surrounding the emitter region, the isolation region surrounding the collector region,

the lightly doped region further comprises a second lightly doped region which transversely extends into the epitaxial layer from the inside of the collector region, and the second lightly doped region exceeds the collector region by a second preset length.

17. The semiconductor device according to claim 16, further comprising:

a buried layer located in the substrate and extending into the epitaxial layer; and

and the contact region is positioned between the first lightly doped region and the second lightly doped region, extends from the upper surface of the epitaxial layer to the buried layer, and is positioned on at least one side of the collector region.

18. The semiconductor device of claim 16, wherein the ranges of doping concentrations of the emitter region and the collector region respectively comprise: 1E16/cm^-3To 1E20/cm^-3。

19. The semiconductor device of claim 16, wherein the junction depths of the emitter region and the collector region respectively comprise: 0.5um to 10 um.

20. The semiconductor device of claim 16, wherein the lightly doped region has a doping concentration that is 1 to 3 orders of magnitude lower than that of the emitter region or the collector region.

21. The semiconductor device of claim 16, wherein a junction depth of the lightly doped region ranges from 30% to 85% of a junction depth of the emitter region or the collector region.

22. The semiconductor device of claim 16, wherein the range of second predetermined lengths comprises: the junction depth of the emitter region or the collector region is 0.3 to 2 times.

23. The semiconductor device according to claim 16, wherein the insulating layer comprises:

the first insulating layer is positioned on the upper surface of the epitaxial layer;

a second insulating layer on the first insulating layer; and

a third insulating layer on the second insulating layer,

the first conductive layer is located on the second insulating layer, and the third insulating layer covers the first conductive layer.

24. The semiconductor device of claim 23, further comprising a second conductive layer located between the second insulating layer and the third insulating layer and laterally beyond the second lightly doped region by the third predetermined length.

25. The semiconductor device of claim 24, wherein the lead further comprises:

the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the first contact hole;

the third lead is positioned on the surface of the second insulating layer and is connected with the second lightly doped region through the first contact hole; and

and the fourth lead is positioned on the surface of the second insulating layer and is connected with the emission region through the first contact hole.

26. The semiconductor device according to claim 25, wherein a material of the first conductive layer comprises a metal, and a range of thicknesses of the first conductive layer comprises: 0.2um to 2 um.

27. The semiconductor device according to claim 25, wherein the second wire serves as a base, the third wire serves as a collector, and the fourth wire serves as an emitter.

28. The semiconductor device according to claim 4 or 16, wherein a concentration range of the lightly doped region comprises 1E15/cm^-3To 3E19/cm^-3。

29. The semiconductor device of claim 4 or 16, wherein the lightly doped region is 5% to 70% of the epitaxial layer in thickness.

30. The semiconductor device of claim 4 or 16, wherein the lightly doped region is 10% to 40% of the epitaxial layer in thickness.

31. The semiconductor device of claim 2, wherein the range of first predetermined lengths comprises: 0.3 to 1.5 times the thickness of the epitaxial layer.

32. The semiconductor device according to claim 5 or 24, wherein the range of the third predetermined length includes: the lightly doped region has a junction depth of 0.3 to 2 times.

33. The semiconductor device according to claim 12 or 23, wherein the first lead is located on a surface of the second insulating layer, wherein the third insulating layer covers the first lead,

the first contact hole sequentially penetrates through the second insulating layer and the first insulating layer,

the first lead and the first conductive layer are of an integral structure.

34. The semiconductor device according to claim 12 or 23, wherein a total thickness range of the first insulating layer and the second insulating layer includes: 0.1um to 3 um.

35. The semiconductor device according to claim 13 or 25, wherein the insulating layer further has a plurality of second contact holes in the third insulating layer, the lead further comprises:

a fifth lead located on the surface of the third insulating layer and contacting the second lead through the second contact hole;

a sixth lead located on the surface of the third insulating layer and contacting the third lead through the second contact hole; and

and the seventh lead is positioned on the surface of the third insulating layer and is in contact with the fourth lead through the second contact hole.

36. The semiconductor device according to claim 36, further comprising a passivation layer on a surface of the third insulating layer, covering the fifth lead, the sixth lead, and the seventh lead.

37. The semiconductor device according to claim 13 or 25, wherein the contact region comprises:

a deep contact region connected to the buried layer; and

and the shallow contact region is positioned above the deep contact region and is respectively connected with the deep contact region and the second lead.

38. A method of manufacturing a semiconductor device, comprising forming a semiconductor device as claimed in any one of claims 1 to 37.

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

In bipolar integrated circuits, the two most common types of devices are: a longitudinal NPN device formed in an N-type epitaxial layer above a P-type substrate and a lateral PNP device formed in an N-type epitaxial layer above a P-type substrate.

Taking an NPN device as an example, the main withstand voltage parameters include: the breakdown voltage Vce of the collector region C to the emitter region E when the base region B is suspended, the breakdown voltage Vcb of the collector region C to the base region B, the breakdown voltage Vbs of the base region B to the substrate and the breakdown voltage Vcs of the collector region C to the substrate when the emitter region E is suspended. In practical applications, Vcs of NPN devices can reach 120 to 130V at most, and Vcb can reach 100V at most, but in some integrated circuit applications, Vcs and Vcb of NPN devices are required to reach 180V or more. For requirements above 180V, typically typical values are desired around 200V to 260V, which is a significant challenge to the process.

Fig. 1 shows a schematic structure of a prior art NPN device. Fig. 2 shows a schematic diagram of a lateral PNP device in the prior art. After the device processing steps are completed, when the whole device is applied under a certain working voltage, a certain thickness of local impurities in the silicon body is depleted, and the boundary of the depleted thickness is called a depletion line. As shown in fig. 1 and 2, the depletion line 10 of the NPN device and the depletion line 20 of the lateral PNP device are both bent to a relatively large degree, and when the epitaxial layer is depleted, the electric field strength is large, so that the breakdown voltage of the device is low, and the device is likely to break down.

Disclosure of Invention

In view of the above, the present disclosure provides a semiconductor device and a method for manufacturing the same, which solves the problem of insufficient voltage endurance of the device due to large bending of the depletion line.

According to an aspect of the present invention, there is provided a semiconductor device including: a substrate; an epitaxial layer on the substrate; the insulating layer is positioned on the epitaxial layer; the lightly doped region is positioned in the epitaxial layer; and the conducting layer is positioned in the insulating layer and is connected with the lightly doped region through a lead.

Preferably, the epitaxial layer further comprises an isolation region located in the epitaxial layer and extending from the upper surface of the epitaxial layer to the upper surface of the substrate, wherein the isolation region surrounds at least part of the lightly doped region, wherein the insulating layer has a plurality of first contact holes, the lightly doped region comprises a first lightly doped region, and the first lightly doped region laterally extends from the inside of the isolation region into the epitaxial layer and exceeds the isolation region by a first predetermined length; the conducting layer comprises a first conducting layer which is positioned in the insulating layer and transversely exceeds the first lightly doped region by a third preset length; the lead wire comprises a first lead wire, and the first lead wire is connected with the first lightly doped region through the first contact hole.

Preferably, the method further comprises the following steps: the base region is positioned in the epitaxial layer, and the isolation region surrounds the base region; and an emitter region in the base region.

Preferably, the lightly doped region further includes a second lightly doped region extending from the inside of the base region into the epitaxial layer, and the second lightly doped region exceeds the base region by a second predetermined length.

Preferably, the conductive layer further comprises a second conductive layer located in the insulating layer and laterally beyond the second lightly doped region by a third predetermined length.

Preferably, the method further comprises the following steps: a buried layer located in the substrate and extending into the epitaxial layer; and the contact region is positioned between the first lightly doped region and the second lightly doped region and extends from the upper surface of the epitaxial layer to the buried layer, and the contact region is at least positioned on one side of the base region.

Preferably, the doping concentration range of the base region includes: 1E16/cm^-3To 1E20/cm^-3。

Preferably, the junction depth of the base region includes: 0.5um to 10 um.

Preferably, the doping concentration of the lightly doped region is 1 to 3 orders of magnitude lower than that of the base region.

Preferably, the junction depth of the lightly doped region ranges from 30% to 85% of the junction depth of the base region.

Preferably, the range of the second predetermined length includes: the junction depth of the base region is 0.3 to 2 times.

Preferably, the insulating layer includes: the first insulating layer is positioned on the upper surface of the epitaxial layer; a second insulating layer on the first insulating layer; and a third insulating layer on the second insulating layer, wherein the first conductive layer and the second conductive layer are on the second insulating layer, and the third insulating layer covers the first conductive layer and the second conductive layer.

Preferably, the lead further comprises: the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the first contact hole; the third lead is positioned on the surface of the second insulating layer, is connected with the second lightly doped region through the first contact hole and is in an integral structure with the second conducting layer; and a fourth lead located on the surface of the second insulating layer and connected with the emission region through the first contact hole.

Preferably, the material of the first conductive layer and the second conductive layer comprises metal, and the thickness range of the first conductive layer and the second conductive layer comprises: 0.2um to 2 um.

Preferably, the second lead serves as a collector, the third lead serves as a base, and the fourth lead serves as an emitter.

Preferably, the substrate, the isolation region, the base region, the first lightly doped region and the second lightly doped region are of a first doping type, the epitaxial layer, the buried layer, the contact region and the emitter region are of a second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

Preferably, the method further comprises the following steps: an emitter region located in the epitaxial layer; and the collector region is positioned in the epitaxial layer and surrounds the emitter region, and the isolation region surrounds the collector region, wherein the lightly doped region further comprises a second lightly doped region which transversely extends into the epitaxial layer from the interior of the collector region, and the second lightly doped region exceeds the collector region by a second preset length.

Preferably, the method further comprises the following steps: a buried layer located in the substrate and extending into the epitaxial layer; and the contact region is positioned between the first lightly doped region and the second lightly doped region, extends from the upper surface of the epitaxial layer to the buried layer, and is positioned on at least one side of the collector region.

Preferably, the ranges of the doping concentrations of the emitter region and the collector region respectively include: 1E16/cm^-3To 1E20/cm^-3。

Preferably, the junction depths of the emitter region and the collector region respectively include: 0.5um to 10 um.

Preferably, the lightly doped region has a doping concentration 1 to 3 orders of magnitude lower than that of the emitter region or the collector region.

Preferably, the junction depth of the lightly doped region ranges from 30% to 85% of the junction depth of the emitter region or the collector region.

Preferably, the range of the second predetermined length includes: the junction depth of the emitter region or the collector region is 0.3 to 2 times.

Preferably, the insulating layer includes: the first insulating layer is positioned on the upper surface of the epitaxial layer; a second insulating layer on the first insulating layer; and a third insulating layer on the second insulating layer, wherein the first conductive layer is on the second insulating layer, and the third insulating layer covers the first conductive layer.

Preferably, the second conductive layer is located between the second insulating layer and the third insulating layer and laterally exceeds the second lightly doped region by the third predetermined length.

Preferably, the lead further comprises: the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the first contact hole; the third lead is positioned on the surface of the second insulating layer and is connected with the second lightly doped region through the first contact hole; and a fourth lead located on the surface of the second insulating layer and connected with the emission region through the first contact hole.

Preferably, the material of the first conductive layer comprises a metal, and the range of the thickness of the first conductive layer comprises: 0.2um to 2 um.

Preferably, the second lead is used as a base, the third lead is used as a collector, and the fourth lead is used as an emitter.

Preferably, the concentration range of the lightly doped region comprises 1E15/cm^-3To 3E19/cm^-3。

Preferably, the thickness of the lightly doped region is 5% to 70% of the epitaxial layer.

Preferably, the thickness of the lightly doped region is 10% to 40% of the epitaxial layer.

Preferably, the range of the first predetermined length includes: 0.3 to 1.5 times the thickness of the epitaxial layer.

Preferably, the range of the third predetermined length includes: the lightly doped region has a junction depth of 0.3 to 2 times.

Preferably, the first lead is located on the surface of the second insulating layer, the third insulating layer covers the first lead, the first contact hole sequentially penetrates through the second insulating layer and the first insulating layer, and the first lead and the first conductive layer are in an integral structure.

Preferably, the total thickness range of the first insulating layer and the second insulating layer includes: 0.1um to 3 um.

Preferably, the insulating layer further has a plurality of second contact holes in the third insulating layer, and the lead further includes: a fifth lead located on the surface of the third insulating layer and contacting the second lead through the second contact hole; a sixth lead located on the surface of the third insulating layer and contacting the third lead through the second contact hole; and a seventh lead located on the surface of the third insulating layer and contacting the fourth lead through the second contact hole.

Preferably, the passivation layer is located on the surface of the third insulating layer and covers the fifth lead, the sixth lead and the seventh lead.

Preferably, the contact zone comprises: a deep contact region connected to the buried layer; and a shallow contact region located above the deep contact region and connected to the deep contact region and the second lead, respectively.

Preferably, the substrate, the isolation region, the emitter region, the collector region, the first lightly doped region, and the second lightly doped region are of a first doping type, the epitaxial layer, the buried layer, and the contact region are of a second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming a semiconductor device as described above.

According to the semiconductor device and the manufacturing method thereof disclosed by the invention, the lightly doped region is arranged in the epitaxial layer, and the conducting layer connected with the lightly doped region is arranged above the epitaxial layer, so that the bending degree of a depletion line is reduced, the length and the width of the depletion layer are prolonged, the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the semiconductor device is further achieved.

According to the semiconductor device and the manufacturing method thereof disclosed by the invention, the first lightly doped region transversely extends to the epitaxial layer from the inside of the isolation region, the first lightly doped region exceeds the first preset length of the isolation region, the bending degree of the depletion line is reduced, the width of the depletion layer is prolonged, namely the depletion line is prolonged, the bending degree of the terminal of the depletion line is reduced, the length of the depletion line is prolonged through the first conducting layer which is positioned above the first lightly doped region and transversely exceeds the third preset length of the first lightly doped region, the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the semiconductor device is further achieved.

According to the semiconductor device and the manufacturing method thereof disclosed by the invention, the second lightly doped region transversely extends to the epitaxial layer from the inside of the heavily doped region, the second lightly doped region exceeds the second preset length of the heavily doped region, so that the bending degree of the depletion line is further reduced, the bending degree of the terminal of the depletion line is further reduced through the second conducting layer which is positioned above the second lightly doped region and transversely exceeds the third preset length of the second lightly doped region, the length of the depletion line is prolonged, the field intensity is reduced, and the purpose of improving the withstand voltage degree of the semiconductor device is further achieved.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

Fig. 1 shows a schematic structure of a prior art NPN device.

Fig. 2 shows a schematic diagram of a lateral PNP device in the prior art.

Fig. 3 shows a schematic structural diagram of an NPN device according to the first embodiment of the present disclosure.

Fig. 4 to 7 show a flow chart of a method of manufacturing the NPN device of fig. 3.

Fig. 8 shows a schematic structural diagram of a lateral PNP device according to a second embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

Numerous specific details of the present disclosure are set forth in the following description in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details. The explanations regarding the depletion lines appearing hereinafter are: after the device processing steps are completed, when the entire device is applied at a certain operating voltage, a certain thickness of local impurities in the silicon body (epitaxial layer) is depleted, and the boundary of the depleted thickness is called a depletion line. Wherein, in the epitaxial layer, the edge close to the isolation region bears the highest withstand voltage value.

Fig. 3 shows a schematic structural diagram of an NPN device according to the first embodiment of the present disclosure.

As shown in fig. 3, the NPN device of the first embodiment of the present disclosure includes: the semiconductor device includes a substrate 100, a buried layer 110, an epitaxial layer 120, an isolation region, a contact region, a base region 151 (a heavily doped region), an emitter region 152, a lightly doped region, an insulating layer 210, a passivation layer 230, a conductive layer, and a plurality of leads, the lightly doped region being connected to the conductive layer through the leads. The isolation region includes a lower isolation region 131 and an upper isolation region 132 that are connected. The contact region includes a deep contact region 141 and a shallow contact region 142 that are connected. The lightly doped region includes a first lightly doped region 161 and a second lightly doped region 162. The insulating layer 210 includes a first insulating layer 211, a second insulating layer 212, and a third insulating layer 213. The conductive layers include a first conductive layer 312 and a second conductive layer 332. The plurality of lead lines include a first lead line 311, a second lead line 320, a third lead line 331, a fourth lead line 340, a fifth lead line 350, a sixth lead line 360, and a seventh lead line 370. The substrate 100, the isolation region, the base region 151, the first lightly doped region 161, and the second lightly doped region 162 are of a first doping type, the buried layer 110, the epitaxial layer 120, the contact region, and the emitter region are of a second doping type, the first doping type is opposite to the second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping. In the present embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. However, the first embodiment of the invention is not limited thereto, and the first doping type may also be N-type doping, and the second doping type is P-type doping.

In the present embodiment, the substrate 100 is a P-type doped crystal-oriented silicon layer. An epitaxial layer 120 is located on the substrate 100. The buried layer 110 is located in the substrate 100 and the epitaxial layer 120. The isolation region is located in the epitaxial layer 120, wherein the lower isolation region 131 is connected to the substrate 100, and the upper isolation region 132 is connected to the first lightly doped region 161. Contact regions are located in the epitaxial layer 120 and at least on one side of the base region 151, wherein the deep contact regions 141 are connected to the buried layer 110 and the shallow contact regions 142 are connected to the second wiring 320.

Base region 151 is located in epitaxial layer 120, and emitter region 152 is located in base region 151, wherein the range of doping concentration of base region 151 includes: 1E16/cm^-3To 1E20/cm^-3The junction depth of the base region 151 includes: 0.5um to 10 um.

The first lightly doped region 161 is located in the epitaxial layer 120 and laterally extends to the epitaxial layer 120 from inside of the isolation region, the first lightly doped region 161 exceeds a first preset length L1 of the isolation region, the second lightly doped region 162 is located in the epitaxial layer 120 and laterally extends to the epitaxial layer 120 from inside of the base region 151, the second lightly doped region 162 exceeds a second preset length L2 of the base region 151, wherein doping concentrations of the first lightly doped region 161 and the second lightly doped region 162 are both 1 to 3 orders of magnitude lower than that of the base region 151, and a range of junction depths of the first lightly doped region 161 and the second lightly doped region 162 includes: 30% to 85% of the junction depth of the base region 151, firstThe range of the fixed length L1 includes: the second predetermined length L2 is in a range of 0.3 to 1.5 times the thickness of the epitaxial layer 120, including: the junction depth of base region 151 is 0.3 to 2 times. The concentration range of the lightly doped region comprises 1E15/cm^-3To 3E19/cm^-3. The thickness of the lightly doped region is 5% to 70% of the epitaxial layer, and preferably, the thickness of the lightly doped region is 10% to 40% of the epitaxial layer.

The insulating layer 210 is disposed on the epitaxial layer 120, wherein the first insulating layer 211 is disposed on the epitaxial layer 120, the second insulating layer 212 is disposed on the first insulating layer 211, and the third insulating layer 213 is disposed on the second insulating layer 212. In the present embodiment, the insulating layer 210 is formed with first contact holes respectively corresponding to the first lightly doped region 161, the shallow contact region 142, the base region 151 and the emitter region 152, and the first contact holes sequentially pass through the second insulating layer 212 and the first insulating layer 211. The total thickness of the first insulating layer 211 and the second insulating layer 212 ranges from 0.1um to 3 um.

The first lead line 311, the first conductive layer 312, the second lead line 320, the second conductive layer 332, the third lead line 331, and the fourth lead line 340 are located on the second insulating layer 212, and one end of the first lead line 311, the second lead line 320, the third lead line 331, and the fourth lead line 340 is connected to the first lightly doped region 161, the shallow contact region 142, the base region 151, and the emitter region 151 through a first contact hole on the insulating layer 210, respectively. First lead line 311 serves as a ground terminal, second lead line 320 serves as a collector, third lead line 331 serves as a base, and fourth lead line 340 serves as an emitter.

In this embodiment, the other ends of the first lead 311, the second lead 320, the third lead 331 and the fourth lead 340 respectively extend laterally along the surface of the insulating layer 212, and the first lead 311 contacts the first conductive layer 312, and the third lead 331 contacts the second conductive layer 332. The first lead 311, the first conductive layer 312, the second lead 320, the second conductive layer 332, the third lead 331, and the fourth lead 340 are formed in the same step, and the materials are the same.

In some other embodiments, the first lead line 311 may be separated from the first conductive layer 312, and the third lead line 331 may be separated from the second conductive layer 332.

The first conductive layer 312 is located above the first lightly doped region 161, and a portion of the first conductive layer 312 beyond an edge of the first doped region 161 reaches a third predetermined length L3. The second conductive layer 332 is located above the second lightly doped region 162, and a portion of the second conductive layer 332 beyond an edge of the second doped region 162 reaches a third predetermined length L3, wherein the third predetermined length L3 includes: the junction depth of the first lightly doped region 161 or the second lightly doped region 162 is 0.3 to 2 times, and the thickness ranges of the first conductive layer 312 and the second conductive layer include: 0.2um to 2 um.

The third insulating layer 213 covers the first lead 311, the first conductive layer 312, the second lead 320, the second conductive layer 332, the third lead 331, and the fourth lead 340. The third insulating layer 213 has second contact holes formed at the connection portions of the second lead 320, the third lead 331, and the second conductive layer 332, and at the corresponding portions of the fourth lead 340, respectively.

The fifth lead 350, the sixth lead 360 and the seventh lead 370 are all located on the surface of the third insulating layer 213, one end of each of the fifth lead 350, the sixth lead 360 and the seventh lead 370 extends transversely along the surface of the third insulating layer 213, and the other end of each of the fifth lead, the sixth lead 360 and the seventh lead 370 is in contact with the second lead 320, the third lead 331 and the fourth lead 340 through corresponding second contact holes, so that the electrical extraction of the collector, the base and the emitter is realized.

The passivation layer 230 is located on the third insulating layer 213, and covers the fifth lead 350, the sixth lead 360, and the seventh lead 370, so as to prevent external mobile ions from entering an electric field region in the device structure to cause contamination, and ensure high temperature reliability of the device.

In the embodiment of the present invention, in order to ensure high voltage endurance of the device, it is necessary to ensure that the depletion line 121 is as smooth as possible, so it is necessary to use the length of L1 for transition, and if the L1 is set too large, the depletion line 121 may have a steep slope, which causes the voltage at the steep slope to be too high and the device to be broken down, so it is appropriate to set the thickness of L1 to be 0.3 to 1.5 times the thickness of the epitaxial layer 120. Similarly, the arrangement of L2, L3 is similar to L1.

A method of manufacturing the NPN device of fig. 3 will be described in detail with reference to fig. 4 to 7.

The manufacturing method starts with a substrate 100. The substrate 100 is a P-type doped crystal orientation silicon substrate.

Then, a thick oxide layer is formed on the substrate 100 by using a thermal oxidation process, a doping window of a buried layer is formed on the thick oxide layer by using a photolithography and etching process, and a buried layer 110 is formed in the substrate 100 through the doping window of the buried layer, wherein the buried layer 110 is doped N-type. A doping window of the lower isolation region is formed on the thick oxide layer by using photolithography and etching processes, and a lower isolation region 131 is formed in the substrate 100 through the doping window of the isolation region, wherein the lower isolation region 131 is doped P-type. The thick oxide layer is removed and an epitaxial layer 120 is formed on the substrate 100, wherein the epitaxial layer 120 is doped N-type. In this process, the buried layer 110 and the lower isolation region 131 diffuse into the epitaxial layer 120, so that the buried layer 110 and the lower isolation region 131 are disposed adjacent to the substrate 100 and the epitaxial layer 120, as shown in fig. 4.

Then, an oxide layer is formed on the epitaxial layer 120 by using a thermal oxidation process, a doping window of a deep contact region is formed on the oxide layer by using a photolithography and etching process, a deep contact region 141 is formed in the epitaxial layer 120 through the doping window of the deep contact region, and after diffusion and junction pushing, the deep contact region 141 is connected to the buried layer 110, as shown in fig. 4, wherein the doping type of the deep contact region 140 is N-type doping, and in this embodiment, the doping material of the deep contact region 140 is phosphorus.

Then, a doping window of the upper isolation region is formed on the oxide layer by using photolithography and etching processes, an upper isolation region 132 is formed in the epitaxial layer 120 through the doping window of the upper isolation region, and after junction pushing, the upper isolation region 132 is connected to the lower isolation region 131, as shown in fig. 4, wherein the doping type of the upper isolation region 132 is P-type doping.

Then, the oxide layer is removed to expose the epitaxial layer 120, a thin oxide layer is formed on the epitaxial layer 120, and a base region 151 is formed in the epitaxial layer 120, as shown in fig. 4, wherein the doping type of the base region 151 is P-type doping.

The range of doping concentration of the base region 151 includes: 1E16/cm^-3To 1E20/cm^-3The junction depth of the base region 151 includes: from 0.5um to 10 um.

Then, a first lightly doped region 161 and a second lightly doped region 162 are formed in the epitaxial layer 120, the first lightly doped region 161 laterally extends from inside the isolation region to the epitaxial layer 120, the first lightly doped region 161 exceeds the isolation region by a first preset length L1, the second lightly doped region 162 laterally extends from inside the base region 151 to the epitaxial layer 120, and the second lightly doped region 162 exceeds the base region 151 by a second preset length L2, as shown in fig. 4, wherein the first lightly doped region 161 and the second lightly doped region 162 are both P-type doped and have doping concentrations 1 to 3 orders of magnitude lower than that of the base region 151, and the junction depths of the first lightly doped region 161 and the second lightly doped region 162 both include: the junction depth of the base region 151 is 30% to 85%, and the range of the first predetermined length L1 includes: the second predetermined length L2 is in a range of 0.3 to 1.5 times the thickness of the epitaxial layer 120, including: the junction depth of base region 151 is 0.3 to 2 times.

Then, annealing and oxidizing the base region 151, and forming an emitter region 152 in the base region 151 and a shallow contact region 142 in the epitaxial layer 120 by using photolithography, etching, annealing and oxidizing processes, wherein the shallow contact region 142 forms an ohmic contact with the deep contact region 141, as shown in fig. 4, wherein the doping types of the emitter region 152 and the shallow contact region 142 are N-type doping.

Further, the emitter region 152 and the shallow contact region 142 are annealed and oxidized to form a first insulating layer 211 and a second insulating layer 212 on the epitaxial layer 120, as shown in fig. 5. The total thickness of the first insulating layer 211 and the second insulating layer 212 is in the range: 0.1um to 3 um.

Further, a plurality of first contact holes 201 are formed on the first insulating layer 211 and the second insulating layer 212, as shown in fig. 5.

In this step, the first insulating layer 211 and the second insulating layer 212 are etched to form first contact holes 201 respectively above the first lightly doped region 161, the shallow contact region 142, the base region 151, and the emitter region 152.

Further, a metal is deposited on the second insulating layer 212, and a first lead 311, a first conductive layer 312, a second lead 320, a second conductive layer 332, a third lead 331, and a fourth lead 340 are formed by photolithography, etching, and the like, as shown in fig. 6. One end of each of the first lead line 311, the second lead line 320, the third lead line 331 and the fourth lead line 340 is connected to the first lightly doped region 161, the shallow contact region 142, the base region 151 and the emitter region 152 through the first contact hole 101, and the other end extends laterally along the surface of the second insulating layer 212. First lead line 311 serves as a ground terminal, second lead line 320 serves as a collector, third lead line 331 serves as a base, and fourth lead line 340 serves as an emitter.

In the present embodiment, the first lead 311 contacts the first conductive layer 312, and the third lead 331 contacts the second conductive layer 332. The first wire 311, the first conductive layer 312, the second wire 320, the second conductive layer 332, the third wire 331, and the fourth wire 340 are formed in the same step, and are made of the same material, for example, metal or metal compound such as copper, aluminum, SiCr, Ti, and TiN.

In some other embodiments, the first lead line 311 may be separated from the first conductive layer 312, and the third lead line 331 may be separated from the second conductive layer 332.

In the present embodiment, the first conductive layer 312 is located above the first lightly doped region 161, and a portion of the first conductive layer 312 beyond the edge of the first doped region 161 reaches a third predetermined length L3. The second conductive layer 332 is located above the second lightly doped region 162, and a portion of the second conductive layer 332 beyond an edge of the second doped region 162 reaches a third predetermined length L3, wherein the third predetermined length L3 includes: the junction depth of the first lightly doped region 161 or the second lightly doped region 162 is 0.3 to 2 times, and the thickness ranges of the first conductive layer 312 and the second conductive layer include: 0.2um to 2 um.

Further, a third insulating layer 213 is formed on the second insulating layer 212, as shown in fig. 7. The third insulating layer 213 covers the first lead 311, the first conductive layer 312, the second lead 320, the second conductive layer 332, the third lead 331, and the fourth lead 340. The first insulating layer 211, the second insulating layer 212, and the third insulating layer 213 constitute an insulating layer 210.

Further, a fifth wiring 350, a sixth wiring 360, and a seventh wiring 370 are formed on the surface of the third insulating layer 213, as shown in fig. 3.

In this step, the third insulating layer 213 is first etched to form a second contact hole over the second field plate 332, the fourth lead wire 340, and the junction of the second lead wire 320, the third lead wire 331, and the second conductive layer 332, for example. Then, a second metal layer is deposited on the third insulating layer 213 by photolithography, etching, and the like, and a fifth lead 350, a sixth lead 360, and a seventh lead 370 are formed by photolithography, etching, and the like. One end of the fifth wire 350, one end of the sixth wire 360, and one end of the seventh wire 370 extend laterally along the surface of the third insulating layer 213, and the other end of the fifth wire is connected to the second wire 320, the third wire 331, and the fourth wire 340 through the second contact hole, respectively, so as to electrically extract the collector, the base, and the emitter.

Further, a passivation layer 230 is formed on the third insulating layer 213, and finally the NPN device shown in fig. 3 is formed by steps of bonding window lithography, etching, and the like.

According to the first embodiment of the present disclosure, the second lightly doped region 162 is formed in the epitaxial layer 120, and the length range of the two ends of the second lightly doped region 162 extending out of the base region 151, the doping concentration of the second lightly doped region 162, and the junction depth range are controlled, so that the bending degree of the depletion line 121 of the device is reduced, and the purpose of making the boundary electric field distribution uniform is achieved.

According to the first embodiment of the present disclosure, the first lightly doped region 161 is formed in the epitaxial layer 120, and the length range of the first lightly doped region 161 beyond the upper isolation region 132, the doping concentration of the first lightly doped region 161, and the junction depth range are controlled, so that the bending degree of the depletion line 121 of the device is reduced, and the purpose of making the boundary electric field distribution uniform is achieved.

According to the NPN device and the method of manufacturing the same of the first embodiment of the present invention, the degree of bending of the depletion line 121 is reduced by the first lightly doped region 161 laterally extending from the inside of the isolation region to the epitaxial layer, the second lightly doped region 162 laterally extending from the inside of the base region 151 to the epitaxial layer, by the first conductive layer 312 located above the first lightly doped region 161 and laterally extending beyond the first lightly doped region 161 by a certain length, and the second conductive layer 332 located above the second lightly doped region 162 and laterally extending beyond the second lightly doped region 162 by a predetermined length, and by controlling the thicknesses of the first conductive layer 312 and the second conductive layer 332, controlling the extent of the extent, the length of a depletion boundary, namely the length of a depletion line, is prolonged, the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the NPN device is further achieved.

In some specific embodiments, when the integrated circuit longitudinal NPN device is suspended in the emitter region, the breakdown voltage Vcs of the collector region to the substrate is increased to around 200 to 260V, and the breakdown voltage Vcb of the collector region to the base region is increased to around 200V to 260V.

Fig. 8 shows a schematic structural diagram of a lateral PNP device according to a second embodiment of the present disclosure.

As shown in fig. 8, a lateral PNP device of a second embodiment of the present disclosure includes: the semiconductor device includes a substrate 500, a buried layer 510, an epitaxial layer 520, an isolation region including a lower isolation region 531 and an upper isolation region 532 which are in contact, a contact region including a deep contact region 541 and a shallow contact region 542 which are in contact, a heavily doped region including a collector region 551 and an emitter region 552, a first lightly doped region 561, a second lightly doped region 562, a first wiring 611, a first conductive layer 612, a second wiring 620, a third wiring 630, a fourth wiring 640, a fifth wiring 650, a sixth wiring 660, a seventh wiring 670, a first insulating layer 711, a second insulating layer 712, a third insulating layer 713, and a passivation layer 730. The substrate 500, the isolation region, the collector region 551, the emitter region 552, the first lightly doped region 561, and the second lightly doped region 562 are of a first doping type, the buried layer 510, the epitaxial layer 520, and the contact region are of a second doping type, the first doping type is opposite to the second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping. In the present embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. However, the first embodiment of the invention is not limited thereto, and the first doping type may also be N-type doping, and the second doping type is P-type doping.

The first lightly doped region 561 is located in the epitaxial layer 520 and extends laterally from inside the upper isolation region 532 to the epitaxial layer 520 beyond the upper isolation region 532 by a first predetermined length L1. A second lightly doped region 562 is located in epitaxial layer 520 and extends laterally from within base region 551 to epitaxial layer 520 beyond base region 551 by a second predetermined length L2. The range of the first predetermined length L1 includes: the second predetermined length L2 is in a range of 0.3 to 1.5 times the thickness of the epitaxial layer 520 and includes: collector 551 or emitter 552 are 0.3 to 2 times deeper than the junction depth. The first conductive layer 612 is located above the first lightly doped region 561, and extends laterally beyond the first lightly doped region 561 by a third predetermined length L3, where the third predetermined length L3 includes: the junction depth of the first lightly doped region is 0.3 to 2 times.

The structure and the manufacturing method of the lateral PNP device according to the second embodiment of the present disclosure are similar to those of the NPN device according to the first embodiment, and are not repeated herein, but are different from the first embodiment in that in the lateral PNP device according to the second embodiment, the collector region 551 surrounds the emitter region 552, and the periphery of the emitter region 552 is surrounded by the collector region 551. The second conductive layer is not disposed around the second lightly doped region, the first lead 611 is connected to the first lightly doped region 561 and the first conductive layer 612 through the first contact hole, respectively, and serves as a ground lead of the lateral PNP device, the second lead 620 is connected to the shallow contact region 542 through the first contact hole and serves as a base of the lateral PNP device, the third lead 630 is connected to the collector region 551 through the first contact hole and serves as a collector of the lateral PNP device, and the fourth lead 640 is connected to the emitter region 552 through the contact hole and serves as an emitter of the lateral PNP device. The fifth lead 650, the sixth lead 660 and the seventh lead 670 are respectively connected with the second lead 620, the third lead 630 and the fourth lead 640 through corresponding second contact holes for leading out the motor.

In other alternative embodiments of the second embodiment, a second conductive layer is further included, and the second conductive layer is disposed between the second insulating layer 712 and the third insulating layer 713, and such that a portion of the second conductive layer beyond the edge of the second doped region 562 reaches a third predetermined length L3.

According to the lateral PNP device of the second embodiment of the present invention, the bending degree of the depletion line is reduced by the first lightly doped region laterally extending from the inside of the isolation region to the epitaxial layer, the second lightly doped region laterally extending from the inside of the collector region to the epitaxial layer, the bending degree of the depletion line is further reduced by the first conductive layer located above the first lightly doped region and laterally extending beyond the first lightly doped region by a certain length, and the second conductive layer located above the second lightly doped region and laterally extending beyond the second lightly doped region by a predetermined length, and the thicknesses of the first conductive layer and the second conductive layer are controlled, the lateral extent of the first conductive layer beyond the first lightly doped region and the lateral extent of the second conductive layer beyond the second lightly doped region is controlled, so that the bending degree of the terminal of the depletion line (for example, a position near the isolation region and the upper surface of the epitaxial layer) is further reduced, and the length of the depletion boundary is extended, namely, the length of the depletion line is prolonged, the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the transverse PNP device is further achieved.

In some specific embodiments, when the lateral PNP device of the integrated circuit is suspended in the emitter region, the breakdown voltage Vcs of the collector region to the substrate is increased to around 200V to 260V, and the breakdown voltage Vbs of the base region to the substrate is increased to around 200V to 260V.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.