阅读说明：本技术 半导体器件及其制造方法 (Semiconductor device and method for manufacturing the same ) 是由 冯荣杰 于 2020-04-29 设计创作，主要内容包括：本申请公开了一种半导体器件及其制造方法。该半导体器件包括：衬底；外延层,位于衬底上；绝缘层,位于外延层上,具有多个接触孔；隔离区,位于外延层中,从外延层的上表面延伸至衬底的上表面；第一轻掺杂区,位于外延层中并且从隔离区内部横向延伸至外延层中,第一轻掺杂区超出隔离区第一预定长度；以及第一导电层,位于绝缘层上,并且位于第一轻掺杂区上方,横向超出第一轻掺杂区第三预定长度,其中,第一引线经由接触孔与第一轻掺杂区相连。该半导体器件通过设置第一轻掺杂区和第一导电层,减小了耗尽线的弯曲程度,进一步减小了耗尽线终端的弯曲程度,延长了耗尽线的长度,从而减小了场强,进而达到了提高半导体器件耐压程度的目的。(The application discloses a semiconductor device and a method of manufacturing the same. The semiconductor device includes: a substrate; an epitaxial layer on the substrate; the insulating layer is positioned on the epitaxial layer and is provided with a plurality of contact holes; the isolation region is positioned in the epitaxial layer and extends from the upper surface of the epitaxial layer to the upper surface of the substrate; the first lightly doped region is positioned in the epitaxial layer and transversely extends into the epitaxial layer from the interior of the isolation region, and the first lightly doped region exceeds the isolation region by a first preset length; and a first conductive layer on the insulating layer and above the first lightly doped region, and laterally beyond the first lightly doped region by a third predetermined length, wherein the first lead is connected to the first lightly doped region via the contact hole. The semiconductor device reduces the bending degree of the depletion line by arranging the first lightly doped region and the first conducting layer, further reduces the bending degree of the terminal of the depletion line, prolongs the length of the depletion line, reduces the field intensity and further achieves the purpose of improving the withstand voltage degree of the semiconductor device.)

1. A semiconductor device, comprising:

a substrate;

an epitaxial layer on the substrate;

the insulating layer is positioned on the epitaxial layer and is provided with a plurality of contact holes;

an isolation region in the epitaxial layer extending from an upper surface of the epitaxial layer to an upper surface of the substrate;

a first lightly doped region in the epitaxial layer and extending laterally into the epitaxial layer from inside the isolation region, the first lightly doped region exceeding the isolation region by a first predetermined length; and

a first conductive layer in the insulating layer and above the first lightly doped region and laterally beyond the first lightly doped region by a third predetermined length,

the first lightly doped region is connected with the first field plate through a first lead wire, and the first lead wire is respectively connected with the first lightly doped region and the first field plate through contact holes.

2. The semiconductor device according to claim 1, further comprising:

the base region is positioned in the epitaxial layer, and the isolation region surrounds the base region; and

and the emitter region is positioned in the base region.

3. The semiconductor device of claim 2, further comprising a second lightly doped region extending laterally into the epitaxial layer from an interior of the base region, the second lightly doped region extending a second predetermined length beyond the base region.

4. The semiconductor device of claim 3, further comprising a second conductive layer on the insulating layer and over the second lightly doped region a third predetermined length laterally beyond the second lightly doped region.

5. The semiconductor device according to claim 4, further comprising:

a buried layer located in the substrate and the epitaxial layer; and

and the contact region is positioned between the first lightly doped region and the second lightly doped region, extends from the upper surface of the epitaxial layer to the buried layer, and is at least positioned on one side of the base region.

6. The semiconductor device according to claim 3, wherein a range of doping concentrations of the base region includes: 1E16/cm^-3To 1E20/cm^-3。

7. The semiconductor device of claim 3, wherein the junction depth of the base region ranges from: 0.5um to 10 um.

8. The semiconductor device according to claim 3, wherein the doping concentration of each of the first lightly doped region and the second lightly doped region is 1 to 3 orders of magnitude lower than the doping concentration of the base region.

9. The semiconductor device of claim 3, wherein the junction depths of the first lightly doped region and the second lightly doped region each comprise: the junction depth of the base region is 30% to 85%.

10. The semiconductor device of claim 3, wherein the range of second predetermined lengths comprises: the junction depth of the base region is 0.3 to 2 times.

11. The semiconductor device according to claim 1, further comprising:

an emitter region located in the epitaxial layer;

the collector region is positioned in the epitaxial layer and surrounds the emitter region, and the isolation region surrounds the collector region; and

and the second lightly doped region transversely extends into the epitaxial layer from the interior of the collector region, and exceeds the collector region by a second preset length.

12. The semiconductor device according to claim 11, further comprising:

a buried layer located in the substrate and extending into the epitaxial layer; and

and the contact region is positioned between the first lightly doped region and the second lightly doped region, extends from the upper surface of the epitaxial layer to the buried layer, and is positioned on at least one side of the collector region.

13. The semiconductor device of claim 12, further comprising a second conductive layer in the insulating layer and over the second lightly doped region a third predetermined length laterally beyond the second lightly doped region.

14. The semiconductor device of claim 11, wherein the ranges of doping concentrations of the emitter region and the collector region respectively comprise: 1E16/cm^-3To 1E20/cm^-3。

15. The semiconductor device of claim 11, wherein the junction depths of the emitter region and the collector region respectively comprise: 0.5um to 10 um.

16. The semiconductor device of claim 11, wherein the doping concentration of each of the first and second lightly doped regions is 1 to 3 orders of magnitude lower than that of the emitter region or the collector region.

17. The semiconductor device of claim 11, wherein a range of junction depths of the first lightly doped region and the second lightly doped region each comprise 30% to 85% of a junction depth of the emitter region or the collector region.

18. The semiconductor device of claim 11, wherein the range of second predetermined lengths comprises: the junction depth of the emitter region or the collector region is 0.3 to 2 times.

19. The semiconductor device of claim 1, wherein the range of first predetermined lengths comprises: 0.3 to 1.5 times the thickness of the epitaxial layer.

20. The semiconductor device according to claim 4 or 13, wherein the range of the third predetermined length includes: the junction depth of the first lightly doped region or the second lightly doped region is 0.3 to 2 times.

21. The semiconductor device according to claim 3 or 11, wherein the concentration ranges of the first lightly doped region and the second lightly doped region each comprise 1E15/cm^-3To 3E19/cm^-3。

22. The semiconductor device according to claim 3 or 11, wherein the first lightly doped region and the second lightly doped region each have a thickness of 5 to 70% of the epitaxial layer.

23. The semiconductor device according to claim 3 or 11, wherein the thickness of each of the first lightly doped region and the second lightly doped region is 10% to 40% of the epitaxial layer.

24. The semiconductor device according to claim 4 or 13, wherein a material of the first conductive layer and the second conductive layer is selected from polysilicon or semi-insulating polysilicon,

the range of thicknesses of the first conductive layer and the second conductive layer includes: 0.03um to 1 um.

25. The semiconductor device according to claim 4 or 13, wherein a material of the first conductive layer and the second conductive layer is any one selected from SiCr, Ti, and TiN,

the thickness range of the first conductive layer and the second conductive layer comprises: 0.01um to 0.5 um.

26. The semiconductor device according to claim 5, wherein the insulating layer comprises:

the first insulating layer is positioned on the upper surface of the epitaxial layer;

a second insulating layer on the first insulating layer; and

a third insulating layer on the second insulating layer,

wherein the first conductive layer and the second conductive layer are located between the second insulating layer and the third insulating layer.

27. The semiconductor device according to claim 26, further comprising:

the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the contact hole;

the third lead is positioned on the surface of the second insulating layer and is connected with the second lightly doped region through the contact hole; and

and the fourth lead is positioned on the surface of the second insulating layer and is connected with the emitting region through the contact hole.

28. The semiconductor device according to claim 27, wherein the second wiring serves as a collector, the third wiring serves as a base, and the fourth wiring serves as an emitter.

29. The semiconductor device according to claim 13, wherein the insulating layer comprises:

the first insulating layer is positioned on the upper surface of the epitaxial layer;

a second insulating layer on the first insulating layer; and

a third insulating layer on the second insulating layer,

wherein the first conductive layer and the second conductive layer are located between the second insulating layer and the third insulating layer.

30. The semiconductor device according to claim 29, further comprising:

the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the contact hole;

the third lead is positioned on the surface of the second insulating layer and is connected with the second lightly doped region through the contact hole; and

and the fourth lead is positioned on the surface of the second insulating layer and is connected with the emitting region through the contact hole.

31. The semiconductor device according to claim 30, wherein the second wire serves as a base, the third wire serves as a collector, and the fourth wire serves as an emitter.

32. The semiconductor device according to claim 26 or 29, wherein a range of a sum of thicknesses of the first insulating layer and the second insulating layer includes: 0.1um to 3 um.

33. The semiconductor device according to claim 27 or 30, further comprising a passivation layer over the third insulating layer, covering the first lead, the second lead, the third lead, and the fourth lead.

34. The semiconductor device according to claim 27 or 30, wherein the contact region comprises:

a deep contact region connected to the buried layer; and

and the shallow contact region is positioned above the deep contact region and is respectively connected with the deep contact region and the second lead.

35. A method of manufacturing a semiconductor device, comprising forming a semiconductor device as claimed in any one of claims 1 to 34.

Technical Field

The present disclosure relates to the field of semiconductor technology, and more particularly, to a semiconductor device and a method for manufacturing the same.

Background

In bipolar integrated circuits, the two most common types of devices are: a longitudinal NPN device formed in an N-type epitaxial layer above a P-type substrate and a lateral PNP device formed in an N-type epitaxial layer above a P-type substrate.

Taking an NPN device as an example, the main withstand voltage parameters include: the breakdown voltage Vcbo of the collector region C to the base region B, the breakdown voltage Vbs of the base region B to the substrate and the breakdown voltage Vcs of the collector region C to the substrate when the base region B is suspended. In practical applications, the Vcs of the NPN device can reach 120 to 130V at most, and the Vcbo can reach 100V at most, but in some integrated circuit applications, the Vcs and the Vcbo of the NPN device need to reach more than 180V. For requirements above 180V, typically a typical value is desired around 200 to 260V, which is a significant challenge to the process.

Fig. 1 shows a schematic structure of a prior art NPN device. Fig. 2 shows a schematic diagram of a lateral PNP device in the prior art. After the device processing steps are completed, when the whole device is applied under a certain working voltage, a certain thickness of local impurities in the silicon body is depleted, and the boundary of the depleted thickness is called a depletion line. As shown in fig. 1 and 2, the depletion line 10 of the NPN device and the depletion line 20 of the lateral PNP device are both bent to a relatively large degree, and when the epitaxial layer is depleted, the electric field strength is large, so that the breakdown voltage of the device is low, and the device is likely to break down.

Disclosure of Invention

In view of the above, the present disclosure provides a semiconductor device and a method for manufacturing the same, which solves the problem of insufficient voltage endurance of the device due to large bending of the depletion line.

According to an aspect of the present invention, there is provided a semiconductor device including: a substrate; an epitaxial layer on the substrate; the insulating layer is positioned on the epitaxial layer and is provided with a plurality of contact holes; an isolation region in the epitaxial layer extending from an upper surface of the epitaxial layer to an upper surface of the substrate; a first lightly doped region in the epitaxial layer and extending laterally into the epitaxial layer from inside the isolation region, the first lightly doped region exceeding the isolation region by a first predetermined length; and the first conducting layer is positioned in the insulating layer, positioned above the first lightly doped region and transversely exceeds the first lightly doped region by a third preset length, wherein the first lightly doped region is connected with the first field plate through a first lead wire, and the first lead wire is respectively connected with the first lightly doped region and the first field plate through contact holes.

Preferably, the method further comprises the following steps: the base region is positioned in the epitaxial layer, and the isolation region surrounds the base region; and an emitter region in the base region.

Preferably, the epitaxial layer further comprises a second lightly doped region extending from the inside of the base region into the epitaxial layer, and the second lightly doped region exceeds the base region by a second predetermined length.

Preferably, the device further comprises a second conductive layer located on the insulating layer and above the second lightly doped region, and laterally beyond the second lightly doped region by a third predetermined length.

Preferably, the method further comprises the following steps: a buried layer located in the substrate and the epitaxial layer; and the contact region is positioned between the first lightly doped region and the second lightly doped region and extends from the upper surface of the epitaxial layer to the buried layer, and the contact region is at least positioned on one side of the base region.

Preferably, the doping concentration range of the base region includes: 1E16/cm^-3To 1E20/cm^-3。

Preferably, the junction depth of the base region includes: 0.5um to 10 um.

Preferably, the doping concentration of the first lightly doped region and the doping concentration of the second lightly doped region are both 1 to 3 orders of magnitude lower than the doping concentration of the base region.

Preferably, the junction depths of the first lightly doped region and the second lightly doped region both include: the junction depth of the base region is 30% to 85%.

Preferably, the range of the second predetermined length includes: the junction depth of the base region is 0.3 to 2 times.

Preferably, the substrate, the isolation region, the base region, the first lightly doped region and the second lightly doped region are of a first doping type, the epitaxial layer, the buried layer, the contact region and the emitter region are of a second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

An emitter region located in the epitaxial layer; the collector region is positioned in the epitaxial layer and surrounds the emitter region, and the isolation region surrounds the collector region; and the second lightly doped region transversely extends into the epitaxial layer from the interior of the collector region, and exceeds the collector region by a second preset length.

Preferably, the method further comprises the following steps: a buried layer located in the substrate and extending into the epitaxial layer; and the contact region is positioned between the first lightly doped region and the second lightly doped region, extends from the upper surface of the epitaxial layer to the buried layer, and is positioned on at least one side of the collector region.

Preferably, the semiconductor device further comprises a second conductive layer located in the insulating layer and above the second lightly doped region, and laterally exceeds the second lightly doped region by a third predetermined length.

Preferably, the ranges of the doping concentrations of the emitter region and the collector region respectively include: 1E16/cm^-3To 1E20/cm^-3。

Preferably, the junction depths of the emitter region and the collector region respectively include: 0.5um to 10 um.

Preferably, the doping concentration of each of the first lightly doped region and the second lightly doped region is 1 to 3 orders of magnitude lower than that of the emitter region or the collector region.

Preferably, the junction depths of the first lightly doped region and the second lightly doped region both range from 30% to 85% of the junction depth of the emitter region or the collector region.

Preferably, the range of the second predetermined length includes: the junction depth of the emitter region or the collector region is 0.3 to 2 times.

Preferably, the range of the first predetermined length includes: 0.3 to 1.5 times the thickness of the epitaxial layer.

Preferably, the range of the third predetermined length includes: the junction depth of the first lightly doped region or the second lightly doped region is 0.3 to 2 times.

Preferably, the concentration ranges of the first lightly doped region and the second lightly doped region both include 1E15/cm^-3To 3E19/cm^-3。

Preferably, the thickness of each of the first lightly doped region and the second lightly doped region is 5% to 70% of the epitaxial layer.

Preferably, the thickness of the first lightly doped region and the thickness of the second lightly doped region are both 10% to 40% of the epitaxial layer.

Preferably, the material of the first conductive layer and the second conductive layer is selected from polysilicon or semi-insulating polysilicon, and the range of the thickness of the first conductive layer and the second conductive layer includes: 0.03um to 1 um.

Preferably, the material of the first conductive layer and the second conductive layer is selected from any one of SiCr, Ti, and TiN, and the thickness range of the first conductive layer and the second conductive layer includes: 0.01um to 0.5 um.

Preferably, the insulating layer includes: the first insulating layer is positioned on the upper surface of the epitaxial layer; a second insulating layer on the first insulating layer; and a third insulating layer on the second insulating layer, wherein the first conductive layer and the second conductive layer are located between the second insulating layer and the third insulating layer.

Preferably, the method further comprises the following steps: the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the contact hole; the third lead is positioned on the surface of the second insulating layer and is connected with the second lightly doped region through the contact hole; and a fourth lead located on the surface of the second insulating layer and connected with the emission region through the contact hole.

Preferably, the second lead serves as a collector, the third lead serves as a base, and the fourth lead serves as an emitter.

Preferably, the insulating layer includes: the first insulating layer is positioned on the upper surface of the epitaxial layer; a second insulating layer on the first insulating layer; and a third insulating layer on the second insulating layer, wherein the first conductive layer and the second conductive layer are located between the second insulating layer and the third insulating layer.

Preferably, the method further comprises the following steps: the second lead is positioned on the surface of the second insulating layer and is connected with the contact region through the contact hole; the third lead is positioned on the surface of the second insulating layer and is connected with the second lightly doped region through the contact hole; and a fourth lead located on the surface of the second insulating layer and connected with the emission region through the contact hole.

Preferably, the second lead is used as a base, the third lead is used as a collector, and the fourth lead is used as an emitter.

Preferably, the range of the sum of the thicknesses of the first insulating layer and the second insulating layer includes: 0.1um to 3 um.

Preferably, a passivation layer is further included on the third insulating layer, covering the first, second, third, and fourth leads.

Preferably, the contact zone comprises: a deep contact region connected to the buried layer; and a shallow contact region located above the deep contact region and connected to the deep contact region and the second lead, respectively.

Preferably, the substrate, the isolation region, the emitter region, the collector region, the first lightly doped region, and the second lightly doped region are of a first doping type, the epitaxial layer, the buried layer, and the contact region are of a second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping.

According to another aspect of the present invention, there is provided a method of manufacturing a semiconductor device, comprising forming the semiconductor device described above.

According to the semiconductor device and the manufacturing method thereof disclosed by the invention, the first lightly doped region transversely extends to the epitaxial layer from the inside of the isolation region, the first lightly doped region exceeds the first preset length of the isolation region, the bending degree of the depletion line is reduced, the width of the depletion layer is prolonged, namely the depletion line is prolonged, and the bending degree of the terminal of the depletion line is reduced through the first conducting layer which is positioned above the first lightly doped region and transversely exceeds the third preset length of the first lightly doped region, so that the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the semiconductor device is further achieved.

According to the semiconductor device and the manufacturing method thereof disclosed by the invention, the second lightly doped region transversely extends to the epitaxial layer from the inside of the heavily doped region, the second lightly doped region exceeds the second preset length of the heavily doped region, so that the bending degree of the depletion line is further reduced, the bending degree of the terminal of the depletion line is further reduced through the second conducting layer which is positioned above the second lightly doped region and transversely exceeds the third preset length of the second lightly doped region, the length of a depletion boundary is prolonged, namely the length of the depletion line is prolonged, the field intensity is reduced, and the purpose of improving the withstand voltage degree of the semiconductor device is further achieved.

In addition, according to the semiconductor device and the manufacturing method thereof of the present disclosure, the first conductive layer and the second conductive layer are polysilicon conductive layers, which are located in the insulating layer, and the first lead and the third lead are respectively in contact with the first lightly doped region and the second lightly doped region, so that a wiring pattern is simple without changing a lead layout in the prior art, thereby reducing a production cost.

Drawings

The above and other objects, features and advantages of the present disclosure will become more apparent from the following description of the embodiments of the present disclosure with reference to the accompanying drawings.

Fig. 1 shows a schematic structure of a prior art NPN device.

Fig. 2 shows a schematic diagram of a lateral PNP device in the prior art.

Fig. 3 shows a schematic structural diagram of an NPN device according to the first embodiment of the present disclosure.

Fig. 4 to 9 show sectional views of the manufacturing method of the NPN device according to the first embodiment of the invention at various stages.

Fig. 10 shows a schematic structural diagram of a lateral PNP device according to a second embodiment of the present disclosure.

Fig. 11 shows a schematic structural diagram of a lateral PNP device according to a third embodiment of the present disclosure.

Detailed Description

The present disclosure will be described in more detail below with reference to the accompanying drawings. Like elements in the various figures are denoted by like reference numerals. For purposes of clarity, the various features in the drawings are not necessarily drawn to scale. In addition, certain well known components may not be shown.

Numerous specific details of the present disclosure are set forth in the following description in order to provide a more thorough understanding of the invention. However, as will be understood by those skilled in the art, the present disclosure may be practiced without these specific details. The explanations regarding the depletion lines appearing hereinafter are: after the device processing steps are completed, when the entire device is applied at a certain operating voltage, a certain thickness of local impurities in the silicon body (epitaxial layer) is depleted, and the boundary of the depleted thickness is called a depletion line. Wherein, in the epitaxial layer, the edge close to the isolation region bears the highest withstand voltage value.

Fig. 3 shows a schematic structural diagram of an NPN device according to the first embodiment of the present disclosure.

As shown in fig. 3, the NPN device of the first embodiment of the present disclosure includes: the semiconductor device includes a substrate 100, a buried layer 110, an epitaxial layer 120, an isolation region, a contact region, a base region 151 (a heavily doped region), an emitter region 152, a first lightly doped region 161, a second lightly doped region 162, an insulating layer 210, a passivation layer 230, a first conductive layer 311, a second conductive layer 312, a first lead 321, a second lead 322, a third lead 323, and a fourth lead 324. The substrate 100, the isolation region, the base region 151, the first lightly doped region 161, and the second lightly doped region 162 are of a first doping type, the buried layer 110, the epitaxial layer 120, the contact region, and the emitter region are of a second doping type, the first doping type is opposite to the second doping type, the first doping type is selected from one of P-type doping and N-type doping, and the second doping type is selected from the other of P-type doping and N-type doping. In the present embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. However, the first embodiment of the invention is not limited thereto, and the first doping type may also be N-type doping, and the second doping type is P-type doping.

In the present embodiment, the buried layer 110 is located in the substrate 100 and the epitaxial layer 120. An epitaxial layer 120 is located on the substrate 100. The isolation region is located in the epitaxial layer 120 to form a zigzag structure, and includes a lower isolation region 131 and an upper isolation region 132 connected to each other, the lower isolation region 131 is connected to the substrate 100, and the upper isolation region 132 is connected to the first lightly doped region 161. Contact regions are located in epitaxial layer 120, wherein the contact regions are located at least on one side of base region 151, or peripherally enclosed around base region 151. The contact regions include a deep contact region 141 and a shallow contact region 142 connected to each other, the deep contact region 141 is connected to the buried layer 110, and the shallow contact region 142 is connected to the second wiring 322.

Base region 151 is located in epitaxial layer 120, and emitter region 152 is located in base region 151, wherein the range of doping concentration of base region 151 includes: 1E16/cm^-3To 1E20/cm^-3The junction depth of the base region 151 includes: 0.5um to 10 um.

The first lightly doped region 161 is located in the epitaxial layer 120 and laterally extends into the epitaxial layer 120 from the inside of the isolation region, the first lightly doped region 161 exceeds the isolation region by a first predetermined length L1, the second lightly doped region 162 is located in the epitaxial layer 120 and laterally extends into the epitaxial layer 120 from the inside of the base region 151, the second lightly doped region 162 exceeds the base region 151 by a second predetermined length L2, wherein the doping concentrations of the first lightly doped region 161 and the second lightly doped region 162 are both 1 to 3 orders of magnitude lower than the doping concentration of the base region 151, and the junction depths of the first lightly doped region 161 and the second lightly doped region 162 both include: the junction depth of the base region 151 is 30% to 85%, and the range of the first predetermined length L1 includes: the second predetermined length L2 is in a range of 0.3 to 1.5 times the thickness of the epitaxial layer 120, including: the junction depth of base region 151 is 0.3 to 2 times. The concentration range of the first lightly doped region 161 and the second lightly doped region 162 includes 1E15/cm^-3To 3E19/cm^-3. The junction depth of the first lightly doped region 161 and the second lightly doped region 162 is 5% -70% of the thickness of the epitaxial layer 120. Preferably, the junction depth of the first lightly doped region 161 and the second lightly doped region 162 is 10% -40% of the thickness of the epitaxial layer.

The insulating layer 210 is on the epitaxial layer 120 and has a plurality of contact holes, and the insulating layer 210 includes: a first insulating layer 211, a second insulating layer 212, and a third insulating layer 213 stacked in this order, wherein a range of a sum of thicknesses of the first insulating layer 211 and the second insulating layer 212 includes: 0.1um to 3um, the effect of the first conductive layer 311 and the second conductive layer 312 to smooth the depletion line is the best within this thickness range.

The first conductive layer 311 and the second conductive layer 312 are located in the insulating layer 210, and further, the first conductive layer 311 and the second conductive layer 312 are located between the second insulating layer 212 and the third insulating layer 213, wherein the first conductive layer 311 is located above the first lightly doped region 161 and laterally exceeds the first lightly doped region 161 by a third predetermined length L3, and the second conductive layer 312 is located above the second lightly doped region 162 and laterally exceeds the second lightly doped region 162 by a third predetermined length L3. On the surface of the second insulating layer 212, the first conductive layer 311 and the second conductive layer 312 form a zigzag structure, and the first conductive layer 311 surrounds the second conductive layer 312. The length of the first conductive layer 311 laterally beyond the isolation region is the sum of a first predetermined length L1 and a third predetermined length L3, the length of the second conductive layer 312 laterally beyond the base region 151 is the sum of a first predetermined length L1 and a third predetermined length L3, wherein the range of the third predetermined length L3 includes: the first lightly doped region 161 is 0.2 to 2 times deeper than the junction depth.

In the embodiment of the present invention, in order to ensure high voltage endurance of the device, it is necessary to ensure that the bending degree of the depletion line 121 is as smooth as possible, so that it is necessary to use the length of L1 for transition, and if the L1 is set too large, the depletion line 121 may have a steep slope, so that the voltage at the steep slope is too high and the device is broken down, so that it is appropriate to set the thickness of L1 to be 0.3 to 1.5 times of the thickness of the epitaxial layer 120. Similarly, the arrangement of L2 and L3 is similar to L1.

In this embodiment, the material of the first conductive layer 311 and the second conductive layer 312 includes polysilicon, and the thickness ranges of the first conductive layer 311 and the second conductive layer 312 each include: 0.03um to 1 um.

In some other embodiments, the material of the first conductive layer 311 and the second conductive layer 312 includes semi-insulating polysilicon, and the thickness ranges of the first conductive layer 311 and the second conductive layer 312 each include: 0.03um to 1 um.

The bending degree of the terminal (for example, a position close to the isolation region and the upper surface of the epitaxial layer) of the depletion line 121 is further reduced by using the polysilicon conducting layer, the length of a depletion boundary is prolonged, namely the length of the depletion line is prolonged, the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the NPN device is further achieved.

In still other embodiments, the material of the first conductive layer 311 and the second conductive layer 312 includes any one of various metal sheet resistors such as SiCr, Ti, TiN, and the like, and the thickness ranges of the first conductive layer 311 and the second conductive layer 312 include: 0.01um to 0.5 um.

A first wire 321, a second wire 322, a third wire 323, and a fourth wire 324 are disposed on the insulating layer 210, and further, the first wire 321, the second wire 322, the third wire 323, and the fourth wire 324 are disposed on the third insulating layer 213, where the first wire 321 is connected to the first lightly doped region 161 and the first conductive layer 311 through contact holes and serves as a ground terminal of the NPN device, the second wire 322 is connected to the shallow contact region 142 through contact holes and serves as a collector of the NPN device, the third wire 323 is connected to the base region 151 and the second conductive layer 312 through contact holes and serves as a base of the NPN device, and the fourth wire 324 is connected to the emitter region 152 through contact holes and serves as an emitter of the NPN device.

The passivation layer 230 is located on the insulating layer 210 and covers the first lead 321, the second lead 322, the third lead 323, and the fourth lead 324, so as to prevent external mobile ions from entering an electric field region in the device structure to cause contamination, and ensure high temperature reliability of the device.

Fig. 4 to 9 show sectional views of the manufacturing method of the NPN device according to the first embodiment of the invention at various stages.

The manufacturing method starts with a substrate 100. The substrate 100 is a P-type doped crystal orientation silicon substrate.

Then, a thick insulating layer is formed on the substrate 100 by using a thermal oxidation process, a doping window of a buried layer is formed on the thick insulating layer by using a photolithography and etching process, and a buried layer 110 is formed in the substrate 100 through the doping window of the buried layer, wherein the buried layer 110 is doped N-type. A doping window of the lower isolation region is formed on the thick insulating layer by using photolithography and etching processes, and a lower isolation region 131 is formed in the substrate 100 through the doping window of the isolation region, wherein the lower isolation region 131 is doped P-type. The thick insulating layer is removed and an epitaxial layer 120 is formed on the substrate 100, wherein the epitaxial layer 120 is doped N-type. In this process, the buried layer 110 and the lower isolation region 131 diffuse into the epitaxial layer 120, so that the buried layer 110 and the lower isolation region 131 are disposed adjacent to the substrate 100 and the epitaxial layer 120, as shown in fig. 4.

Then, an insulating layer is formed on the epitaxial layer 120 by using a thermal oxidation process, a doping window for a deep contact region is formed on the insulating layer by using a photolithography and etching process, a deep contact region 141 is formed in the epitaxial layer 120 through the doping window for the deep contact region, and after diffusion and push junction, the deep contact region 141 is connected to the buried layer 110, as shown in fig. 4, wherein the doping type of the deep contact region 141 is N-type doping, and in this embodiment, the doping material of the deep contact region 140 is phosphorus.

Then, a doping window of the upper isolation region is formed on the insulating layer by using photolithography and etching processes, an upper isolation region 132 is formed in the epitaxial layer 120 through the doping window of the upper isolation region, and after junction pushing, the upper isolation region 132 is connected to the lower isolation region 131, as shown in fig. 4, wherein the doping type of the upper isolation region 132 is P-type doping.

Then, the insulating layer is removed to expose the epitaxial layer 120, a thin insulating layer is formed on the epitaxial layer 120, and a base region 151 is formed in the epitaxial layer 120, as shown in fig. 4, wherein the doping type of the base region 151 is P-type doping.

The range of doping concentration of the base region 151 includes: 1E16/cm^-3To 1E20/cm^-3The junction depth of the base region 151 includes: 0.5um to 10 um.

Then, a first lightly doped region 161 and a second lightly doped region 162 are formed in the epitaxial layer 120, the first lightly doped region 161 laterally extends into the epitaxial layer from the inside of the isolation region, the first lightly doped region 161 exceeds the isolation region by a first predetermined length L1, the second lightly doped region 162 laterally extends into the epitaxial layer 120 from the inside of the base region 151, and the second lightly doped region 162 exceeds the base region 151 by a second predetermined length L2, as shown in fig. 4, wherein the first lightly doped region 161 and the second lightly doped region 162 are both P-type doped and have doping concentrations 1 to 3 orders of magnitude lower than the doping concentration of the base region 151, and the junction depths of the first lightly doped region 161 and the second lightly doped region 162 both include: the junction depth of the base region 151 is 30% to 85%, and the range of the first predetermined length L1 includes: the second predetermined length L2 is in a range of 0.3 to 1.5 times the thickness of the epitaxial layer 120, including: the junction depth of base region 151 is 0.3 to 2 times.

Then, annealing and oxidizing the base region 151, and forming an emitter region 152 in the base region 151 and a shallow contact region 142 in the epitaxial layer 120 by using photolithography, etching, annealing and oxidizing processes, wherein the shallow contact region 142 forms an ohmic contact with the deep contact region 141, as shown in fig. 4, wherein the doping types of the emitter region 152 and the shallow contact region 142 are N-type doping.

Then, a first insulating layer 211 and a second insulating layer 212 are sequentially formed on the epitaxial layer 120, as shown in fig. 5, wherein a range of a sum of thicknesses of the first insulating layer 211 and the second insulating layer 212 includes: 0.1um to 3 um.

Then, a first conductive layer 311 and a second conductive layer 312 are formed on the second insulating layer 212 by deposition, doping, annealing, photolithography and etching processes, as shown in fig. 6, wherein the first conductive layer 311 is located above the first lightly doped region 161 and laterally exceeds the first lightly doped region 161 by a third predetermined length L3, and the second conductive layer 312 is located above the second lightly doped region 162 and laterally exceeds the second lightly doped region 162 by a third predetermined length L3. On the surface of the second insulating layer 212, the first conductive layer 311 and the second conductive layer 312 form a zigzag structure, and the first conductive layer 311 surrounds the second conductive layer 312. Wherein the range of the third predetermined length L3 includes: the junction depth of the first lightly doped region is 0.2 to 2 times.

In this embodiment, the material of the first conductive layer 311 and the second conductive layer 312 includes polysilicon, and the thickness ranges of the first conductive layer 311 and the second conductive layer 312 each include: 0.03um to 1 um.

In some other embodiments, the material of the first conductive layer 311 and the second conductive layer 312 includes semi-insulating polysilicon, and the thickness ranges of the first conductive layer 311 and the second conductive layer 312 each include: 0.03um to 1 um.

In still other embodiments, the material of the first conductive layer 311 and the second conductive layer 312 includes any one of various metal sheet resistors such as SiCr, Ti, TiN, and the like, and the thickness ranges of the first conductive layer 311 and the second conductive layer 312 include: 0.01um to 0.5 um.

Then, a third insulating layer 213 is formed over the second insulating layer 212 covering the first conductive layer 311 and the second conductive layer 312, as shown in fig. 7.

Then, the insulating layer 210 composed of the first insulating layer 211, the second insulating layer 212 and the third insulating layer 213 is etched to form a plurality of contact holes 201, wherein a portion of the first lightly doped region 161, the first conductive layer 311, the shallow contact region 142, the second conductive layer 312, the base region 151 and the emitter region 152 are respectively exposed through the corresponding contact holes 201, as shown in fig. 8.

Then, a first lead 321, a second lead 322, a third lead 323, and a fourth lead 324 are formed on the third insulating layer 213 by deposition, photolithography, and etching processes, wherein the first lead 321 is connected to the first lightly doped region 161 and the first conductive layer 311 through the contact hole 201, respectively, and serves as a ground lead of the NPN device, the second lead 322 is connected to the shallow contact region 142 through the contact hole 201, and serves as a collector lead of the NPN device, the third lead 323 is connected to the base region 151 and the second conductive layer 312 through the contact hole 201, and serves as a base lead of the NPN device, and the fourth lead 324 is connected to the emitter region 152 through the contact hole 201, and serves as an emitter lead of the NPN device, as shown in fig. 9.

Then, a passivation layer 230 is formed on the third insulating layer 213 covering the first, second, third and fourth wires 321, 322, 323 and 324, and a bonding window is formed on the passivation layer 230 by using photolithography and etching processes, so as to form the NPN device according to the first embodiment of the present invention as shown in fig. 3.

According to the first embodiment of the present disclosure, the second lightly doped region 162 is formed in the epitaxial layer 120, and the length range of the two ends of the second lightly doped region 162 extending out of the base region 151, the doping concentration of the second lightly doped region 162, and the junction depth range are controlled, so that the bending degree of the depletion line 121 of the device is reduced, and the purpose of making the boundary electric field distribution uniform is achieved.

According to the first embodiment of the present disclosure, the first lightly doped region 161 is formed in the epitaxial layer 120, and the length range of the first lightly doped region 161 beyond the upper isolation region 132, the doping concentration of the first lightly doped region 161, and the junction depth range are controlled, so that the bending degree of the depletion line 121 of the device is reduced, and the purpose of making the boundary electric field distribution uniform is achieved.

According to the NPN device and the method of manufacturing the same of the first embodiment of the present invention, the degree of bending of the depletion line 121 is reduced by the first lightly doped region 161 laterally extending from the inside of the isolation region to the epitaxial layer, the second lightly doped region 162 laterally extending from the inside of the base region 151 to the epitaxial layer, by the first conductive layer 311 located above the first lightly doped region 161 and laterally extending beyond the first lightly doped region 161 by a certain length, and the second conductive layer 312 located above the second lightly doped region 162 and laterally extending beyond the second lightly doped region 162 by a predetermined length, and by controlling the thicknesses of the first conductive layer 311 and the second conductive layer 312, controlling the extent of the first conductive layer 311 laterally extending beyond the first lightly doped region 161 and the extent of the second conductive layer 312 laterally extending beyond the second lightly doped region 162, thereby further reducing the degree of bending of the terminal end of the depletion line 121 (e.g., a position near the isolation region and the upper surface of the epitaxial layer), the length of a depletion boundary, namely the length of a depletion line, is prolonged, the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the NPN device is further achieved.

In some specific embodiments, when the integrated circuit longitudinal NPN device is suspended in the emitter region, the breakdown voltage Vcs of the collector region to the substrate is increased to around 200 to 260V, and when the emitter is suspended, the breakdown voltage Vcbo of the collector region to the base region is increased to around 200V to 260V.

Fig. 10 shows a schematic structural diagram of a lateral PNP device according to a second embodiment of the present disclosure.

As shown in fig. 10, a lateral PNP device of a second embodiment of the present disclosure includes: the semiconductor device includes a substrate 500, a buried layer 510, an epitaxial layer 520, an isolation region including a lower isolation region 531 and an upper isolation region 532 which are in contact, a contact region including a deep contact region 541 and a shallow contact region 542 which are in contact, a collector region 551, an emitter region 552, a first lightly doped region 561, a second lightly doped region 562, an insulating layer 610, a passivation layer 630, a first conductive layer 711, a first lead 721, a second lead 722, a third lead 723, and a fourth lead 724. Wherein, the insulating layer 610 includes: a first insulating layer 611, a second insulating layer 612, and a third insulating layer 613. The substrate 500, the isolation region, the collector region 551, the emitter region 552, the first lightly doped region 561, and the second lightly doped region 562 are of a first doping type, and the buried layer 510, the epitaxial layer 520, and the contact region are of a second doping type, the first doping type being opposite to the second doping type, the first doping type being selected from one of P-type doping and N-type doping, and the second doping type being selected from the other of P-type doping and N-type doping. In the present embodiment, the first doping type is selected from P-type doping, and the second doping type is selected from N-type doping. However, the first embodiment of the invention is not limited thereto, and the first doping type may also be N-type doping, and the second doping type is P-type doping.

A first lightly doped region 561 is located in the epitaxial layer 520 and extends laterally from inside the upper isolation region 532 into the epitaxial layer 520, the first lightly doped region 561 exceeds the upper isolation region 532 by a first predetermined length L1, a second lightly doped region 562 is located in the epitaxial layer 520 and extends laterally from inside the base region 551 into the epitaxial layer 520, the second lightly doped region 562 exceeds the base region 551 by a second predetermined length L2, and the range of the first predetermined length L1 includes: the second predetermined length L2 is in a range of 0.3 to 1.5 times the thickness of the epitaxial layer 520 and includes: collector 551 or emitter 552 are 0.3 to 2 times deeper than the junction depth.

The first conductive layer 711 is located over the first lightly doped region 561. The first conductive layer 711 forms a zigzag structure on the surface of the second insulating layer 612. In the cross-sectional view of fig. 10, the first conductive layer 711 is located above the first lightly doped region 561 and laterally exceeds the first lightly doped region 561 by a third predetermined length L3, where the third predetermined length L3 includes: the junction depth of the first lightly doped region is 0.2 to 2 times.

The structure and manufacturing method of the lateral PNP device of the second embodiment of the present disclosure are similar to those of the NPN device of the first embodiment, and are not repeated herein, but differ from the first embodiment in that in the lateral PNP device of the second embodiment, the collector region 551 surrounds the emitter region 552, the second lightly doped region is not provided with the second conductive layer around it, the first lead 721 is connected to the first lightly doped region 561 and the first conductive layer 711 respectively via contact holes and serves as a ground lead of the lateral PNP device, the second lead 722 is connected to the shallow contact region 542 via contact holes and serves as a base of the lateral PNP device, the third lead 723 is connected to the collector region 551 via contact holes and serves as a collector of the lateral PNP device, and the fourth lead 724 is connected to the emitter region 552 via contact holes and serves as an emitter of the lateral PNP device.

Fig. 11 shows a schematic structural diagram of a lateral PNP device according to a third embodiment of the present disclosure.

In the third embodiment, a second conductive layer 712 is further included, and as shown in fig. 11, the second conductive layer 712 is disposed between the third insulating layer 163 and the second insulating layer 162.

According to the lateral PNP device and the method of manufacturing the same of the second or third embodiment of the present invention, the degree of curvature of the depletion line is reduced by the first lightly doped region extending laterally from the inside of the isolation region to the epitaxial layer, the second lightly doped region extending laterally from the inside of the collector region to the epitaxial layer, the degree of curvature of the depletion line is further reduced by the first conductive layer located above the first lightly doped region and extending laterally beyond the first lightly doped region by a certain length, and the second conductive layer located above the second lightly doped region and extending laterally beyond the second lightly doped region by a predetermined length, and by controlling the thicknesses of the first conductive layer and the second conductive layer, controlling the extent of the lateral extent of the first conductive layer beyond the first lightly doped region and the lateral extent of the second conductive layer beyond the second lightly doped region, thereby further reducing the degree of curvature of the depletion line termination (e.g., a location near the isolation region and the upper surface of the epitaxial layer), the length of the depletion boundary, namely the length of the depletion line, is prolonged, the concentration degree of an electric field is reduced, and the purpose of improving the withstand voltage degree of the lateral PNP device is further achieved.

In some specific embodiments, when the lateral PNP device of the integrated circuit is suspended in the emitter region, the breakdown voltage Vcs of the collector region to the substrate is increased to be about 200-260V; when the emitter region is suspended, the breakdown voltage Vbs of the base region to the substrate is increased to be about 200V to 260V.

It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

While embodiments in accordance with the invention have been described above, these embodiments are not intended to be exhaustive or to limit the invention to the precise embodiments described. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best utilize the invention and various embodiments with various modifications as are suited to the particular use contemplated.