阅读说明：本技术 一种适用于5g-nr的并行交织器、解交织器以及方法 (Parallel interleaver, deinterleaver and method suitable for 5G-NR ) 是由 陈红艳 马上 迟博恩 龙凯 于 2020-06-10 设计创作，主要内容包括：本发明涉及5G-NR数据处理领域,具体涉及一种适用于5G-NR的并行交织器、解交织器以及方法。本发明通过每个处理时钟从输入端口中输入多个数据,从输出端口中输出多个数据,使交织器/解交织器内部在每个时钟内能够同时能处理从端口输入的多个数据,即通过提高交织器/解交织器内部数据处理的并行度,从而提高数据的吞吐量,降低处理延迟。且本发明适用于5G-NR中物理信道中使用LDPC信道编码方式的解交织或交织数据处理流程。(The invention relates to the field of 5G-NR data processing, in particular to a parallel interleaver, a deinterleaver and a method suitable for 5G-NR. The invention inputs a plurality of data from the input port through each processing clock and outputs a plurality of data from the output port, so that the plurality of data input from the port can be simultaneously processed in each clock in the interleaver/deinterleaver, namely, the data processing parallelism in the interleaver/deinterleaver is improved, thereby improving the data throughput and reducing the processing delay. The invention is suitable for the de-interleaving or interleaving data processing flow using the LDPC channel coding mode in the physical channel in the 5G-NR.)

1. A parallel interleaver adapted for 5G-NR, characterized by: the device comprises at least two bit interleaving modules, a ping-pong controller, an input channel switching module and an output channel switching module;

each bit interleaving module is respectively connected between the input channel switching module and the output channel switching module and is used for carrying out bit interleaving processing on input parallel data, the parallelism of the parallel data is p, and p is any parallelism;

the input channel switching module and the output channel switching module are respectively connected with the ping-pong controller and are used for switching the bit interleaving module for data transmission;

the ping-pong controller is respectively connected with each bit interleaving module and is used for controlling the working state of the bit interleaving modules and the switching of the input channel and the output channel, so that when one bit interleaving module receives parallel data, the other bit interleaving module outputs the parallel data, and the alternate control is realized.

2. The parallel interleaver of claim 1, wherein: the bit interleaving module comprises a matrix construction unit and a read-write buffer;

the matrix construction unit comprises at least 8 independent RAM memories for constructing a virtual matrix to store the parallel data;

the read-write buffer comprises at least 8 registers for accommodating parallel bus data for adjusting the parallel data written into the virtual matrix or adjusting the parallel data read from the virtual matrix.

3. The parallel interleaver of claim 2, wherein: the bit interleaving module does not comprise a read-write buffer, and the read-write buffer is arranged behind the output channel switching module.

4. The parallel interleaver of claim 2, wherein: the number of rows of a virtual memory constructed by the RAM memory of the matrix construction unit is the same as the modulation order.

5. A deinterleaver adapted for 5G-NR, characterized by: the device comprises at least two de-interleaving modules, a ping-pong controller, an input channel switching module and an output channel switching module;

each de-interleaving module is respectively connected between the input channel switching module and the output channel switching module and is used for de-interleaving input parallel data, the parallelism of the parallel data is p, and p is any parallelism;

the input channel switching module and the output channel switching module are respectively connected with the ping-pong controller and are used for switching the de-interleaving module for data transmission;

the ping-pong controller is respectively connected with each de-interleaving module and is used for controlling the working state of the de-interleaving modules and the switching of the input channel and the output channel, so that when one de-interleaving module receives parallel data, the other de-interleaving module outputs the parallel data, and the alternate control is realized.

6. The deinterleaver according to claim 5, wherein: the de-interleaving module comprises a matrix construction unit and a read-write buffer;

the matrix construction unit comprises at least 8 independent RAM memories for constructing a virtual matrix to store the parallel data;

the read-write buffer comprises at least 8 registers for accommodating parallel bus data for adjusting the parallel data written into the virtual matrix or adjusting the parallel data read from the virtual matrix.

7. The deinterleaver according to claim 6, wherein: the de-interleaving module does not comprise a read-write buffer, a read-write buffer is arranged in front of the input channel switching module, and a bit splicing module is arranged behind the output channel switching module; the bit splicing module is used for eliminating invalid bytes in each data and splicing the valid parts to form new p-byte data.

8. A parallel interleaving method suitable for 5G-NR, comprising the steps of:

s1001: loading parallel data to be processed, wherein the parallelism of the parallel data is p, and p is any parallelism;

s1002: selecting a working interleaver by adopting a ping-pong control method;

s1003: performing interleaving processing on the parallel data and outputting the interleaved parallel data;

the ping-pong control method comprises the following steps:

detecting the storage state of the interleaver A; when A is not fully stored, switching an input channel to the interleaver A and switching an output channel to the interleaver B; and when the memory A is full, switching an input channel to the interleaver B and switching an output channel to the interleaver A.

9. The parallel interleaving method according to claim 8, wherein: the interleaver comprises at least 8 independent RAM memories for building a virtual matrix.

10. A deinterleaving method for 5G-NR, comprising the steps of:

s2001: loading parallel data to be processed, wherein the parallelism of the parallel data is p, and p is any parallelism;

s2002: selecting a working de-interleaver by adopting a ping-pong control method;

s2003: de-interleaving the parallel data and outputting the de-interleaved parallel data;

the ping-pong control method comprises the following steps:

detecting the storage state of the deinterleaver A; when the deinterleaver A is not full, switching an input channel to the deinterleaver A and switching an output channel to a deinterleaver B; and when the deinterleaver A is full, switching an input channel to the deinterleaver B and switching an output channel to the deinterleaver A.

Technical Field

The invention relates to the field of interleaving and deinterleaving, in particular to a parallel interleaver, a deinterleaver and a method suitable for 5G-NR.

Background

The revolution in mobile communication technology has injected a strong impetus for economic development in developed and developing countries. Compared with a third generation mobile communication (3G) system, the fourth generation mobile communication (4G) greatly improves the network bandwidth and promotes the rapid development of part of industries. Technological advances and corresponding user needs continue to push innovation, shortening the cycle from development to production to sales of advanced communication applications. Meanwhile, with the steady development of economy, the physical living standard of people is correspondingly improved, and smart phones, tablet computers and innovative mobile applications developed for users are rapidly popularized, so that the mobile data flow is continuously increased. The rapid popularization of mobile equipment, a new market field is developed through a wireless communication technology, the development of digital economy (such as a smart grid, electronic medical treatment, an intelligent transportation system, traffic management and the like) is promoted, and the current mobile communication system cannot meet the development requirements; in order to realize the vision of people for better life while the living standard of matter is improved, and under the condition that science and technology is approved, the fifth generation mobile communication technology (5G) is produced.

5G has numerous application scenarios. In these application scenarios, a significant portion of the applications have stringent requirements on bandwidth and latency. Due to the characteristics of the architecture of the general processor, the manner of performing data processing according to the instruction, the influence of scheduling and terminals on data processing, and the like, the general processing platform cannot guarantee stable delay, and thus the general processing platform cannot be applied to applications with strict delay requirements. In addition, most general hardware processing platform data input/output interfaces can only provide limited bandwidth, and cannot provide enough bandwidth for data processing. A small part of general data processing platforms can provide enough bandwidth, but the performance is poor in the aspects of cost performance and energy efficiency, and a large amount of deployment cannot be achieved. The 5GNR key performance indexes indicate that the downlink peak rate reaches 20Gbps, and the uplink peak rate reaches 10Gbps, which is 20 times higher than that of the previous generation mobile communication system. For URLLC application scenarios, the latency is reduced to 1/20 for the previous generation mobile communication systems. The great improvement of the 5G key index performance brings new challenges to the data processing of the physical layer of the 5G network. The interleaving/deinterleaving operation of the physical shared channel affects the throughput and data processing delay of the data processing of the physical layer to some extent. In order to meet various service requirements of the 5G mobile communication system, a technology for processing interleaving/deinterleaving data in a physical shared channel is urgently needed.

The existing interleaving/de-interleaving technology generally has the problem of low throughput, most of the existing interleaving/de-interleaving technologies adopt an interleaving/de-interleaving mode of passing input, the mode cannot perform parallel operation and has low throughput, and the parallel reading of the existing interleaving/de-interleaving technologies is not high enough and the throughput is still very low due to a small number of parallel interleaving/de-interleaving methods. There is a need for an interleaving/deinterleaving technique with greater throughput.

Disclosure of Invention

The invention aims to: aiming at the problems of low throughput and low efficiency of the existing interleaving/de-interleaving technology, the parallel interleaver, the de-interleaver and the method which are suitable for 5G-NR are provided.

In order to achieve the purpose, the invention adopts the technical scheme that:

a parallel interleaver suitable for 5G-NR comprises at least two bit interleaving modules, a ping-pong controller, an input channel switching module and an output channel switching module;

each bit interleaving module is respectively connected between the input channel switching module and the output channel switching module and is used for carrying out bit interleaving processing on input parallel data, the parallelism of the parallel data is p, and p is any parallelism;

the input channel switching module and the output channel switching module are respectively connected with the ping-pong controller and are used for switching the bit interleaving module for data transmission;

the ping-pong controller is respectively connected with each bit interleaving module and is used for controlling the working state of the bit interleaving modules and the switching of the input channel and the output channel, so that when one bit interleaving module receives parallel data, the other bit interleaving module outputs the parallel data, and the alternate control is realized. The invention improves the parallelism of data input and output, adopts the form of ping-pong control to carry out stream processing on data, inputs or outputs a plurality of data by each clock, can be approximately regarded as the processing of full-flow water because the clock consumed by ping-pong operation control logic occupies a small part, and improves the parallelism and obviously improves the throughput compared with the traditional serial.

As a preferred scheme of the present invention, the bit interleaving module includes a matrix construction unit and a read-write buffer;

the matrix construction unit comprises at least 8 independent RAM memories for constructing a virtual matrix to store the parallel data;

the read-write buffer comprises at least 8 registers for accommodating parallel bus data for adjusting the parallel data written into the virtual matrix or adjusting the parallel data read from the virtual matrix.

As a preferred scheme of the present invention, the bit interleaving module does not include a read-write buffer, and a read-write buffer is disposed behind the output channel switching module. The invention takes out the read-write buffer module in the bit interleaving module and puts the read-write buffer module behind the output channel switching module, and the two virtual matrixes share the read-write buffer. The structure of the whole device is simplified, and resources are saved.

As a preferred embodiment of the present invention, the number of virtual memory rows constructed by the RAM memory of the matrix construction unit is the same as the modulation order.

A de-interleaver suitable for 5G-NR comprises at least two de-interleaving modules, a ping-pong controller, an input channel switching module and an output channel switching module;

each de-interleaving module is respectively connected between the input channel switching module and the output channel switching module and is used for de-interleaving input parallel data, the parallelism of the parallel data is p, and p is any parallelism;

the input channel switching module and the output channel switching module are respectively connected with the ping-pong controller and are used for switching the de-interleaving module for data transmission;

the ping-pong controller is respectively connected with each de-interleaving module and is used for controlling the working state of the de-interleaving modules and the switching of the input channel and the output channel, so that when one de-interleaving module receives parallel data, the other de-interleaving module outputs the parallel data, and the alternate control is realized.

As a preferred scheme of the present invention, the de-interleaving module includes a matrix construction unit and a read-write buffer;

the matrix construction unit comprises at least 8 independent RAM memories for constructing a virtual matrix to store the parallel data;

the read-write buffer comprises at least 8 registers for accommodating parallel bus data for adjusting the parallel data written into the virtual matrix or adjusting the parallel data read from the virtual matrix.

As a preferred scheme of the present invention, the de-interleaving module does not include a read-write buffer, a read-write buffer is arranged in front of the input channel switching module, and a bit splicing module is arranged behind the output channel switching module; the bit splicing module is used for removing invalid bytes in each data, splicing the valid parts to form new p-byte data, and is also called Packing operation in the AXIS bus protocol. The invention greatly optimizes the processing process and avoids the interference of invalid bytes by arranging the bit splicing module behind the output channel switching module of the de-interleaver.

A parallel interleaving method suitable for 5G-NR, comprising the steps of:

s1001: loading parallel data to be processed, wherein the parallelism of the parallel data is p, and p is any parallelism;

s1002: selecting a working interleaver by adopting a ping-pong control method;

s1003: performing interleaving processing on the parallel data and outputting the interleaved parallel data;

the ping-pong control method comprises the following steps:

detecting the storage state of the interleaver A; when A is not fully stored, switching an input channel to the interleaver A and switching an output channel to the interleaver B; and when the memory A is full, switching an input channel to the interleaver B and switching an output channel to the interleaver A.

As a preferred aspect of the present invention, the interleaver includes at least 8 independent RAM memories for constructing the virtual matrix.

A deinterleaving method for 5G-NR, comprising the steps of:

s2001: loading parallel data to be processed, wherein the parallelism of the parallel data is p, and p is more than or equal to 16;

s2002: selecting a working de-interleaver by adopting a ping-pong control method;

s2003: de-interleaving the parallel data and outputting the de-interleaved parallel data;

the ping-pong control method comprises the following steps:

detecting the storage state of the deinterleaver A; when the deinterleaver A is not full, switching an input channel to the deinterleaver A and switching an output channel to a deinterleaver B; and when the deinterleaver A is full, switching an input channel to the deinterleaver B and switching an output channel to the deinterleaver A.

In summary, due to the adoption of the technical scheme, the invention has the beneficial effects that:

1. the invention improves the parallelism of data input and output, adopts the form of ping-pong control to carry out stream processing on data, inputs or outputs a plurality of data by each clock, can be approximately regarded as the processing of full-flow water because the clock consumed by ping-pong operation control logic occupies a small part, and improves the parallelism and obviously improves the throughput compared with the traditional serial.

2. The invention takes out the read-write buffer module in the bit interleaving module and puts the read-write buffer module behind the output channel switching module, and the two virtual matrixes share the read-write buffer. The structure of the whole device is simplified, and resources are saved.

3. The invention sets a bit splicing module behind the output channel switching module of the de-interleaver. And eliminating invalid bytes in each data, and splicing the valid parts to form new p-byte data. The processing process is greatly optimized, and the influence of invalid bytes on the throughput of the bus is avoided.

Drawings

FIG. 1 is an interleaving schematic of the present invention;

FIG. 2 is a diagram of the first two data at the input during interleaving according to the present invention;

FIG. 3 is a diagram illustrating the data numbering at the output end during interleaving according to the present invention;

FIG. 4 is a diagram of the first two data at the output during interleaving according to the present invention;

FIG. 5 is a diagram of the deinterleaving scheme of the present invention;

FIG. 6 is a diagram of the first two data at the input during interleaving according to the present invention;

FIG. 7 is a diagram illustrating the data numbering at the output end during interleaving according to the present invention;

FIG. 8 is a diagram of the first two data at the output during interleaving according to the present invention;

fig. 9 is a schematic structural diagram of a bit interleaver suitable for 5G-NR according to embodiment 1 of the present invention;

fig. 10 is a schematic structural diagram of a bit interleaving module of a bit interleaver suitable for 5G-NR according to embodiment 1 of the present invention;

fig. 11 is a schematic data transmission diagram of a bit interleaving module of a bit interleaver suitable for 5G-NR according to embodiment 1 of the present invention;

FIG. 12 shows Q in a bit interleaver for 5G-NR according to embodiment 2 of the present invention_mA schematic diagram of parallel data stored in the 8-th register # 0;

FIG. 13 shows Q in a bit interleaver for 5G-NR according to embodiment 2 of the present invention_mA schematic diagram of parallel data stored in register # 0 when 2;

FIG. 14 shows Q in a bit interleaver for 5G-NR according to embodiment 2 of the present invention_mA schematic diagram of parallel data stored in the register # 0 when 4;

FIG. 15 shows Q in a bit interleaver for 5G-NR according to embodiment 2 of the present invention_mA schematic diagram of parallel data stored in register No. 0 at 6;

FIG. 16 shows a ratio suitable for 5G-NR according to example 2 of the present inventionQ in special interleaver_mThe arrangement schematic diagram of the RAM memory in the matrix construction module is 2;

FIG. 17 shows Q in a bit interleaver for 5G-NR according to embodiment 2 of the present invention_mThe arrangement schematic diagram of the RAM memory in the matrix construction module is 4;

FIG. 18 shows Q in a bit interleaver for 5G-NR according to embodiment 2 of the present invention_mThe arrangement schematic diagram of the RAM memory in the matrix construction module is 6;

FIG. 19 shows Q in a bit interleaver for 5G-NR according to embodiment 2 of the present invention_mThe arrangement schematic diagram of the RAM memory in the matrix construction module is 8;

fig. 20 is a schematic structural diagram of a bit interleaver for 5G-NR according to embodiment 3 of the present invention;

fig. 21 is a schematic structural diagram of a deinterleaver applied to 5G-NR according to embodiment 4 of the present invention;

FIG. 22 shows a deinterleaver at Q for 5G-NR according to embodiment 5 of the present invention_mWhen the time is 8, the read-write buffer writes data into the virtual matrix;

FIG. 23 shows a deinterleaver at Q for 5G-NR according to embodiment 5 of the present invention_mWhen the time is 2, the read-write buffer writes data into the virtual matrix;

FIG. 24 shows a deinterleaver at Q for 5G-NR according to embodiment 5 of the present invention_mWhen the time is 4, the read-write buffer writes data into the virtual matrix;

FIG. 25 shows a deinterleaver at Q for 5G-NR according to embodiment 5 of the present invention_mWhen the time is 6, the read-write buffer writes data into the virtual matrix;

fig. 26 is a schematic structural diagram of a deinterleaver applied to 5G-NR according to embodiment 6 of the present invention;

fig. 27 is an operation process diagram of a ping-pong control method in a parallel interleaving method for 5G-NR according to embodiment 7 of the present invention;

fig. 28 is an input judgment flowchart of a ping-pong control method in the parallel interleaving method for 5G-NR according to embodiment 7 of the present invention;

fig. 29 is a flowchart of output judgment of a ping-pong control method in a parallel interleaving method applicable to 5G-NR according to embodiment 7 of the present invention;

fig. 30 shows a deinterleaving method suitable for 5G-NR in embodiment 8 of the present invention with a parallelism of p-16, Q_m8, and each data is 1 byte, the writing process of the first data input register is shown schematically;

fig. 31 shows a deinterleaving method suitable for 5G-NR in embodiment 8 of the present invention with a parallelism of p-16, Q_mAnd 8, each data is 1 byte, and the writing process of the last data input register is shown schematically.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings.

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

Bit interleaving is part of rate matching in coding. Data before interleaving is e₀,e₁,e₂,…,e_E-1The deinterleaved data is f₀,f₁,f₂,…,f_E-1Modulation order of Q_mAnd E is the length of the interleaved data, and the operation procedure is as follows:

the bit interleaver writes the LLR data column-by-column into a matrix and then reads the data out of the matrix row-by-row, the schematic diagram of bit interleaving reading and writing is shown in fig. 1.

Assuming that the data range from 0to E-1, the output index starts from 0 and is written into the first row and the second row in sequence until the whole memory matrix is completely filled. Output data from the first columnAt first, 0, E/Q_m,…,(Q_m-1)×E/Q_m,1,E/Q_m+1,…,(Q_m-1)×E/Q_m,E/Q_m-1,…,E-1。

With Q_mAs an example, the parallelism of data input is 32, the first two data of the input end are shown in fig. 2, the data number of the output end is shown in fig. 3 according to the bit interleaving principle, and the numbers of the first two data of the output end at this time are obtained, as shown in fig. 4.

De-interleaving is the inverse of interleaving in encoding. Suppose the data before de-interleaving is e₀,e₁,e₂,…,e_E-1The deinterleaved data is f₀,f₁,f₂,…,f_E-1Modulation order of Q_mAnd E is the length of the deinterleaved data;

assuming that there is one row for the modulation order Q_mThe number of columns is E/Q_mThe matrix stores only one data per cell. The deinterleaver writes LLR data column-by-column into a matrix and then reads data out of the matrix row-by-row.

As shown in FIG. 5 as Q_mThe de-interleaving scheme is 4. The figure shows a matrix with 4 rows and E/4 columns. Assuming that the data range from 0to E-1, the output index starts from 0 and is written into the first column and the second column in sequence until the whole memory matrix is completely filled. The output data is 0,4, …, E-8, E-4,1,5, …, E-7, E-3,2,6, … E-6, E-2,3,7, E-5, E-1 in this order from the first row.

Take p as an example 16. According to the requirement, the input end of the de-interleaving module transmits 16 data at a time, and the 16 data are numbered in sequence, wherein the numbering starts from 0. The deinterleaved output data is output from the first row of the matrix. Suppose the data length to be deinterleaved is greater than 16Q_mI.e. the first 16 data are located in the first row of the matrix. The number sequence of the first 16 data of the deinterleaving output is: index ═ iQ_mFori is 0to 15. Thus obtaining the first16 parallel output data requires at least 15Q_m16 parallel data inputs, i.e. Q_mAnd inputting the parallel data.

When Q is_mWhen the number of the first two data of the input end is 8, the number of the first two data of the output end is shown in fig. 6, and the number of the first two data of the output end at this time is obtained according to the deinterleaving principle, as shown in fig. 8.