阅读说明：本技术 用于三电平降压调节器的电路 (Circuit for three-level buck regulator ) 是由 阿尔贝托·亚历山德罗·安吉洛·普杰利 李敏馥 汉斯·梅瓦特 李志鹏 于 2019-01-11 设计创作，主要内容包括：电感器；第一开关,其具有连接至第一电压源(VS1)的第一端；第二开关,其具有连接至所述第一开关的第二端(2SS1)的第一端,和连接至所述电感器的第一端(1SI)的第二端；第三开关,其具有连接至所述1SI的第一端；第四开关,其具有连接至所述第三开关的第二端(2SS3)的第一端,和连接至第二电压源(VS2)的第二端；第五开关,其具有连接至所述1SI的第一端,和连接至所述VS1和/或所述VS2的第二端；第一电容器,其具有连接至所述2SS1的第一端,和连接至所述2SS3的第二端；以及第二电容器,其具有连接至所述电感器的第二端的第一端,和连接至所述VS2的第二端。(An inductor; a first switch having a first terminal connected to a first voltage source (VS 1); a second switch having a first terminal connected to the second terminal (2SS1) of the first switch, and a second terminal connected to the first terminal (1SI) of the inductor; a third switch having a first terminal connected to the 1 SI; a fourth switch having a first terminal connected to the second terminal (2SS3) of the third switch and a second terminal connected to a second voltage source (VS 2); a fifth switch having a first terminal connected to the 1SI and a second terminal connected to the VS1 and/or the VS 2; a first capacitor having a first terminal connected to the 2SS1, and a second terminal connected to the 2SS 3; and a second capacitor having a first terminal connected to the second terminal of the inductor, and a second terminal connected to the VS 2.)

1. A circuit for a three-level buck regulator, comprising:

an inductor having a first end and having a second end;

a first switch having a first terminal connected to a first voltage source and having a second terminal;

a second switch having a first end connected to the second end of the first switch and having a second end connected to the first end of the inductor.

A third switch having a first end connected to the first end of the inductor and having a second end;

a fourth switch having a first terminal connected to the second terminal of the third switch and having a second terminal connected to a second voltage source;

a fifth switch having a first end connected to the first end of the inductor and having a second end connected to one of the first and second voltage sources;

a first capacitor having a first terminal connected to the second terminal of the first switch and having a second terminal connected to the second terminal of the third switch; and

a second capacitor having a first terminal connected to the second terminal of the inductor and having a second terminal connected to the second voltage source.

2. The circuit of claim 1, wherein a second terminal of the fifth switch is connected to the second voltage source, further comprising:

a sixth switch having a first terminal connected to the first terminal of the inductor and having a second terminal connected to the first voltage source.

3. The circuit of claim 1, wherein a second terminal of the fifth switch is connected to the second voltage source, and wherein in state 0 of the regulator:

the first switch is opened;

the second switch is opened;

the third switch is closed;

the fourth switch is closed; and is

The fifth switch is closed.

4. The circuit of claim 3, wherein in state 1 of the regulator:

the first switch is opened;

the second switch is closed;

the third switch is open;

the fourth switch is closed; and is

The fifth switch is open.

5. The circuit of claim 4, wherein in state 2 of the regulator:

the first switch is closed;

the second switch is opened;

the third switch is closed;

the fourth switch is opened; and is

The fifth switch is open.

6. The circuit of claim 5, wherein the regulator switches between state 0, state 1, and state 2 during a cycle of the regulator.

7. The circuit of claim 1, wherein a second terminal of the fifth switch is connected to the second voltage source, and wherein in state 3 of the regulator:

the first switch is closed;

the second switch is closed;

the third switch is open;

the fourth switch is opened; and is

The fifth switch is closed.

8. The circuit of claim 7, wherein in state 1 of the regulator:

the first switch is opened;

the second switch is closed;

the third switch is open;

the fourth switch is closed; and is

The fifth switch is open.

9. The circuit of claim 8, wherein in state 2 of the regulator:

the first switch is closed;

the second switch is opened;

the third switch is closed;

the fourth switch is opened; and is

The fifth switch is open.

10. The circuit of claim 9, wherein the regulator switches between state 3, state 1, and state 2 during a cycle of the regulator.

11. The circuit of claim 1, wherein a second end of the inductor is coupled to a load.

Background

Voltage regulators are ubiquitous circuit components that are critical to providing stable power to a circuit load. Buck regulators constitute a class of voltage regulators that are popular in certain applications. However, buck regulators may be inefficient due to parasitic resistances in these regulators.

Therefore, new circuits for voltage regulators are needed.

Disclosure of Invention

A circuit for a three-level buck regulator is provided. In some embodiments, the circuit comprises: an inductor having a first end and having a second end; a first switch having a first terminal connected to a first voltage source and having a second terminal; a second switch having a first end connected to the second end of the first switch and having a second end connected to the first end of the inductor; a third switch having a first end connected to the first end of the inductor and having a second end; a fourth switch having a first terminal connected to the second terminal of the third switch and having a second terminal connected to a second voltage source; a fifth switch having a first end connected to the first end of the inductor and having a second end connected to one of the first and second voltage sources; a first capacitor having a first terminal connected to the second terminal of the first switch and having a second terminal connected to the second terminal of the third switch; and a second capacitor having a first terminal connected to the second terminal of the inductor and having a second terminal connected to the second voltage source.

In some embodiments, the second terminal of the fifth switch is connected to the second voltage source, and the circuit further comprises: a sixth switch having a first terminal connected to the first terminal of the inductor and having a second terminal connected to the first voltage source.

In some embodiments, a second terminal of the fifth switch is connected to the second voltage source, and wherein in state 0 of the regulator: the first switch is opened; the second switch is opened; the third switch is closed; the fourth switch is closed; and the fifth switch is closed. In some such embodiments, in state 1 of the regulator: the first switch is opened; the second switch is closed; the third switch is open; the fourth switch is closed; and the fifth switch is open. Further, in some such embodiments, in state 2 of the regulator: the first switch is closed; the second switch is opened; the third switch is closed; the fourth switch is opened; and the fifth switch is open. Still further, in some such embodiments, the regulator switches between state 0, state 1, and state 2 during cycling of the regulator.

In some embodiments, a second terminal of the fifth switch is connected to the second voltage source, and wherein in state 3 of the regulator: the first switch is closed; the second switch is closed; the third switch is open; the fourth switch is opened; and the fifth switch is closed. In some such embodiments, in state 1 of the regulator: the first switch is opened; the second switch is closed; the third switch is open; the fourth switch is closed; and the fifth switch is open. Further, in some such embodiments, in state 2 of the regulator: the first switch is closed; the second switch is opened; the third switch is closed; the fourth switch is opened; and the fifth switch is turned on. Still further, in some such embodiments, the regulator switches between state 3, state 1, and state 2 during a cycle of the regulator.

In some embodiments, the second end of the inductor is coupled to a load.

Drawings

Fig. 1A-1B illustrate examples of buck regulators and their operation as known in the prior art.

Fig. 2A-2F illustrate an example of a three-level buck regulator and its operation as known in the prior art.

Figures 3A-3D illustrate examples of a three-level buck regulator including a switch to ground to reduce parasitic resistance and its operation according to some embodiments.

FIGS. 4A-4D illustrate a junction to V to reduce parasitic resistance, according to some embodiments_INAnd an example of the operation thereof.

5A-5F illustrate a switch including ground to reduce parasitic resistance and a ground to V, according to some embodiments_INAnd an example of the operation thereof.

Detailed Description

1A-1B illustrate an example 100 of a buck regulator and its operation as known in the prior art. As shown in fig. 1A, buck regulator 100 includes an inductor 108, two switches 114 and 116, and a capacitor 120. The buck regulator drives a load 106.

During operation, buck regulator 100 connects inductor 108 to first voltage source V through switches 114 and 116_IN104 and a second voltage source 118. In some cases, it is assumed for simplicity only for the remainder of this application that the second voltage source 118 is a ground voltage (0V) source. Switches 114 and 116 are turned on and off using control signals from any suitable control mechanism, such as a hardware processor. Switches 114 and 116 are controlled so that the two switches do not turn on at the same time. Switches 114 and 116 may be implemented as transistors, such as MOSFET transistors. For example, switch 114 may be implemented with a P-channel MOSFET transistor, and switch 116 may be implemented with an N-channel MOSFET transistor.

When switches 114 and 116 are on, as shown in FIG. 1BVoltage V at the left end (input) of inductor 108 when switched on and off during period T_X102 at 0V (ground) and V during the period T_INAnd swings. More specifically, between time 0 and time DT, and between time T and T + DT, switch 114 is closed and switch 116 is open. This will result in V_X102 is equal to V_IN104. Between time DT and time T, and between time T + DT and time 2T, switch 114 is open and switch 116 is closed. This results in V_X102 is equal to ground. Inductor 108 and capacitor 120 act to average V over time_X102 operate to produce a signal V at the regulator output with low voltage ripple_OUT110。V_OUT110 may be dependent on the connection of inductor 108 to first voltage source V_IN104 and the amount of time that inductor 108 is connected to second voltage source 118. For example, buck regulator 100 may adjust V_OUT110 level so that it is equal to V_IND + (0V) (1-D), where D is a number between 0 and 1, and is also V_XIs coupled to V_INPart of the time of (c). D is also referred to as the duty cycle. The output load 106, which consumes the output current, may be any type of electronic device, including a hardware processor, memory (DRAM, NAND, flash, etc.), RF chip, WiFi combo chip, and power amplifier.

The efficiency of buck regulator 100 can be calculated as:

wherein, P_LRepresents the power delivered to the output load 106, and P_IRepresenting the input power to the buck regulator 108. P_LIt can be calculated as follows: p_L＝P_I-P_LOSSIn which P is_LOSSIncluding the amount of power lost during voltage regulation.

The primary power loss P associated with buck regulator 100_LOSSIncludes a resistive loss P caused by parasitic resistance of inductor 108_R. When the buck regulator 100 is providing the current I_L112 will transfer powerWhen delivered to the output load 106, the buck regulator 100 ideally provides all of the power it receives at the input (input power) to the output load 106 as output power. In practice, however, buck regulator 100 dissipates some of its input power within inductor 108. Ideally, inductor 108 has zero resistance. Thus, the current through inductor 108 does not dissipate any power. However, in practice, inductor 108 is associated with a finite resistance, primarily due to the resistance of the material forming inductor 108. This undesirably finite resistance of inductor 108 is referred to as parasitic resistance. Parasitic resistance can cause resistive power losses because parasitic resistance can cause energy to be dissipated by the current through inductor 108. Thus, resistive power losses may reduce the power conversion efficiency of buck regulator 100.

When the current is ac, then the resistive power loss can be calculated as P_L＝I_L,RMS ²R_LWherein R is_LIs the value of the parasitic resistance of inductor 108, and I_L,RMSIs the root mean square of the current through inductor 108. By reducing inductor current (I)_L,PP120) Peak-to-peak ripple of_L,RMS. Therefore, buck regulator 100 may reduce inductor current I_L,PP120 peak-to-peak ripple to reduce resistive loss P_R。

There are two ways to reduce the inductor current I_L,PPPeak-to-peak ripple. First, buck regulator 100 can switch to high frequencies and reduce the period T of the switching regulator. However, this solution may increase the power consumed by charging and discharging the parasitic capacitance at the junction 122 between the switches 114 and 116. This capacitive power loss may be significant because the size of switches 114 and 116 may be large, which increases parasitic capacitance, and because V_XThe voltage swing on 102 is large. The capacitive power loss can be calculated as follows: p_L＝fCV²Where C is the amount of parasitic capacitance at node 122, f is the switching frequency of buck regulator 100, and V is the voltage swing at node 122. This power loss may be significant because of the large size of switches 114 and 116This increases the parasitic capacitance, and because of V_XThe voltage swing on 102 is large.

Second, the buck regulator 100 may use a high inductance inductor 108 to reduce the parasitic resistance R_L. However, this approach can make inductor 108 large, making integration difficult.

Fig. 2A-2F illustrate an example 200 of a three-level buck regulator and its operation as known in the prior art. At high level, regulator 200 is 2: 1 switched capacitor regulator followed by an inductor. As described in connection with FIGS. 1A-1B, the buck regulator is at V_X102 have values of 0 and V_IN104, which are two voltage levels. However, a three level buck regulator may have 0, V_IN/2 or V_X102V_INAnd/2, hence the name "three" level buck regulator.

When the duty ratio "D" is less than 0.5, V is shown in FIG. 2E_X102 from 0 to V_IN/2 to swing so as to drive V_OUT110 are adjusted to 0 to V_INA value between/2. More specifically, as shown in FIG. 2E, between time 0 and time (0.5-D) T and between time 0.5T and time (1-D) T, regulator 200 operates in state 0 as shown in FIG. 2A. In this state, switches 202 and 204 are open and switches 206 and 208 are closed. Between time (0.5-D) T and time 0.5T, regulator 200 operates in State 1 as shown in FIG. 2B. In this state, switches 202 and 207 are open, and switches 204 and 208 are closed. Between time (1-D) T and time T, regulator 200 operates in State 2 as shown in FIG. 2C. In this state, switches 204 and 208 are open and switches 202 and 206 are closed.

When D is greater than or equal to 0.5, V is_X102 at V_INV and 2_IN104 to swing V_OUT110 is adjusted to V_INV and 2_INA value in between. More specifically, as shown in FIG. 2F, between time 0 and time (D-0.5) T and between time 0.5T and time DT, regulator 200 operates in State 3 as shown in FIG. 2D. In this state, switches 206 and 208 are open and switches 202 and 204 are closed. At time (D-0.5) T andbetween 0.5T, the regulator 200 operates in state 1 as shown in fig. 2B. In this state, switches 202 and 207 are open, and switches 204 and 208 are closed. Between time DT and time T, regulator 200 operates in state 2 as shown in fig. 2C. In this state, switches 204 and 208 are open and switches 202 and 206 are closed.

As shown in FIGS. 1A-1B, V is not considered a value of D between 0 and 1_XThe voltage swing on 102 is V_INV of a two-level buck regulator_XV of_INHalf of the swing. Due to V_XThe voltage swing on is half, so the peak-to-peak inductor current ripple I_L112 is also one half. Thus, a three-level buck regulator may have a smaller I on the inductor_L,RMS ²Loss, or for the same I_L,RMS ²The losses may use a smaller inductance value than the buck regulator.

Three-level buck regulator using C_FLY210 to generate a third level V_IN/2. State 1 and state 2 are compared to typical 2: the 1SC regulator is the same, so the iteration between these two states will be at V_XGo to generate V_IN/2。

One drawback of three-level buck regulators is that the switches (e.g., switches 206 and 208 in fig. 2A, and switches 202 and 204 in fig. 2D) are cascaded in series, which results in a larger I due to parasitic resistance across the switches²And R is lost. In state 0, switches 206 and 208 are connected in series, while in state 3, switches 202 and 204 are connected in series.

3A-3D illustrate an example 300 of a three-level buck regulator, according to some embodiments, at ground (0V) (or any other suitable second voltage source) and V_X102 to reduce the resistance when the switches 206 and 208 are cascaded as shown in figure 3A. More specifically, as shown in fig. 3A and 3D, when D is less than 0.5, the ground and V can be reduced using switch 302 in state 0_X102, the parasitic resistance between them. Switch 302 is only used when D is less than 0.5 and regulator 300 is in state 0. When D is greater than or equal to 0.5, the three-level buck regulator 300 can operate (as will be seen in fig. 2B, 2C, 2D, and 2F)The illustrated regulator 200 operates similarly), but the switch 302 is always off and does not provide any advantage over the typical three level buck regulator shown in fig. 2A-2F.

4A-4D illustrate an example 400 of a three-level buck regulator, at V, according to some embodiments_X102 and V_IN104 to reduce the resistance when switches 202 and 204 are cascaded as shown in fig. 4C. More specifically, as shown in FIGS. 4C and 4D, when D is greater than or equal to 0.5, V may be lowered using switch 404 in State 3_X102 and V_IN104 between the electrodes. Switch 404 is only used when D is greater than or equal to 0.5 and regulator 400 is in state 3. When D is less than 0.5, the three-level buck regulator 400 can operate (which operates similarly to the regulator 200 shown in fig. 2A, 2B, 2C, and 2E), but the switch 404 is always off and does not provide any advantage over the typical three-level buck regulator shown in fig. 2A-2F.

5A-5F illustrate an example 500 of a three-stage buck regulator, according to some embodiments, at ground (0V) (or any other suitable second voltage source) and V_X102 to reduce the resistance in the cascade of switches 206 and 208 as shown in figure 5A, and at V_X102 and V_IN104 to reduce the resistance when switches 202 and 204 are cascaded as shown in figure 5D. More specifically, as shown in FIGS. 5A and 5E, when D is less than 0.5, V may be decreased using the 302 switch in State 0_X102 and ground. The switch 302 is only used when D is less than 0.5 and the regulator 500 is in state 0. As shown in FIGS. 5D and 5F, when D is greater than or equal to 0.5, V may be lowered using switch 404 in State 3_X102 and V_IN104 between the electrodes. Switch 404 is only used when D is greater than or equal to 0.5 and regulator 500 is in state 3. When the regulator 500 is in state 1 or state 2, both switches 302 and 404 are off.

In some embodiments, switches 302 and 404 may be rated as V_IN/2, since the maximum voltage across the switch is V_IN/2. This ratio is rated at V_IN104 is preferably a switchSince the size and resistance of the switch increases with increasing voltage rating.

While the invention has been described and illustrated in the foregoing illustrative embodiments, it is to be understood that the present disclosure is by way of example only and that numerous changes in the details of implementation of the invention may be made without departing from the spirit and scope of the invention, which is limited only by the claims appended hereto. The features of the disclosed embodiments may be combined and rearranged in various ways.