阅读说明：本技术 可缩短内文交换时间的方法及其半导体装置 (Method for shortening text exchange time and semiconductor device thereof ) 是由 张柏坚 曾志豪 于 2019-02-19 设计创作，主要内容包括：本发明涉及一种可缩短内文交换时间的方法及其半导体装置,该半导体装置包含有至少一中央处理器、一逻辑电路及至少一缓存器,其中该缓存器包含有一个或一个以上的一般缓存器群、一个或一个以上的控制状态缓存器及程序计数缓存器,供利用该逻辑电路直接读写该中央处理器的所有缓存器与至少一内存的内文交换的至少一任务的内文,当需要进行内文交换时,该逻辑电路会暂停中央处理器,将中央处理器的所有任务的内文用DMA技术存放于指定的内存中,并且修改运行顺序的值,然后将预计执行的下一组任务中的内文用DMA技术存回中央处理器中,最后恢复中央处理器执行,如此就可以完成内文交换,而能缩短作业时间,并可提升多任务处理效率。(The invention relates to a method for shortening the context exchange time and a semiconductor device thereof, the semiconductor device comprises at least a central processing unit, a logic circuit and at least a buffer, wherein the buffer comprises one or more than one general buffer group, one or more than one control state buffer and a program counting buffer, for utilizing the logic circuit to directly read and write the context of at least one task of the context exchange between all the buffers of the central processing unit and at least one memory, when the context exchange is needed, the logic circuit can suspend the central processing unit, store the context of all the tasks of the central processing unit in the appointed memory by using the DMA technology, and modify the value of the operation sequence, then store the context in the next group of tasks expected to be executed back to the central processing unit by using the DMA technology, and finally resume the execution of the central processing unit, therefore, the context exchange can be completed, the operation time can be shortened, and the multitasking efficiency can be improved.)

1. A semiconductor device capable of shortening a context exchange time, comprising: the semiconductor device comprises at least one central processing unit and a logic circuit, wherein the logic circuit is used for directly reading and writing the central processing unit and exchanging task information of a plurality of tasks between the central processing unit and at least one memory;

the central processing unit comprises a control unit, a processing unit and a plurality of buffers, wherein the control unit is modified into an instruction capable of executing the logic circuit, and all the buffers are modified into the instruction capable of being accessed by the logic circuit;

the logic circuit is arranged in the semiconductor device, and adopts direct memory access technology, so that the logic circuit can suspend and start the instruction execution of the central processing unit and can read and write all the caches of the central processing unit;

defining an area in the area of the memory for storing the serial numbers, the priority order, the states and the texts of a plurality of task information;

a semiconductor device capable of shortening a text exchange time by shortening an operation time and improving a multitasking efficiency is constituted.

2. The semiconductor device for shortening a context exchange time according to claim 1, wherein: the logic circuit may control the architecture of more than one central processing unit.

3. The semiconductor device for shortening a context exchange time according to claim 1, wherein: the registers include at least one general register group, at least one group control status register, and at least one group program counter register.

4. The semiconductor device for shortening a context exchange time according to claim 1, wherein: the logic circuit includes a switching mask register for the logic circuit to determine whether to perform context switching operation for the corresponding task according to the set context of the switching mask register, and the switching mask register is set and cleared by software.

5. The semiconductor device for shortening a context exchange time according to claim 1, wherein: the logic circuit has a timing circuit for setting the time for performing the context exchange.

6. The semiconductor device for shortening a context exchange time according to claim 1, wherein: the memory may be a dynamic random access memory or may be a static random access memory.

7. A semiconductor device capable of shortening a context exchange time, comprising: the semiconductor device comprises at least one central processing unit, a logic circuit and at least one memory;

the logic circuit directly reads and writes the central processing unit and exchanges task information of a plurality of tasks between the central processing unit and the memory;

the central processing unit comprises a control unit, a processing unit and a plurality of buffers;

wherein the control unit is modified to execute instructions of the logic circuit;

wherein all the registers are modified to be accessible to the logic circuit;

the logic circuit adopts direct memory access technology, can suspend and start the instruction execution of the central processing unit, and can read and write all the buffers of the central processing unit;

wherein the memory has a region for storing the number, priority, status and context of a plurality of task information.

8. A method for shortening a context exchange time of a semiconductor device according to any one of claims 1 to 6, wherein: the method comprises the following steps:

firstly, executing step S101, the logic circuit requests a central processing unit to suspend executing the instruction;

then, step S102 is executed, and the logic circuit reads the context of an original execution task in the cpu: the logic circuit reads the context of the suspended task by DMA technology;

then, step S103 is executed, the logic circuit loads the context of the original execution task from the cache of the central processing unit to a designated address in the memory; the logic circuit loads the task information of the task into a designated address of a memory by a DMA technology and sets and modifies a sequence value of the task;

then, step S104 is executed, the logic circuit captures a context of a task to be executed from a memory; the logic circuit captures the text of the task to be executed by using the DMA technology according to the sequence value of each section task in each memory;

then, step S105 is executed, the logic circuit writes the context of the task to be executed into a central processing unit; the logic circuit further writes the text of the task to be executed into a buffer in the central processing unit by using a DMA technology;

finally, step S106 is executed, and the logic circuit informs the central processing unit to recover the instruction operation;

and repeating and sequentially executing the steps for completing the action of the context exchange of the multitask processing.

9. The method for reducing a context exchange time of claim 8, wherein: in step S103, the logic circuit has a swap mask register, wherein the logic circuit determines whether to perform context swapping according to the context of the swap mask register.

10. The method for reducing a context exchange time of claim 8, wherein: in step S103, the logic circuit is provided with a timing circuit for determining how much time to perform a context exchange.

Technical Field

The present invention relates to a technique for shortening a context exchange time, and more particularly, to a method for shortening a context exchange time by a hardware circuit and a semiconductor device using the same.

Background

The core of a computer is a Central Processing Unit (CPU), which basically receives commands, inputs data, calculates or outputs data, and the like, while early computers mostly have only one CPU, but to process many programs or tasks, the simplest idea is to finish one program or task and then do the next program or task, but this feels that the following programs or tasks are waiting all the time, so some people want to say that the programs or tasks are cut into many pieces, and the CPU processes a part of the programs or tasks each time, which feels that many tasks are processed at the same time, and this is called multitasking. As shown in fig. 1, "time-sharing multitasking" is a method for implementing multitasking, which divides the running time of a CPU into a plurality of segments, each segment executing the Task of a certain program or Task [ Task ], such as Task1, Task2, Task3, Task4 …, and when one of the segments, such as Task1, arrives, it is necessary to store the state of the currently executing Task, referred to as snapshot, and load a snapshot of another Task, such as Task2, for continuing the next Task, such as Task of Task2, and so on;

however, context switching is a method commonly used in the current time-sharing multitasking for storing and loading snapshots, and context switching is to store all registers related to a Task in a currently executing CPU into a memory, and load a next register to be executed with the Task in a memory of another area to achieve the functions of storing and loading snapshots. In many applications, Task needs to be multitasked and high-speed reaction, which is a very important consideration in design, but in order to complete the storage and loading of the snapshot, the software needs to consume hundreds or even thousands of instruction cycles to achieve this function, which may affect the execution performance of the Task.

As shown in fig. 2, if the context exchange time is longer for the same time length, the time that the CPU can spend processing Task is relatively shorter, so the more time spent for the context exchange, the more the multitask performance is deteriorated;

in other words, in most multitasking environments, the task of implementing the context exchange is completed in software, and the task of the software needs hundreds or thousands of instruction cycles of the CPU to complete the task, so that the multitasking efficiency cannot be effectively improved.

Accordingly, the present invention is made in view of the above-mentioned needs and problems, and by means of the experience of the inventor in conducting related development for many years, the inventor has actively sought a solution, and through continuous research and development, has successfully developed a method for shortening the context exchange time and a semiconductor device thereof, which can effectively solve the inconvenience and trouble caused by the failure to effectively shorten the context exchange time.

Disclosure of Invention

Therefore, the present invention is directed to a method for reducing a text exchange time and a semiconductor device thereof, which can reduce the text exchange time by a direct memory access method to be much shorter than the conventional software, thereby improving the execution efficiency of a multitask system.

It is another objective of the claimed invention to provide a method for reducing the context exchange time and a semiconductor device thereof, which can stabilize the multitasking of a computer system and improve the efficiency of the entire computer system.

Therefore, the present invention mainly achieves the above-mentioned objects and effects by the following technical means, wherein the semiconductor device comprises at least a central processing unit and a logic circuit, for directly reading and writing task information of at least one task exchanged by context of the central processing unit and at least one memory by using the logic circuit;

the central processing unit comprises a control unit, a processing unit and a buffer, wherein the buffer comprises one or more than one general buffer group, one or more than one control state buffer and a program counting buffer, the control unit is modified into an instruction capable of executing the logic circuit, and the general buffer group, the control state buffer and the program counting buffer can be modified into a state capable of being accessed by the logic circuit;

the logic circuit is arranged in the semiconductor device, adopts direct memory access technology, can suspend and start the instruction execution of the central processing unit, and can read and write all the buffers of the central processing unit;

defining an area in the area of the memory for storing the serial numbers, the priority order, the states and the texts of a plurality of task information;

therefore, when the context exchange is needed, the logic circuit can suspend the central processing unit, store all the buffers storing the task information of all the tasks in the central processing unit in the appointed memory by using the DMA technology, modify the value of the running priority, then store the contexts in the next group of tasks to be executed back to the buffer of the central processing unit by using the DMA technology, and finally resume the execution of the central processing unit, thereby completing the task, shortening the operation time and improving the multi-task processing efficiency.

Further, the logic circuit may control the architecture of more than one central processing unit.

Further, the registers include at least one general register group, at least one group control status register, and at least one group program count register.

Furthermore, the logic circuit includes a switching mask register for the logic circuit to determine whether to perform a context switching operation for the corresponding task according to the setting context of the switching mask register, and the switching mask register is set and cleared by software.

Further, the logic circuit has a timing circuit for setting the time for performing the context exchange.

Further, the memory may be a dynamic random access memory or may be a static random access memory, a method of reducing a context exchange time of the semiconductor device according to any one of the above embodiments adopts the following scheme:

the method comprises the following steps: firstly, executing step S101, the logic circuit requests a central processing unit to suspend executing the instruction;

then, step S102 is executed, and the logic circuit reads the context of an original execution task in the cpu: the logic circuit reads the context of the suspended task by DMA technology;

then, step S103 is executed, the logic circuit loads the context of the original execution task from the cache of the central processing unit to a designated address in the memory; the logic circuit loads the task information of the task into a designated address of a memory by a DMA technology and sets and modifies a sequence value of the task;

then, step S104 is executed, the logic circuit captures a context of a task to be executed from a memory; the logic circuit captures the text of the task to be executed by using the DMA technology according to the sequence value of each section task in each memory;

then, step S105 is executed, the logic circuit writes the context of the task to be executed into a central processing unit; the logic circuit further writes the text of the task to be executed into a buffer in the central processing unit by using a DMA technology;

finally, step S106 is executed, and the logic circuit informs the central processing unit to recover the instruction operation;

and repeating and sequentially executing the steps for completing the action of the context exchange of the multitask processing.

Further, in step S103, the logic circuit has a swap mask register, wherein the logic circuit determines whether to perform context swap according to the context of the swap mask register.

Further, in step S103, the logic circuit is provided with a timing circuit for determining how much time to perform a context exchange.

Drawings

FIG. 1 is a diagram illustrating a task execution fragment of a conventional processor in multitasking.

FIG. 2 is a timing diagram of a context exchange runtime of a conventional processor in multitasking.

FIG. 3 is a block diagram of a semiconductor device with reduced context exchange time according to the present invention.

FIG. 4 is a flow chart of the method for shortening the text exchange time according to the present invention.

FIG. 5 is a schematic diagram of an operation structure of a semiconductor device capable of reducing the context exchange time in actual operation according to the present invention.

Names corresponding to the marks in the figure: 10. the system comprises a Central Processing Unit (CPU), a control unit (12), a processing unit (14), a processing unit (16), a general buffer group (18), a control state buffer (19), a program counting buffer (20), a logic circuit (21), a switching mask buffer (25), a timing circuit (30), a memory (35) and a system connection bus.

Detailed Description

The accompanying drawings illustrate embodiments of the present invention and components thereof, and all references to front and back, left and right, top and bottom, upper and lower, and horizontal and vertical are only used for convenience of description and do not limit the invention or its components to any position or spatial orientation. The dimensions specified in the figures and description may vary depending on the design and requirements of particular embodiments of the invention without departing from the scope of the claims.

As shown in fig. 3, the semiconductor device includes at least a cpu 10 and a logic circuit 20. The logic circuit 20 directly reads and writes data migration between the cpu 10 and at least one memory 30. In the preferred embodiment, the semiconductor device has two central processing units 10.

Each CPU 10 includes a control unit 12, a processing unit 14, and a register. The register groups include at least one general register group 16, at least one control status register 18, and at least one program counter register 19. The control unit 12 is used for controlling the operations of other units inside the central processing unit 10 and receiving or sending instructions to the outside. The processing unit 14 processes the instructions of the cpu 10 according to the instructions received by the control unit 12. The general register group 16 can be used to store and execute the working status of tasks. The general cache pool 16 is a high-speed storage unit of limited storage capacity that can be used to temporarily store data, addresses, or other operational information. The control status register 18 and the program counter register 19 are used for storing the control and status information of the control unit 12.

The logic circuit 20 (which may be referred to as Context-Changer) is disposed in the semiconductor device, and in some embodiments the logic circuit 20 may operate more than one cpu 10 in the semiconductor device synchronously. Furthermore, the logic circuit 20 adopts a Direct Memory Access (DMA) technology for independently and directly reading and writing and transmitting data between all registers of the cpu 10 and the memories 30, and modifies the control unit 12 of the cpu 10, so that the logic circuit 20 can suspend the instruction execution of the cpu 10 through the control unit 12, and modify the access modes of the general register group 16, the program count register 19, and the control state register 18 of the cpu 10, so that the logic circuit 20 can read and write all registers of the cpu 10. According to some embodiments, the logic circuit 20 includes a swap mask register 21, for the logic circuit 20 to determine whether to perform a context swap operation for a corresponding task according to the context set in the swap mask register 21, the swap mask register 21 is set and cleared by software, if the logic circuit 20 is to perform a context swap operation, if the swap mask register 21 is found to be set, the logic circuit suspends the context swap operation until the swap mask register 21 is cleared, and then the logic circuit 20 performs the context swap operation. According to some embodiments, the logic circuit 20 further comprises a timer circuit 25 for determining how much time to perform a context exchange.

The Memory 30 may be a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM). Each of the memories 30 is connected to the cpu 10 through at least one system connection bus 35. And according to some embodiments, each of the memory 30 and the cpu 10 may be the same semiconductor device. A block area is defined in the memory 30 for storing the Task number [ ID ], Priority, Status and Context [ Context Data ] of the Task information [ Task-Info ].

Thus, a semiconductor device capable of shortening the operating time and reducing the text exchange time while improving the efficiency of multitasking is constructed.

When time-division multiplexing is required, the present invention utilizes the logic circuit 20 of the semiconductor device to perform context exchange of multitasking in the cpu 10 and the memory 30. This method of reducing the context exchange time is shown in FIG. 4.

Referring to fig. 4 and 5, first, in step (S101), the logic circuit requests a cpu to suspend executing instructions: the logic circuit 20 requests the control unit 12 of a cpu 10 to suspend the execution of instructions, so that the cpu 10 stops the execution of the task under execution. The logic circuit 20 can control a plurality of cpus 10 at the same time, but the task information of the same group of tasks can be executed only in one cpu 10 at the same time. After that, the step (S102) is executed.

In step (S102), a logic circuit reads the context of an original execution task in the cpu: the logic circuit 20 reads the context of the suspended task by a direct memory access technique [ DMA technique ], and then executes the step (S103).

In step (S103), a logic circuit loads the context of the original execution task to a specified address in a memory: the logic circuit 20 uses DMA technology to load the context of the task from the registers of the cpu to a specified address in the memory 30, and sets and modifies the values of task number, priority and status in the task information of the task to determine the next execution sequence and time. According to some embodiments, the logic circuit 20 may determine to perform the context switching operation according to the context set by the switch mask register 21. Furthermore, according to some embodiments, the logic circuit 20 further performs the context exchange operation of the corresponding task according to the time set by the timer circuit 25. And according to some embodiments, the logic circuit 20 may also be configured with software to immediately perform a context exchange operation once. After that, the step (S104) is executed.

In step (S104), a logic circuit fetches a context to be executed from a memory: the logic circuit 20 captures the context of the task information of the task to be executed by using the aforementioned DMA technique in the first order according to the order of the task number, priority, and status of each task in each segment in the memory 30, and then executes the step (S105).

In step (S105), a logic circuit writes the context of the task to be executed into a cpu: the logic circuit 20 further writes the context of the task to be executed into the register of the central processing unit 10 by using the DMA technique, and then executes the step (S106).

In step (S106), a logic circuit notifies the cpu to resume instruction execution: the logic circuit 20 further informs the control unit 12 of the cpu 10 to resume the instruction execution after writing the context of the next task to be executed into the register of the cpu 10.

Through the above description, the present invention can utilize the DMA technique of the logic circuit 20 to complete the operations of storing the context of the old task in the cpu 10 and reloading the context of the new task, and continuously loop the steps (S101) to (S106) to complete the operation of the multitask processing, because the time required for the DMA technique of the logic circuit 20 in the form of hardware to move data is much shorter than the time required for the conventional software to move data, the present invention can greatly reduce the time for exchanging contexts to improve the execution efficiency of the multitask system.

In view of the above, it can be understood that the present invention is an excellent creative creation, which effectively solves the problems of the prior art and greatly improves the efficacy, and the same or similar creation or disclosure of products is not found in the same technical field and has an improvement in efficacy, so that the present invention meets the requirements of "novelty" and "advancement" of the invention patent, and the application of the invention patent is legally proposed.