阅读说明：本技术 电子雷管的通信解调电路、电子雷管芯片、电子雷管系统 (Communication demodulation circuit of electronic detonator, electronic detonator chip and electronic detonator system ) 是由 关硕 黄圣专 王昭 于 2020-05-07 设计创作，主要内容包括：本发明实施例提供的一种电子雷管的通信解调电路、电子雷管芯片、电子雷管系统,该通信解调电路包括：第二场效应管、第三场效应管、阻性元件、整流器、数字信号输出单元；所述第二场效应管的第二栅极与所述第三场效应管的第三栅极耦接；所述第二场效应管的第二漏极、第二栅极共同耦接于第一电缆线；所述第二场效应管的第二源极与所述第三场效应管的第三源极共同接地；所述第三场效应管的第三漏极与所述阻性元件的第一端耦接于第一电耦接点；所述阻性元件的第二端与电源VDD耦接；所述第一电耦接点耦接所述数字信号输出单元；本方案在满足电力供应和通信需求的同时,结构简单,成本和功耗低。(The embodiment of the invention provides a communication demodulation circuit of an electronic detonator, an electronic detonator chip and an electronic detonator system, wherein the communication demodulation circuit comprises: the device comprises a second field effect transistor, a third field effect transistor, a resistive element, a rectifier and a digital signal output unit; the second grid electrode of the second field effect transistor is coupled with the third grid electrode of the third field effect transistor; the second drain electrode and the second grid electrode of the second field effect transistor are commonly coupled to the first cable wire; a second source electrode of the second field effect transistor and a third source electrode of the third field effect transistor are grounded together; the third drain of the third field effect transistor and the first end of the resistive element are coupled to a first electrical coupling point; the second end of the resistive element is coupled with a power supply VDD; the first electric coupling contact is coupled with the digital signal output unit; the scheme has the advantages of simple structure, low cost and low power consumption while meeting the requirements of power supply and communication.)

1. A communication demodulation circuit of an electronic detonator is characterized by comprising: the device comprises a second field effect transistor, a third field effect transistor, a resistive element, a rectifier and a digital signal output unit;

the second grid electrode of the second field effect transistor is coupled with the third grid electrode of the third field effect transistor;

the second drain electrode and the second grid electrode of the second field effect transistor are commonly coupled to the first cable wire;

a second source electrode of the second field effect transistor and a third source electrode of the third field effect transistor are grounded together;

the third drain of the third field effect transistor and the first end of the resistive element are coupled to a first electrical coupling point;

the second end of the resistive element is coupled with a power supply VDD; the first electric coupling contact is coupled with the digital signal output unit;

the digital signal output unit is used for outputting a digital logic signal to the detonator control unit according to the voltage of the first electric coupling joint; the detonator control unit is coupled to the output end of the digital signal output unit;

the rectifier is coupled with the first cable wire and the second cable wire and used for outputting direct current to supply power for the communication demodulation circuit.

2. The communication demodulation circuit of claim 1,

the rectifier includes: the diode comprises a first diode, a second diode, a third diode and a fourth diode;

the first diode and the third diode are coupled to a second coupling point in the same direction according to the conducting direction of current;

the second diode and the fourth diode are coupled to a third coupling point in the same direction according to the conducting direction of current;

the first cable wire is coupled to the second coupling point;

the second cable wire is coupled to the third coupling point;

the third diode is coupled with the forward output end of the fourth diode to serve as a power supply output end.

3. The communication demodulation circuit according to claim 1, further comprising: a first field effect transistor;

the first grid electrode of the first field effect transistor is coupled with the power supply VDD;

a first drain electrode of the first field effect transistor is coupled with the first cable line;

the first source electrode of the first field effect transistor is coupled with the second drain electrode and the second grid electrode.

4. The communication demodulation circuit according to claim 3, further comprising: a fifth diode;

the first field effect transistor is coupled with the first cable line through the fifth diode;

the anode of the fifth diode is coupled with the first cable line;

and the cathode of the fifth diode is coupled with the drain electrode of the first field effect transistor.

5. The communication demodulation circuit of claim 1,

the resistive element includes: resistor, MOS resistor, current source.

6. The communication demodulation circuit according to any one of claims 1 to 5,

the digital signal output unit includes: a reverse schmitt trigger, an inverter, or a forward schmitt trigger.

7. An electronic detonator chip, comprising: a detonator control unit, a communication demodulation circuit of an electronic detonator as claimed in any one of claims 1 to 6;

the input end of the detonator control unit is coupled with the output end of the digital signal output unit of the communication regulating circuit.

8. The electronic detonator chip of claim 7 wherein the detonator control unit is further configured to: when the detonator control unit is powered on, the received signals are defaulted to be the signals with the same polarity of the digital signal output unit, then the preset time is delayed, and if the output of the digital signal output unit is always logic high, the output ends of the detonator control received signals and the digital signal output unit are kept the same; otherwise, if the output of the digital signal output unit is always logic low after delaying the preset time, the signal received by the detonator control unit is opposite to the digital signal output unit through internal logic processing.

9. An electronic detonator system, comprising: an electronic detonator control host, an electronic detonator chip as claimed in claim 7 or 8;

the N electronic detonator chips are connected with the electronic detonator control host through a first cable and a second cable.

Technical Field

The embodiment of the invention relates to the technical field of electronic detonators, in particular to a communication demodulation circuit of an electronic detonator, an electronic detonator chip and an electronic detonator system.

Background

The electronic detonator is also called a digital electronic detonator, a digital detonator or an industrial digital electronic detonator, namely an electronic detonator which controls the detonation process by adopting an electronic control module. The electronic control module is arranged in the digital electronic detonator and has the functions of controlling the detonator detonation delay time and controlling the detonation energy.

Electronic detonators, which are the result of a combination of detonator and integrated circuit technology, have been widely used and have replaced conventional initiation systems in many applications. Compared with the prior detonating tube, the high-precision detonating tube realizes the characteristics of high-precision delay, safe control, reliable detonation and the like. The electronic detonator mainly comprises an electronic control module, a bridgewire with a powder head and a powder tube (or a non-detonating powder tube). Before detonation, the external controller supplies power and communicates with the electronic detonator through the bus, so that the operations of encoding, detecting, charging, detonation and the like of the electronic detonator are realized. The external controller generally couples a single or multiple electronic detonators by using a pair of twisted pairs, and the electronic detonators need to meet the requirements of low-voltage and high-voltage communication and stably and correctly receive data.

However, the existing receiving circuit or the structure is complex, which results in high cost and power consumption, or has insufficient compatibility and stability to meet the requirements of full-cycle application.

Therefore, how to provide a communication scheme for an electronic detonator, which can satisfy the power supply and communication requirements and has a simple structure and low cost and power consumption, is a technical problem to be solved by those skilled in the art.

Disclosure of Invention

Therefore, the embodiment of the invention provides a communication demodulation circuit of an electronic detonator, an electronic detonator chip and an electronic detonator system, which can meet the requirements of power supply and communication and have the advantages of simple structure and low cost and power consumption.

In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:

in a first aspect, an embodiment of the present invention provides a communication demodulation circuit of an electronic detonator, including: the device comprises a second field effect transistor, a third field effect transistor, a resistive element, a rectifier and a digital signal output unit;

the second grid electrode of the second field effect transistor is coupled with the third grid electrode of the third field effect transistor;

the second drain electrode and the second grid electrode of the second field effect transistor are commonly coupled to the first cable wire;

a second source electrode of the second field effect transistor and a third source electrode of the third field effect transistor are grounded together;

the third drain of the third field effect transistor and the first end of the resistive element are coupled to a first electrical coupling point;

the second end of the resistive element is coupled with a power supply VDD; the first electric coupling contact is coupled with the digital signal output unit;

the digital signal output unit is used for outputting a digital logic signal to the detonator control unit according to the voltage of the first electric coupling joint; the detonator control unit is coupled to the output end of the digital signal output unit;

the rectifier is coupled with the first cable wire and the second cable wire and used for outputting direct current to supply power for the communication demodulation circuit.

Preferably, the rectifier includes: the diode comprises a first diode, a second diode, a third diode and a fourth diode;

the first diode and the third diode are coupled to a second coupling point in the same direction according to the conducting direction of current;

the second diode and the fourth diode are coupled to a third coupling point in the same direction according to the conducting direction of current;

the first cable wire is coupled to the second coupling point;

the second cable wire is coupled to the third coupling point;

the third diode is coupled with the forward output end of the fourth diode to serve as a power supply output end.

Preferably, the method further comprises the following steps: a first field effect transistor;

the first grid electrode of the first field effect transistor is coupled with the power supply VDD;

a first drain electrode of the first field effect transistor is coupled with the first cable line;

the first source electrode of the first field effect transistor is coupled with the second drain electrode and the second grid electrode.

Preferably, the method further comprises the following steps: a fifth diode;

the first field effect transistor is coupled with the first cable line through the fifth diode;

the anode of the fifth diode is coupled with the first cable line;

and the cathode of the fifth diode is coupled with the drain electrode of the first field effect transistor.

Preferably, the resistive element comprises: resistor, MOS resistor, current source.

Preferably, the digital signal output unit includes: a reverse schmitt trigger, an inverter, or a forward schmitt trigger.

In a second aspect, an embodiment of the present invention provides an electronic detonator chip, including: a detonator control unit, a communication demodulation circuit of the electronic detonator according to any of the first aspects;

the input end of the detonator control unit is coupled with the output end of the digital signal output unit of the communication regulating circuit.

Preferably, the detonator control unit is further configured to: when the detonator control unit is powered on, the received signals are defaulted to be the signals with the same polarity of the digital signal output unit, then the preset time is delayed, and if the output of the digital signal output unit is always logic high, the output ends of the detonator control received signals and the digital signal output unit are kept the same; otherwise, if the output of the digital signal output unit is always logic low after delaying the preset time, the signal received by the detonator control unit is opposite to the digital signal output unit through internal logic processing.

In a third aspect, an embodiment of the present invention provides an electronic detonator control system, including: an electronic detonator control host, such as the electronic detonator chip of any of the second aspects described above;

the N electronic detonator chips are connected with the electronic detonator control host through a first cable and a second cable.

The embodiment of the invention provides a communication demodulation circuit of an electronic detonator, which comprises: the device comprises a second field effect transistor, a third field effect transistor, a resistive element, a rectifier and a digital signal output unit; the second grid electrode of the second field effect transistor is coupled with the third grid electrode of the third field effect transistor; the second drain electrode and the second grid electrode of the second field effect transistor are commonly coupled to the first cable wire; a second source electrode of the second field effect transistor and a third source electrode of the third field effect transistor are grounded together; the third drain of the third field effect transistor and the first end of the resistive element are coupled to a first electrical coupling point; the second end of the resistive element is coupled with a power supply VDD; the first electric coupling contact is coupled with the digital signal output unit; the digital signal output unit is used for outputting a digital logic signal to the detonator control unit according to the voltage of the first electric coupling joint; the detonator control unit is coupled to the output end of the digital signal output unit; the rectifier is coupled with the first cable wire and the second cable wire and used for outputting direct current to supply power for the communication demodulation circuit. The scheme has the advantages of simple structure, low cost and low power consumption while meeting the requirements of power supply and communication.

The communication demodulation circuit of the electronic detonator, the electronic detonator chip and the electronic detonator system provided by the embodiment of the invention have the same beneficial effects, and are not repeated.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It should be apparent that the drawings in the following description are merely exemplary, and that other embodiments can be derived from the drawings provided by those of ordinary skill in the art without inventive effort.

The structures, ratios, sizes, and the like shown in the present specification are only used for matching with the contents disclosed in the specification, so as to be understood and read by those skilled in the art, and are not used to limit the conditions that the present invention can be implemented, so that the present invention has no technical significance, and any structural modifications, changes in the ratio relationship, or adjustments of the sizes, without affecting the effects and the achievable by the present invention, should still fall within the range that the technical contents disclosed in the present invention can cover.

Fig. 1 is a schematic structural diagram of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention;

fig. 2 is a schematic view of an expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention;

fig. 3 is a schematic diagram of another expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention;

fig. 4 is a schematic diagram of another expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention;

fig. 5 is a schematic diagram of another expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention;

fig. 6 is a schematic composition diagram of an electronic detonator control system according to an embodiment of the present invention.

Detailed Description

The present invention is described in terms of particular embodiments, other advantages and features of the invention will become apparent to those skilled in the art from the following disclosure, and it is to be understood that the described embodiments are merely exemplary of the invention and that it is not intended to limit the invention to the particular embodiments disclosed. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 2, fig. 3, fig. 4, and fig. 5, fig. 1 is a schematic structural diagram of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention; fig. 2 is a schematic view of an expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention; fig. 3 is a schematic diagram of another expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention; fig. 4 is a schematic diagram of another expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention; fig. 5 is a schematic view of another expanded structure of a communication demodulation circuit of an electronic detonator according to an embodiment of the present invention.

In a specific implementation manner of the present invention, an embodiment of the present invention provides a communication demodulation circuit of an electronic detonator, including: a second field effect transistor 120, a third field effect transistor 130, a resistive element 140, a rectifier 150, and a digital signal output unit 160;

the second gate of the second fet 120 is coupled to the third gate of the third fet 130;

a second drain and a second gate of the second fet 120 are commonly coupled to the first cable line 101;

the second source of the second fet 120 and the third source of the third fet 130 are commonly grounded;

a third drain of the third fet 130 and a first end of the resistive element 140 are coupled to a first electrical coupling point;

a second terminal of the resistive element 140 is coupled to a power supply VDD; the first electrical coupling point 103 is coupled to the digital signal output unit 160;

the digital signal output unit 160 is used for outputting a digital logic signal to the detonator control unit according to the voltage of the first electric coupling joint; the detonator control unit is coupled to the output end of the digital signal output unit 160;

the rectifier 150 is coupled to the first cable line 101 and the second cable line 102, and is used for outputting direct current to power the communication demodulation circuit.

Specifically, for the rectifier 150, a bridge rectifier 150 may be used, and other forms of rectifiers 150 may also be used, and in practice, a rectifier 150 composed of four diodes may be adopted, and the rectifier 150 includes: the diode comprises a first diode, a second diode, a third diode and a fourth diode; the first diode and the third diode are coupled to a second coupling point in the same direction according to the conducting direction of current; the second diode and the fourth diode are coupled to a third coupling point in the same direction according to the conducting direction of current; the second coupling point is coupled with the first cable line 101; the third coupling point is coupled to the second cable line 102; the third diode is coupled with the forward output end of the fourth diode to serve as a power supply output end. Therefore, the L0 and the L1 and the ground of the chip are coupled to the corresponding ports of the rectifier 150 composed of the diodes D1 to D4, when a voltage difference of a certain magnitude exists between the L0 and the L1, a voltage difference is generated between the output of the rectifier 150 and the ground of the chip, at this time, the output of the rectifier 150 provides power for the chip, and the voltage can be converted into a low-voltage power supply VDD for the operation of the internal logic circuit through a power processing module such as an LDO.

Further, in practice, in order to protect the second fet 120 and the third fet 130, the first fet 110 may be further provided; the first gate of the first fet 110 is coupled to the power supply VDD; a first drain electrode of the first field effect transistor 110 is coupled with the first cable line 101; the first source of the first fet 110 is coupled to the second drain and the second gate; the second drain and the second gate of the second fet 120 are commonly coupled to the first cable line 101 through the first source and the second source of the first fet 110. At this time, the second fet 120 and the third fet 130 may be configured as low-voltage fets, and the first fet 110 may be configured as high-voltage fets, but of course, if the first fet 110 is not provided, both the second fet 120 and the third fet 130 may be configured as high-voltage fets in order to prevent the second fet 120 and the third fet 130 from being damaged.

In order to prevent the voltage from reversing, a fifth diode may also be provided; the first fet 110 is coupled to the first cable line 101 through the fifth diode; the anode of the fifth diode is coupled to the first cable line 101; the cathode of the fifth diode is coupled to the drain of the first fet 110. That is, the fifth diode and the first fet 110 are connected in series to the drain of the second fet 120, but only one of the fifth diode and the first fet 110 may be provided.

In practice, for the resistive element 140, a resistor, a MOS resistor, a current source may be used. The terminal voltage and the current have a determined functional relation, and a two-terminal device which reflects the capability of converting electric energy into other forms is represented by a letter R and has the unit of ohm omega. Actual devices such as bulbs, heating wires, resistors, etc. may be represented as resistor elements. Of course, other resistive elements 140 may be used, such as MOS resistors or current sources. For the digital signal output unit 160, a reverse schmitt trigger, an inverter, a forward schmitt trigger, or the like can be used.

In practice, L0 (first cable line) or L1 (second cable line) is also coupled to the circuit for signal demodulation inside the chip for signal transmission.

The signal demodulation circuit comprises a diode D1, a high-voltage NMOS transistor MN1, low-voltage NMOS transistors MN2 and MN3, a resistor R1 and a reverse Schmitt trigger S1. The input end of the signal demodulation unit is shown as a point A, and other coupling relations are also shown as the point A. The gate of the high-voltage NMOS device MN1 is connected with VDD, so that the device is always conducted, and the source voltage of MN2 is limited to VDD-VGSMN1, so that the source voltage of the low-voltage device MN2 cannot exceed the highest tolerable voltage all the time, namely, when the voltage at the point A is higher than the highest tolerable voltage, the MN2 device can still be protected through MN 1. And the reverse Schmitt trigger can eliminate interference signals in communication.

When the voltage of L0 is smaller than L1, L0 is negative voltage relative to the ground of the chip when L0 is connected to the port A of the chip, D1 is cut off, MN2 has no current flowing, and MN2 and MN3 form a current mirror circuit, so that MN3 has no current flowing, the input end of the reverse Schmitt trigger S1 is pulled to VDD potential by a resistor R1, the voltage is obviously larger than the high-side inversion threshold of S1, and the output is logic low; when the voltage of L0 is greater than L1, L0 is positive with respect to the chip ground, and since D1 and MN1 are both turned on, there will be a current flowing from the source of MN2 to the chip ground. The ratio of MN3 to MN2 can be set appropriately so that when point a is at the appropriate voltage, MN3 passes enough current to pull the input potential of the reverse schmitt trigger S1 low to its reversible low-side threshold and the S1 output is high. It can be seen that the S1 output and L0 are now of the same polarity relative to L1. If L1 is connected to chip A port, the output of S1 will have the same polarity as L1. So that signals can be transmitted from either L1 or L0 to the detonator control unit via the signal conditioning circuit.

As shown in fig. 2, the fifth diode is not present in the figure; as shown in fig. 3, the first fet is not present in the figure; as shown in fig. 4, a current source is used as a resistive element in the figure; as shown in fig. 5, in the figure, the fifth diode, the first fet and the resistor are used simultaneously, and these various circuits are all within the protection scope of the present invention.

In another embodiment of the present invention, an electronic detonator chip includes: a detonator control unit, a communication demodulation circuit of the electronic detonator according to any of the first aspects; the input end of the detonator control unit is coupled with the output end of the digital signal output unit of the communication regulating circuit.

Specifically, the detonator control unit is further configured to: when the detonator control unit is powered on, the received signals are defaulted to be the signals with the same polarity of the digital signal output unit, then the preset time is delayed, and if the output of the digital signal output unit is always logic high, the output ends of the detonator control received signals and the digital signal output unit are kept the same; otherwise, if the output of the digital signal output unit is always logic low after delaying the preset time, the signal received by the detonator control unit is opposite to the digital signal output unit through internal logic processing.

In order to avoid confusion between the wiring relationships of L0 and L1, the S1 output is transmitted to the detonator control unit and then processed by the signal polarity: and after the detonator control unit is powered on, the received signal is the signal with the same polarity as the signal S1 by default, the signal is delayed for a period of time, if the output of S1 is always logic high, the signal received by the detonator control is kept the same as the signal S1, otherwise, if the output of S1 is always logic low after the signal is delayed for a period of time, the signal received by the detonator control is kept opposite to the signal S1 through internal logic processing. This ensures that power-up is delayed for a period of time regardless of the direction in which L0 and L1 access the signal demodulation elements. The output of the selector delivered to the detonator control unit is all logic high. Thus, the signals received by the electronic detonator array coupled by the twisted pair by the host are all the same.

For example, the initial state L0 of the electronic detonator host is logic high, L1 is logic low, and meanwhile, for the electronic detonator 1, the coupling mode is that L0 is connected with a, then the initial output of S1 is logic high, after a period of time, the detonator control unit maintains the input of the detonator control unit to be the same as the output polarity of S1, so that when L0> L1, the detonator control will judge that the signal is logic high, and when L0< L1, the detonator control will judge that the signal is logic low; assuming that the connection method of the other electronic detonator 2 mounted on the twisted pair is L1 connection A, the output of S1 is logic low initially, after a period of time, the detonator control unit maintains the polarity of the input of the detonator control unit and the output of S1 to be opposite, so that the detonator control judges that the signal is logic high when L0 is larger than L1, and judges that the signal is logic low and visible when L0 is smaller than L1, and the signals received by the electronic detonator chip mounted on the twisted pair are the same no matter how L0 and L1 are connected.

Note that the waiting time for judging whether the polarity needs to be reversed by the detonator control unit can be freely set according to application requirements, and the signal of the host is determined and unchanged in the judging process, so that the electronic detonator chip can automatically adjust the signal polarity to be in the same state in the power-on initialization stage. In the later working time, the polarity of the signals received by the detonator is always kept in the state of judgment after delay

Referring to fig. 6, fig. 6 is a schematic composition diagram of an electronic detonator control system according to an embodiment of the present invention.

The embodiment of the invention provides an electronic detonator control system, which comprises: an electronic detonator control host, an electronic detonator chip as described in any of the above embodiments; the N electronic detonator chips are connected with the electronic detonator control host through a first cable and a second cable.

Although the invention has been described in detail above with reference to a general description and specific examples, it will be apparent to one skilled in the art that modifications or improvements may be made thereto based on the invention. Accordingly, such modifications and improvements are intended to be within the scope of the invention as claimed.