阅读说明：本技术 一种可编程高精度动态驱动GaN的电路及其应用 (Programmable high-precision dynamic GaN driving circuit and application thereof ) 是由 童乔凌 曾婉华 张毅 严金程 于 2020-03-19 设计创作，主要内容包括：本发明属于功率半导体器件开关领域,具体涉及一种可编程高精度动态驱动GaN的电路及其应用,电路包括可编程数字模块、时钟产生模块和驱动模块；可编程数字模块包括EEPROM读出电路、寄存器电路、逻辑控制电路；驱动电路包括粗略驱动电路和精细驱动电路。开通关断时间均分为多个时间段,每个时间段为一个粗略驱动周期；每个粗略驱动周期中可进行一次精细驱动微调,以产生脉冲控制精细驱动电路驱动电流。上电后通过EEPROM读出电路将片外数据存储于寄存器中,震荡器电路控制逻辑电路在开通和关断过程将所需数据传给驱动电路,动态控制多个粗略驱动周期的粗略驱动电路和精细驱动电路,实现可编程高精度的主动GaN栅极控制。(The invention belongs to the field of power semiconductor device switches, and particularly relates to a programmable high-precision dynamic GaN driving circuit and application thereof, wherein the circuit comprises a programmable digital module, a clock generation module and a driving module; the programmable digital module comprises an EEPROM reading circuit, a register circuit and a logic control circuit; the driving circuit includes a coarse driving circuit and a fine driving circuit. The on-off time is divided into a plurality of time periods, and each time period is a rough driving period; fine drive trimming may be performed once per coarse drive period to generate pulses to control the fine drive circuit drive current. After the power is on, off-chip data are stored in the register through the EEPROM reading circuit, the oscillator circuit controls the logic circuit to transmit required data to the driving circuit in the opening and closing processes, the rough driving circuit and the fine driving circuit of a plurality of rough driving periods are dynamically controlled, and programmable high-precision active GaN grid control is achieved.)

1. A programmable high-precision dynamic GaN driving circuit, comprising: the device comprises a programmable digital module, a driving module and a clock generating module; the programmable digital module comprises an EEPROM reading circuit, a register circuit and a logic control circuit; the driving module comprises a rough driving circuit and a fine driving circuit, wherein the outputs of the rough driving circuit and the fine driving circuit are electrically connected with a GaN grid electrode to be driven;

the control driving process of the logic control circuit is divided into a plurality of rough driving time periods, whether fine trimming is carried out once or not can be selected in each rough driving time period to change the driving current of the rough driving time period, and the driving data is stored in an off-chip programmable EEPROM in a programmable mode;

after the power-on, the EEPROM reading circuit is used for reading out the drive data in the EEPROM and storing the drive data in the register circuit, an externally input PWM square wave signal is electrically connected with the input of the logic control circuit, and the drive module is closed and has no drive current until the action of the PWM square wave signal in the power-on process; after the PWM square wave signal acts, the logic control circuit transmits the driving data in the register circuit to the coarse driving circuit and the fine driving circuit according to the clock signal clk of the clock generating circuit, and controls the currents of the coarse driving and the fine driving for the plurality of coarse driving time periods, thereby achieving the desired dynamic driving waveform.

2. The circuit of claim 1, wherein each coarse driving time period has a plurality of coarse driving circuit current levels selectable, each fine driving circuit current level also has a plurality of fine driving circuit current levels selectable, and the driving data comprises the coarse driving circuit current levels, the fine driving delay time, the fine driving pulse duration, and the fine driving circuit current levels in the plurality of coarse driving time periods.

3. The circuit of claim 1, wherein the coarse driving circuit comprises first to eighth main driving circuits with different output current levels, and the logic control circuit comprises a cycle counting circuit, first to eighth control main driving logic circuits;

the period counting circuit is used for counting the period of the rough driving time period after the PWM square wave signal is detected to jump; the first to eighth control main driving logic circuits are used for selecting corresponding driving data to control the first to eighth main driving circuits according to the rough driving time period indicated by the period counting circuit, so that the total current output by the rough driving circuit meets the current level of the rough driving circuit corresponding to the driving data.

4. The programmable high-precision dynamic driving GaN circuit of claim 3, wherein the period counting circuit is used for generating a short pulse by using the edge detection circuit after detecting the transition of the PWM square wave signal, the period count is cleared, the output of the ports L0 to L2 is 000, which represents the first coarse driving time period, then the clock signal clk is counted eight times, the ports L0 to L2 are sequentially added from 000 to 111, the counting is stopped, and the output is kept at 111, which represents that eight coarse clock periods are counted.

5. The circuit of claim 3, wherein each of the main driving circuits comprises a level shift circuit, a delay matching circuit, a first buffer circuit, a second buffer circuit, a driving PMOS transistor and a driving NMOS transistor;

the level shift circuit is used for improving the level of a logic signal input from the logic control circuit, the first buffer circuit is used for amplifying the driving capability of the logic signal output by the level shift circuit and driving the grid electrode of the driving PMOS tube, and the GaN grid electrode is charged when the driving PMOS tube is opened to open the GaN;

the delay matching circuit is used for ensuring that the delay from the logic signal input by the logic control circuit to the drive NMOS tube is the same as that of the drive PMOS tube; the second buffer circuit is used for amplifying the driving capability of the logic signal output by the delay matching circuit and driving the grid electrode of the driving NMOS tube; when the drive NMOS tube is opened, discharging the GaN grid electrode, and closing the GaN;

the first to eighth control main drive logic circuits are the same and each include a control main drive PMOS logic circuit and a control main drive NMOS logic circuit, and respectively control the switches of the drive PMOS transistors and the drive NMOS transistors of the first to eighth main drive circuits correspondingly.

6. The programmable high-precision dynamic GaN driving circuit of claim 5, wherein the driving PMOS transistor sizes of the first to eighth main driving circuits are respectively, in units of the driving PMOS transistor size of the first main driving circuit: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits are all selectable switches, and the rough driving circuit has 2 in its entirety in the process of driving GaN to be turned on⁸A coarse drive circuit current level;

taking the size of the drive NMOS tube of the first main drive circuit as a unit, the sizes of the drive NMOS tubes of the first to eighth main drive circuits are respectively as follows: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits can all select switches, and the rough driving circuit has 2 in the whole during driving the GaN to be turned off⁸A coarse drive circuit current level.

7. The circuit of claim 6, wherein the fine driving circuit comprises first to sixth sub-driving circuits, wherein each sub-driving circuit has the same structure as each main driving circuit, and the unit driving PMOS transistor and the unit driving NMOS transistor in each sub-driving circuit have different sizes from those of the main driving circuit;

the logic control circuit further includes first to sixth fine driving logic control circuits with the same structure, which respectively control the switches of the driving PMOS transistors and the driving NMOS transistors of the first to sixth sub-driving circuits correspondingly, so that when each coarse driving time period starts, after the fine driving delay time in the driving data corresponding to the period, the switches of the driving PMOS transistors and the driving NMOS transistors in the first to sixth sub-driving circuits are controlled according to the current levels of the fine driving circuits in the driving data, the duration of the fine driving pulse in the driving data corresponding to the period continues, and finally, all the fine driving circuits are turned off after the coarse driving time period ends.

8. The circuit of claim 7, wherein each of said fine drive logic control circuits comprises first through seventh fine drive register logic circuits, a fine drive pulse generation circuit;

the first to seventh fine driving register logic circuits are used for selecting corresponding driving data according to the coarse driving time period indicated by the period indication circuit;

the fine driving pulse generating circuit is used for judging whether to generate a control pulse according to the selected driving data, if so, selecting and outputting the pulse width and the pulse delay to generate a fine driving pulse with adjustable width and delay.

9. The programmable high-precision dynamic driving GaN circuit according to any of claims 1 to 8, wherein the clock generation circuit comprises a ring oscillator circuit, a temperature-positive correlation current generation circuit and a current trimming circuit;

the ring oscillator circuit is used for generating a clock signal, and the precision of the clock signal is deviated due to temperature and a process angle;

the temperature positive correlation current generation circuit is used for generating a temperature positive correlation current to offset the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the temperature;

the current trimming circuit is used for offsetting the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the process angle in the temperature compensated clock signal output by the temperature positive correlation current generating circuit.

10. A dynamic driving method of a GaN power switch device is characterized in that the circuit of programmable high-precision dynamic driving GaN according to any one of claims 1 to 9 is adopted to actively drive the GaN power switch device, so as to realize the dynamic driving of the GaN power switch device.

Technical Field

The invention belongs to the field of power semiconductor device switches, and particularly relates to a programmable high-precision dynamic GaN driving circuit and application thereof.

Background

Power electronic devices are widely used in people's daily life, wherein power semiconductor devices play a crucial role in power electronics. In a power semiconductor device, the performance of an MOSFET device basically tends to be mature and stable, and GaN is used as a new device which is different from the MOSFET in materials and structures and has smaller device size, lower on-resistance and smaller input capacitance; thereby enabling GaN to have faster switching speed and lower static loss.

The faster switching speed of GaN presents challenges to its driving, which can lead to more severe ringing and more overshoot, which not only can damage the device, but can also lead to parasitic conduction, resulting in through-burn out of the device. Typically, to reduce ringing and overshoot, the gate resistance needs to be increased to slow its turn-on speed, but this increases switching losses. There is a trade-off between switching speed and switching losses, and dynamic driving can effectively reduce ringing and overshoot without increasing switching losses. When the GaN-based transistor is switched on, the grid capacitor is rapidly charged by using a small grid driving resistor before the threshold voltage is reached, after a GaN channel is formed, the flowing GaN current rises, then the VDS voltage of the GaN-based transistor drops, and at the stage, the grid capacitor is slowly charged by using a large driving resistor, so that overshoot and ringing phenomena are suppressed. When the grid electrode is turned off, the grid electrode capacitor is discharged, before the grid electrode voltage is reduced to the threshold voltage, the small grid electrode driving resistor is adopted to quickly discharge the grid electrode capacitor, and when the channel is close to be closed, the large grid electrode driving resistor is adopted to slowly discharge the grid electrode capacitor, so that the overshoot and ringing phenomena are inhibited.

The driving method for controlling the grid driving voltage waveform can be realized in a closed loop feedback or open loop mode in theory. Closed-loop feedback is usually implemented by detecting GaN current and voltage, and adjusting the gate drive resistance in real time when the rising or falling speed is too fast, thereby controlling the on/off of the GaN. However, GaN switches at a fast speed, and the feedback loop takes a certain time to adjust the circuit, which is not suitable for driving GaN.

Disclosure of Invention

The invention provides a programmable high-precision dynamic driving GaN circuit and application thereof, which are used for solving the technical problem that a preset driving waveform cannot be obtained when GaN is driven due to driving delay of the conventional dynamic driving GaN circuit.

The technical scheme for solving the technical problems is as follows: a programmable high precision dynamically driven GaN circuit, comprising: the device comprises a programmable digital module, a driving module and a clock generating module; the programmable digital module comprises an EEPROM reading circuit, a register circuit and a logic control circuit; the driving module comprises a rough driving circuit and a fine driving circuit, wherein the outputs of the rough driving circuit and the fine driving circuit are electrically connected with a GaN grid electrode to be driven;

the control driving process of the logic control circuit is divided into a plurality of rough driving time periods, whether fine trimming is carried out once or not can be selected in each rough driving time period to change the driving current of the time period, and the driving data is stored in the programmable EEPROM outside the chip in a programmable mode;

after the power-on, the EEPROM reading circuit is used for reading out the drive data in the EEPROM and storing the drive data in the register circuit, an externally input PWM square wave signal is electrically connected with the input of the logic control circuit, and the drive module is closed and has no drive current until the action of the PWM square wave signal in the power-on process; after the PWM square wave signal acts, the logic control circuit transmits the driving data in the register circuit to the coarse driving circuit and the fine driving circuit according to the clock signal clk of the clock generating circuit, and controls the currents of the coarse driving and the fine driving for the plurality of coarse driving time periods, thereby achieving the desired dynamic driving waveform.

The invention has the beneficial effects that: the invention provides a programmable high-precision dynamic GaN driving circuit, which divides a driving process into a plurality of time periods of rough driving, wherein a plurality of main driving current grades can be selected in each period, whether fine trimming is carried out or not can be selected in each section to change the driving current of the circuit, the currents of the rough driving and the fine driving in eight time periods are controlled in a programmable mode so as to achieve an expected driving waveform, and the control precision is high.

On the basis of the technical scheme, the invention can be further improved as follows.

Further, each coarse driving time period has a plurality of selectable coarse driving circuit current levels, and each fine driving also has a plurality of selectable fine driving circuit current levels, so that the driving data includes the coarse driving circuit current levels, the fine driving delay time, the fine driving pulse duration, and the fine driving circuit current levels in the plurality of coarse driving time periods.

The invention has the further beneficial effects that: each driving period of the rough driving can be provided with a large amount of selectable driving current, whether fine driving is carried out or not can be selected in each driving period of the rough driving, similarly, each fine driving can also be provided with a large amount of selectable driving current, the starting time, the duration and the like of the fine driving can be programmed, driving data can be set according to the actual driving waveform requirement, the driving controllability is high, and the expected driving waveform is finally achieved.

Further, the coarse driving circuit comprises first to eighth main driving circuits with different output current magnitudes, and the logic control circuit comprises a period counting circuit and first to eighth control main driving logic circuits;

the period counting circuit is used for counting the period of the rough driving time period after the PWM square wave signal is detected to jump; the first to eighth control main driving logic circuits are used for selecting corresponding driving data to control the first to eighth main driving circuits according to the rough driving time period indicated by the period counting circuit, so that the total current output by the rough driving circuit meets the current level of the rough driving circuit corresponding to the driving data.

The invention has the further beneficial effects that: the coarse driving circuit for coarse driving of the present invention includes first to eighth main driving circuits having different magnitudes of output currents, each of which is used for coarse drivingTime period, each main driving circuit has two options of on and off, so that the total is 2⁸A switching sequence of 2⁸The rough driving current levels are selectable, the selectivity is high, more expected driving waveforms can be met, and meanwhile the problem of poor controllability caused by excessive main driving circuits is solved.

Further, the period counting circuit is used for generating a short pulse by using the edge detection circuit after detecting that the transition of the PWM square wave signal occurs, the period count is cleared, the output of the output L0 to L2 port is 000, which represents the first coarse driving time period, then the clock signal clk starts to be counted eight times, the output of the output L0 to L2 port is sequentially increased from 000 to 111, namely, the counting is stopped and the output is kept at 111, which represents that the eight coarse clock periods are counted completely.

Furthermore, each main driving circuit comprises a level shift circuit, a delay matching circuit, a first buffer circuit, a second buffer circuit, a driving PMOS tube and a driving NMOS tube;

the level shift circuit is used for improving the level of a logic signal input from the logic control circuit, the first buffer circuit is used for amplifying the driving capability of the logic signal output by the level shift circuit and driving the grid electrode of the driving PMOS tube, and the GaN grid electrode is charged when the driving PMOS tube is opened to open the GaN;

the delay matching circuit is used for ensuring that the delay from the logic signal input by the logic control circuit to the drive NMOS tube is the same as that of the drive PMOS tube; the second buffer circuit is used for amplifying the driving capability of the logic signal output by the delay matching circuit and driving the grid electrode of the driving NMOS tube; when the drive NMOS tube is opened, discharging the GaN grid electrode, and closing the GaN;

the first to eighth control main drive logic circuits are the same and each include a control main drive PMOS logic circuit and a control main drive NMOS logic circuit, and respectively control the switches of the drive PMOS transistors and the drive NMOS transistors of the first to eighth main drive circuits correspondingly.

The invention has the further beneficial effects that: each main driving circuit is divided into two paths of driving and is used for realizing the opening and closing of the GaN respectively, and each main driving circuit is provided with a level shift circuit, a delay matching circuit, a first buffer circuit and a second buffer circuit which realize the functions, so that the driving capability and the driving precision are ensured.

Further, taking the size of the driving PMOS transistor of the first main driving circuit as a unit, the sizes of the driving PMOS transistors of the first to eighth main driving circuits are respectively: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits are all selectable switches, and the rough driving circuit has 2 in its entirety in the process of driving GaN to be turned on⁸A coarse drive circuit current level;

taking the size of the drive NMOS tube of the first main drive circuit as a unit, the sizes of the drive NMOS tubes of the first to eighth main drive circuits are respectively as follows: 1. 2, 4, 16, 32, 64, 128, 256, the first to eighth main driving circuits can all select switches, and the rough driving circuit has 2 in the whole during driving the GaN to be turned off⁸A coarse drive circuit current level.

The invention has the further beneficial effects that: through the size design of the MOS tube, eight main driving circuits with different current output capacities are realized, and the circuit is simple and low in cost.

Further, the fine driving circuit comprises first to sixth auxiliary driving circuits, wherein each auxiliary driving circuit has the same structure as each main driving circuit, and the unit driving PMOS tube and the unit driving NMOS tube in each auxiliary driving circuit have different sizes from those of the unit driving PMOS tube and the unit driving NMOS tube in the main driving circuit;

the logic control circuit further includes first to sixth fine driving logic control circuits with the same structure, which respectively control the switches of the driving PMOS transistors and the driving NMOS transistors of the first to sixth sub-driving circuits correspondingly, so that when each coarse driving time period starts, after the fine driving delay time in the driving data corresponding to the period, the switches of the driving PMOS transistors and the driving NMOS transistors in the first to sixth sub-driving circuits are controlled according to the current levels of the fine driving circuits in the driving data, the duration of the fine driving pulse in the driving data corresponding to the period continues, and finally, all the fine driving circuits are turned off after the coarse driving time period ends.

Further, each of the fine drive logic control circuits includes first to seventh fine drive register logic circuits, a fine drive pulse generating circuit;

the first to seventh fine driving register logic circuits are used for selecting corresponding driving data according to the coarse driving time period indicated by the period indication circuit;

the fine driving pulse generating circuit is used for judging whether to generate a control pulse according to the selected driving data, if so, selecting and outputting the pulse width and the pulse delay to generate a fine driving pulse with adjustable width and delay.

The invention has the further beneficial effects that: different from the first to eighth control main driving logic circuits, the first to sixth fine driving logic control circuits are not divided into two circuits to respectively control the switches of the driving PMOS tube and the driving NMOS tube, so that fine trimming of the driving current is realized.

Further, the clock generation circuit comprises a ring oscillator circuit, a current generation circuit positively correlated with temperature and a current trimming circuit;

the ring oscillator circuit is used for generating a clock signal, and the precision of the clock signal is deviated due to temperature and a process angle;

the temperature positive correlation current generation circuit is used for generating a temperature positive correlation current to offset the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the temperature;

the current trimming circuit is used for offsetting the deviation of the precision of the clock signal generated by the ring oscillator circuit along with the process angle in the temperature compensated clock signal output by the temperature positive correlation current generating circuit.

The invention has the further beneficial effects that: the current generation circuit and the current trimming circuit which are positively correlated with the temperature are adopted to trim the generated clock signal, so that the accuracy of driving on time is further ensured, and an expected driving waveform is obtained.

The invention also provides a dynamic driving method of the GaN power switch device, which adopts any one of the circuits for driving the GaN in a programmable high-precision dynamic mode to actively drive the GaN power switch device, so as to realize the dynamic driving of the GaN power switch device.

The invention has the beneficial effects that: by adopting the circuit for dynamically driving the GaN in the programmable high-precision manner, the driving of the GaN switch in the programmable high-precision manner is realized, the ringing and the overshoot are effectively reduced, the switch loss is not increased, and the practicability is high.

Drawings

FIG. 1 is a block diagram of a programmable high-precision dynamically-driven GaN circuit according to an embodiment of the invention;

FIG. 2 is a circuit diagram of a main driving circuit and a sub-driving circuit in a programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;

FIG. 3 is a diagram of a cycle counting circuit in a logic control module of the programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;

FIG. 4 is a schematic diagram of a main driving logic circuit in a logic control module of the programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;

FIG. 5 is a schematic diagram of a fine driving logic circuit in a logic control module of a programmable high-precision dynamic GaN driving circuit according to an embodiment of the invention;

fig. 6 is a schematic diagram of a fine driving period indication circuit in a fine driving logic circuit in a logic control module in a programmable high-precision dynamic GaN driving circuit according to an embodiment of the present invention;

FIG. 7 is a schematic diagram of a fine driver register logic circuit in a fine driver logic circuit in a logic control module in a programmable high precision dynamic driver GaN driver circuit according to an embodiment of the invention;

fig. 8 is a timing diagram of the driving output current of the programmable high-precision GaN driving circuit according to the embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention. In addition, the technical features involved in the embodiments of the present invention described below may be combined with each other as long as they do not conflict with each other.