阅读说明：本技术 具有突发设定的功率因数校正电路及其操作方法 (Power factor correction circuit with burst setting and method of operating the same ) 是由 洪宗良 姚宇桐 于 2020-04-27 设计创作，主要内容包括：本发明关于一种具有突发设定的功率因数校正电路及其操作方法,方案要点：突发设定电路在输入电源处于正半周上升缘、正半周下降缘、负半周上升缘及负半周下降缘时,分别设定至少一突发时段,且提供对应至少一突发时段的突发设定信号至控制单元,使控制单元限制转换电路在至少一突发时段进行突发操作；本发明的具有突发设定的功率因数校正电路使用突发设定电路侦测输入电源的波形,且根据输入电源的波形设定转换电路能够进行突发操作的特定时段,以达到大幅度的降低输出电源的涟波电压之功效。(The invention relates to a power factor correction circuit with burst setting and an operation method thereof, and the key points of the scheme are as follows: when the input power is at the positive half cycle rising edge, the positive half cycle falling edge, the negative half cycle rising edge and the negative half cycle falling edge, the burst setting circuit respectively sets at least one burst time interval and provides a burst setting signal corresponding to the at least one burst time interval to the control unit, so that the control unit limits the switching circuit to carry out burst operation in the at least one burst time interval; the power factor correction circuit with burst setting of the invention uses the burst setting circuit to detect the waveform of the input power supply, and sets the specific time period for which the conversion circuit can carry out burst operation according to the waveform of the input power supply, so as to achieve the effect of greatly reducing the ripple voltage of the output power supply.)

1. A power factor correction circuit with burst setting is characterized by comprising a conversion circuit, a control unit and a control unit, wherein the conversion circuit receives an input power supply, is coupled with the conversion circuit and controls the conversion circuit to convert the input power supply into an output power supply; and

a burst setting circuit coupled to the switching circuit and the control unit;

when the input power is at the positive half cycle rising edge, the positive half cycle falling edge, the negative half cycle rising edge and the negative half cycle falling edge, the burst setting circuit respectively sets at least one burst time interval, and provides a burst setting signal corresponding to the at least one burst time interval to the control unit, so that the control unit limits the switching circuit to carry out burst operation in the at least one burst time interval.

2. The PFC circuit of claim 1, wherein a midpoint of the at least one burst period is not located between a zero and a peak of the positive half-cycle and the negative half-cycle.

3. The PFC circuit of claim 1, wherein a period width of the at least one burst period is proportional to a load of the conversion circuit.

4. The PFC circuit of claim 1, wherein the at least one burst period of the positive half-cycle rising edge, the positive half-cycle falling edge, the negative half-cycle rising edge and the negative half-cycle falling edge is symmetrically arranged.

5. The pfc circuit of claim 1 wherein the burst setting circuit comprises:

a threshold generating circuit for providing at least one first threshold voltage and at least one second threshold voltage;

a first comparison circuit coupled to the threshold generation circuit and the conversion circuit;

a second comparator coupled to the threshold generating circuit and the converting circuit; and

a logic control circuit coupled to the comparison circuit and the control unit;

the first comparison circuit provides at least one first comparison signal to the logic control circuit according to the at least one first threshold voltage and a half-wave voltage corresponding to the input power supply, and the second comparison circuit provides at least one second comparison signal to the logic control circuit according to the at least one second threshold voltage and the half-wave voltage; the logic control circuit provides the burst setting signal to the control unit according to the at least one first comparison signal and the at least one second comparison signal.

6. The PFC circuit of claim 5, wherein the logic control circuit sets an end point of the at least one burst period of the positive half-cycle rising edge and the negative half-cycle falling edge and sets a start point of the at least one burst period of the positive half-cycle falling edge and the negative half-cycle rising edge according to the first comparison signal.

7. The PFC circuit of claim 5, wherein the logic control circuit sets the start point of operation of the positive half-cycle rising edge and the negative half-cycle falling edge and sets the end point of operation of the positive half-cycle falling edge and the negative half-cycle rising edge according to the at least one second comparison signal.

8. The PFC circuit of claim 5, wherein the threshold generation circuit comprises:

a threshold conversion circuit for receiving the at least one first threshold voltage;

the threshold conversion circuit converts the at least one first threshold voltage into the at least one second threshold voltage, and the at least one second threshold voltage is smaller than the at least one first threshold voltage corresponding to the at least one second threshold voltage.

9. The PFC circuit of claim 5, wherein the threshold generation circuit obtains the at least one first threshold voltage from an external device, or the threshold generation circuit self-generates the at least one first threshold voltage, or the threshold generation circuit is further coupled to the control unit and obtains the at least one first threshold voltage from the control unit.

10. The PFC circuit of claim 5, wherein the logic control circuit comprises:

an edge value trigger circuit coupled to the first comparison circuit and the second comparison circuit;

an OR gate circuit coupled to the edge value trigger circuit; and

a flip-flop coupled to the OR gate;

wherein the edge triggering circuit provides at least one first edge triggering signal to the or gate circuit according to the at least one first comparison signal, and provides at least one second edge triggering signal to the or gate circuit according to the at least one second comparison signal; the OR gate circuit provides a logic signal to the flip-flop according to the at least one first edge trigger signal and the at least one second edge trigger signal, so that the flip-flop provides the burst setting signal to the control unit according to the logic signal.

11. The pfc circuit of claim 1, wherein the control unit comprises:

the comparison unit receives a feedback signal corresponding to the output power supply;

a multiplier coupled to the comparing unit and the converting circuit; and

a pulse width modulation unit coupled to the multiplier, the conversion circuit and the burst setting circuit;

wherein, the comparing unit provides an error signal to the multiplier according to the feedback signal and a reference voltage; the multiplier provides a control signal to the PWM unit according to a half-wave voltage corresponding to the input power and the error signal; the PWM unit provides a PWM signal to control the conversion circuit according to the control signal, and limits the PWM signal to be provided to the conversion circuit in the at least one burst period according to the burst setting signal so as to limit the conversion circuit to perform the burst operation in the at least one burst period.

12. The pfc circuit of claim 1, wherein the switching circuit comprises:

a rectifying unit receiving the input power; and

the conversion unit is coupled with the rectification unit and comprises at least one power switch, and the at least one power switch is coupled with the control unit;

the rectifying unit is used for rectifying the input power supply into a half-wave voltage and filtering the half-wave voltage into a direct-current power supply; the control unit controls the conversion unit to convert the direct current power supply into the output power supply by controlling the switching conduction of the at least one power switch.

13. A method of operating a power factor correction circuit with burst setting, comprising the steps of:

(a) the control unit is used for controlling the conversion circuit to convert the input power supply into the output power supply;

(b) respectively setting at least one burst period when the input power is at a positive half-cycle rising edge, a positive half-cycle falling edge, a negative half-cycle rising edge and a negative half-cycle falling edge, and providing a burst setting signal corresponding to the at least one burst period; and

(c) the control unit limits the switching circuit to perform burst operation in a burst period according to the burst setting signal.

14. The method of operating a power factor correction circuit of claim 13, wherein step (b) comprises:

(b1) providing at least one first comparison signal according to at least one first threshold voltage and a half-wave voltage corresponding to the input power supply;

(b2) providing at least one second comparison signal according to at least one second threshold voltage and the half-wave voltage; and

(b3) the burst setting signal is provided according to the at least one first comparison signal and the at least one second comparison signal.

15. The method of claim 14, wherein step (b1) comprises:

(b11) the at least one first threshold voltage is converted into the at least one second threshold voltage, and the at least one second threshold voltage is smaller than the at least one first threshold voltage corresponding to the at least one second threshold voltage.

16. The method of operating a pfc circuit of claim 14 wherein step (b3) comprises:

(b31) providing at least one first edge value trigger signal according to the at least one first comparison signal, and providing at least one second edge value trigger signal according to the at least one second comparison signal;

(b32) providing a logic signal according to the at least one first edge value trigger signal and the at least one second edge value trigger signal; and

(b33) the burst setup signal is provided according to the logic signal.

17. The method of operating a power factor correction circuit of claim 14, wherein step (a) comprises:

(a1) the conversion circuit rectifies the input power supply into a half-wave voltage and filters the half-wave voltage into a direct current power supply;

(a2) the control unit controls the conversion circuit to convert the direct current power supply into the output power supply;

(a3) the control unit provides an error signal according to a feedback signal corresponding to the output power supply and a reference voltage;

(a4) the control unit provides a control signal according to a half-wave voltage corresponding to the input power supply and the error signal; and

(a5) the control unit provides a pulse width modulation signal to control the conversion circuit according to the control signal.

18. The method of claim 17, wherein step (c) comprises:

(c1) the control unit limits the PWM signal to be provided to the conversion circuit in the at least one burst period according to the burst setting signal, so as to limit the conversion circuit to perform the burst operation in the at least one burst period.

Technical Field

The present invention relates to a power factor correction circuit with burst setting, and more particularly, to a power factor correction circuit capable of performing burst operation in a specific time period and an operating method thereof.

Background

In the field of power factor corrector, the circuit design for improving the efficiency of the power factor corrector is more and more diversified due to the more and more high efficiency of the power factor corrector. When the load of the power factor corrector is light load, the current required by the load is small, and the controller can meet the current required by the load without continuously controlling the power factor corrector to work. Therefore, in order to improve the efficiency of the pfc, a burst Mode (Bust Mode) control method is often used to control the pfc when the load is light.

When the power factor corrector is operated under light load, the controller controls the power factor corrector to operate in a burst mode. When the output power Vo of the power factor corrector is insufficient, the controller controls the power factor corrector to operate, so that the inductor in the power factor corrector starts to store energy and release energy to generate an inductor current Il. Since the input current of the pfc follows the input power, the waveforms of the inductor current Il corresponding to the input current and the half-wave voltage Vh corresponding to the input power are as shown in fig. 1. As can be clearly seen from fig. 1, the controller performs the control of the burst mode as a random action without a fixed period or synchronization with the mains supply, so that the ripple voltage Vr of the output power Vo appears to be irregular, which causes a large ripple voltage Vr and causes poor quality of the output power Vo. Moreover, when the half-wave voltage Vh is close to the zero point (i.e. the input power is close to the zero point), a large number of switching times are required to raise the voltage value of the output power Vo to the upper limit value, so that the conversion efficiency is low when the input power is close to the zero point.

Therefore, how to design a power factor correction circuit with burst setting, which utilizes the burst setting circuit to set the time of burst operation of the power factor corrector, is a major topic to be studied by the present inventors.

Disclosure of Invention

To solve the above problems of the prior art, it is an object of the present invention to provide a power factor correction circuit with burst setting and a method for operating the same.

The main technical means adopted to achieve the above object is a power factor correction circuit with burst setting, which comprises a conversion circuit for receiving an input power supply, a control unit coupled to the conversion circuit and controlling the conversion circuit to convert the input power supply into an output power supply; and

a burst setting circuit coupled to the switching circuit and the control unit;

when the input power is at the positive half cycle rising edge, the positive half cycle falling edge, the negative half cycle rising edge and the negative half cycle falling edge, the burst setting circuit respectively sets at least one burst time interval, and provides a burst setting signal corresponding to the at least one burst time interval to the control unit, so that the control unit limits the switching circuit to carry out burst operation in the at least one burst time interval.

Preferably, the midpoint of the at least one burst period is not located between the zero point and the peak of the positive half cycle and the negative half cycle.

Preferably, the duration of the at least one burst period is proportional to the load of the conversion circuit.

Preferably, the at least one burst period of the positive half-cycle rising edge, the positive half-cycle falling edge, the negative half-cycle rising edge and the negative half-cycle falling edge are symmetrically arranged.

Preferably, the burst setting circuit includes:

a threshold generating circuit for providing at least one first threshold voltage and at least one second threshold voltage;

a first comparison circuit coupled to the threshold generation circuit and the conversion circuit;

a second comparator coupled to the threshold generating circuit and the converting circuit; and

a logic control circuit coupled to the comparison circuit and the control unit;

the first comparison circuit provides at least one first comparison signal to the logic control circuit according to the at least one first threshold voltage and a half-wave voltage corresponding to the input power supply, and the second comparison circuit provides at least one second comparison signal to the logic control circuit according to the at least one second threshold voltage and the half-wave voltage; the logic control circuit provides the burst setting signal to the control unit according to the at least one first comparison signal and the at least one second comparison signal.

Preferably, the logic control circuit sets an operation ending point of the at least one burst period of the positive half-cycle rising edge and the negative half-cycle falling edge and sets an operation starting point of the at least one burst period of the positive half-cycle falling edge and the negative half-cycle rising edge according to the at least one comparison signal.

Preferably, the logic control circuit sets the start point of the operation of the positive half-cycle rising edge and the negative half-cycle falling edge and sets the end point of the operation of the positive half-cycle falling edge and the negative half-cycle rising edge according to the at least one second comparison signal.

Preferably, the threshold generation circuit includes:

a threshold conversion circuit for receiving the at least one first threshold voltage;

the threshold conversion circuit converts the at least one first threshold voltage into the at least one second threshold voltage, and the at least one second threshold voltage is smaller than the at least one first threshold voltage corresponding to the at least one second threshold voltage.

Preferably, the threshold generating circuit obtains the at least one first threshold voltage from an external device, or the threshold generating circuit generates the at least one first threshold voltage by itself, or the threshold generating circuit is further coupled to the control unit, and the control unit obtains the at least one first threshold voltage.

Preferably, the logic control circuit comprises:

an edge value trigger circuit coupled to the first comparison circuit and the second comparison circuit;

an OR gate circuit coupled to the edge value trigger circuit; and

a flip-flop coupled to the OR gate;

wherein the edge triggering circuit provides at least one first edge triggering signal to the or gate circuit according to the at least one first comparison signal, and provides at least one second edge triggering signal to the or gate circuit according to the at least one second comparison signal; the OR gate circuit provides a logic signal to the flip-flop according to the at least one first edge trigger signal and the at least one second edge trigger signal, so that the flip-flop provides the burst setting signal to the control unit according to the logic signal.

Preferably, wherein the control unit comprises:

the comparison unit receives a feedback signal corresponding to the output power supply;

a multiplier coupled to the comparing unit and the converting circuit; and

a pulse width modulation unit coupled to the multiplier, the conversion circuit and the burst setting circuit;

wherein, the comparing unit provides an error signal to the multiplier according to the feedback signal and a reference voltage; the multiplier provides a control signal to the PWM unit according to a half-wave voltage corresponding to the input power and the error signal; the PWM unit provides a PWM signal to control the conversion circuit according to the control signal, and limits the PWM signal to be provided to the conversion circuit in the at least one burst period according to the burst setting signal so as to limit the conversion circuit to perform the burst operation in the at least one burst period.

Preferably, the conversion circuit includes:

a rectifying unit receiving the input power; and

the conversion unit is coupled with the rectification unit and comprises at least one power switch, and the at least one power switch is coupled with the control unit;

the rectifying unit is used for rectifying the input power supply into a half-wave voltage and filtering the half-wave voltage into a direct-current power supply; the control unit controls the conversion unit to convert the direct current power supply into the output power supply by controlling the switching conduction of the at least one power switch.

A method of operating a power factor correction circuit with burst setting, comprising the steps of:

(a) the control unit is used for controlling the conversion circuit to convert the input power supply into the output power supply;

(b) respectively setting at least one burst period when the input power is at a positive half-cycle rising edge, a positive half-cycle falling edge, a negative half-cycle rising edge and a negative half-cycle falling edge, and providing a burst setting signal corresponding to the at least one burst period; and

(c) the control unit limits the switching circuit to perform burst operation in a burst period according to the burst setting signal.

Preferably, wherein step (b) comprises:

(b1) providing at least one first comparison signal according to at least one first threshold voltage and a half-wave voltage corresponding to the input power supply;

(b2) providing at least one second comparison signal according to at least one second threshold voltage and the half-wave voltage; and

(b3) the burst setting signal is provided according to the at least one first comparison signal and the at least one second comparison signal.

Preferably, wherein step (b1) comprises:

(b11) the at least one first threshold voltage is converted into the at least one second threshold voltage, and the at least one second threshold voltage is smaller than the at least one first threshold voltage corresponding to the at least one second threshold voltage.

Preferably, wherein step (b3) comprises:

(b31) providing at least one first edge value trigger signal according to the at least one first comparison signal, and providing at least one second edge value trigger signal according to the at least one second comparison signal;

(b32) providing a logic signal according to the at least one first edge value trigger signal and the at least one second edge value trigger signal; and

(b33) the burst setup signal is provided according to the logic signal.

Preferably, wherein step (a) comprises:

(a1) the conversion circuit rectifies the input power supply into a half-wave voltage and filters the half-wave voltage into a direct current power supply;

(a2) the control unit controls the conversion circuit to convert the direct current power supply into the output power supply;

(a3) the control unit provides an error signal according to a feedback signal corresponding to the output power supply and a reference voltage;

(a4) the control unit provides a control signal according to a half-wave voltage corresponding to the input power supply and the error signal; and

(a5) the control unit provides a pulse width modulation signal to control the conversion circuit according to the control signal.

Preferably, wherein step (c) comprises:

(c1) the control unit limits the PWM signal to be provided to the conversion circuit in the at least one burst period according to the burst setting signal, so as to limit the conversion circuit to perform the burst operation in the at least one burst period.

The power factor correction circuit with burst setting of the invention uses the burst setting circuit to detect the waveform of the input power supply, and sets the specific time period for which the conversion circuit can carry out burst operation according to the waveform of the input power supply, so as to achieve the effect of greatly reducing the ripple voltage of the output power supply.

The invention sets the specific time interval of the switching circuit capable of carrying out burst operation at the non-zero point of the input power supply, so as to avoid the need of providing a longer burst time interval to improve the voltage value of the output power supply, and further achieve the effect of further improving the conversion efficiency of the power factor correction circuit.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.

FIG. 1 is a diagram of a burst mode waveform of a conventional PFC circuit;

FIG. 2 is a block diagram of a power factor correction circuit with burst setting according to the present invention;

FIG. 3 is a block diagram of the conversion circuit and the control unit according to the present invention;

FIG. 4A is a waveform diagram illustrating the operation of the PFC circuit with burst setting according to the first embodiment of the present invention;

FIG. 4B is a waveform diagram illustrating the operation of the PFC circuit with burst setting according to the second embodiment of the present invention; FIG. 5 is a block diagram of a burst setting circuit according to the present invention;

FIG. 6 is a waveform diagram of a burst setting circuit for setting a burst period according to the present invention; and

FIG. 7 is a circuit block diagram of the burst setting circuit according to the present invention.

In the figure, 100-power factor correction circuit, 1-conversion circuit, 12-rectification unit, 122-rectifier, Cin-input capacitance, 14-conversion unit, Qt-power switch, L-power inductance, 2-control unit, 22-comparison unit, 24-multiplier, 26-pulse width modulation unit, 3-burst setting circuit, 32-threshold generation circuit, 322-threshold conversion circuit, 34-first comparison circuit, 342-first comparator, 344-second comparator, 36-second comparison circuit, 362-third comparator, 364-fourth comparator, 38-logic control circuit, 382-edge trigger circuit, 382A-382D-upper edge trigger unit, 384-OR gate circuit, 384A-first OR gate, 384B-second OR gate, 386-trigger, R-reset terminal, S-set terminal, Q-output terminal, Q-input terminal, Q-output,

200-load, Vin-input power, Vo-output power, Vh-half wave voltage, Vd-DC power, Vref-reference voltage, Vr-ripple voltage, V1-preset value, V2-upper limit value, Vt 1-first threshold voltage, Vt 2-second threshold voltage, Io-output current, Il-inductor current, Sb-burst set signal, PWM-pulse width modulation signal, Sf-feedback signal, Se-error signal, Sh-half wave signal, Sc-control signal, Sp 1-first comparison signal, Sp 2-second comparison signal, Sm 1-first edge trigger signal, Sm 2-second edge trigger signal, Sl-logic signal, A-D-waveform, Tp-burst period, Ws-work start point, We-work end point.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention will be described in further detail with reference to the accompanying drawings in conjunction with the following detailed description. It should be understood that the description is intended to be exemplary only, and is not intended to limit the scope of the present invention. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present invention.