阅读说明：本技术 基于偏移的逻辑块映射 (Offset-based logical block mapping ) 是由 A·马尔谢 K·D·舒 于 2018-11-30 设计创作，主要内容包括：可基于与系统块相关联的存储器系统的特性来确定偏移。所述系统块对应于逻辑块。可将所述存储器系统的第一群组的物理块指派给所述系统块的所述多个逻辑块的群组。可在基于所述偏移及所述第一群组的物理块的位置处,识别所述存储器系统的第二群组的物理块。此外,可将所述存储器系统的所述第二群组的物理块指派给与所述系统块相关联的所述多个逻辑块的另一群组。可通过使用所述系统块而运用所述第一群组及第二群组的物理块来存储数据。(The offset may be determined based on characteristics of a memory system associated with the system block. The system block corresponds to a logic block. A first group of physical blocks of the memory system may be assigned to a group of the plurality of logical blocks of the system block. A second group of physical blocks of the memory system may be identified at a location based on the offset and the first group of physical blocks. Further, the second group of physical blocks of the memory system may be assigned to another group of the plurality of logical blocks associated with the system block. The first and second groups of physical blocks may be employed to store data using the system blocks.)

1. A method, comprising:

determining an offset based on a characteristic of a memory system associated with a system block corresponding to a plurality of logical blocks;

assigning a first group of physical blocks of the memory system to a group of the plurality of logical blocks corresponding to the system block;

identifying, by a processing device, a second group of physical blocks of the memory system at a location based on the offset and the first group of physical blocks;

assigning the second group of physical blocks of the memory system to another group of the plurality of logical blocks corresponding to the system block; and

storing data with the assigned first and second groups of physical blocks using the system blocks.

2. The method of claim 1, wherein the characteristic of the memory system corresponds to a number of memory devices included in the memory system and a number of planes included in each of the memory devices included in the memory system.

3. The method of claim 1, wherein the offset specifies a location of the second group of physical blocks relative to a location of the first group of physical blocks of the memory system.

4. The method of claim 1, wherein the assigning the first group of physical blocks and the second group of physical blocks comprises:

identifying, at a first die of a memory device of the memory system, the first group of physical blocks; and

identifying, at a second die, the second group of physical blocks, wherein the second group of physical blocks at the second die are at different index positions than the first group of physical blocks, the different index positions being based on the offset.

5. The method of claim 4, wherein the different index positions correspond to different rows at the second die relative to a row of the first die that includes the first group of physical blocks.

6. The method of claim 1, wherein the assigning the first group of physical blocks and the second group of physical blocks comprises:

identifying, at a first plane of a memory device of the memory system, the first group of physical blocks; and

identifying, at a second plane of the memory device, the second group of physical blocks, wherein the second group of physical blocks at the second plane are at different index positions than the first group of physical blocks at the first plane, the different index positions being based on the offset.

7. The method of claim 1, further comprising:

identifying subsequent system blocks corresponding to the additional plurality of logical blocks; and

assigning a particular group of physical blocks to a portion of the other plurality of logical blocks based on a location of the first group of physical blocks of the group of a plurality of logical blocks assigned to the system block.

8. A system, comprising:

a memory; and

a processing device operably coupled with the memory to:

determining an offset based on a characteristic of a memory system associated with a system block corresponding to a plurality of logical blocks;

assigning a first group of physical blocks of the memory system to a group of the plurality of logical blocks corresponding to the system block;

identifying a second group of physical blocks of the memory system at a location based on the offset and the first group of physical blocks;

assigning the second group of physical blocks of the memory system to another group of the plurality of logical blocks corresponding to the system block; and

storing data with the assigned first and second groups of physical blocks using the system blocks.

9. The system of claim 8, wherein the characteristics of the memory system correspond to a number of memory devices included in the memory system and a number of planes included in each of the memory devices included in the memory system.

10. The system of claim 8, wherein the offset specifies a location of the second group of physical blocks relative to a location of the first group of physical blocks of the memory system.

11. The system of claim 8, wherein to assign the first group of physical blocks and the second group of physical blocks, the processing device further:

identifying, at a first die of a memory device of the memory system, the first group of physical blocks; and

identifying, at a second die, the second group of physical blocks, wherein the second group of physical blocks at the second die are at different index positions than the first group of physical blocks, the different index positions being based on the offset.

12. The system of claim 11, wherein the different index positions correspond to different rows at the second die relative to a row of the first die that includes the first group of physical blocks.

13. The system of claim 8, wherein to assign the first group of physical blocks and the second group of physical blocks, the processing device further:

identifying, at a first plane of a memory device of the memory system, the first group of physical blocks; and

identifying, at a second plane of the memory device, the second group of physical blocks, wherein the second group of physical blocks at the second plane are at different index positions than the first group of physical blocks at the first plane, the different index positions being based on the offset.

14. The system of claim 8, wherein the processing device is further to:

identifying subsequent system blocks corresponding to the additional plurality of logical blocks; and

assigning a particular group of physical blocks to a portion of the other plurality of logical blocks based on a location of the first group of physical blocks of the group of a plurality of logical blocks assigned to the system block.

15. A non-transitory computer-readable medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising:

determining an offset based on a characteristic of a memory system associated with a system block, wherein the system block corresponds to a plurality of logical blocks;

assigning a plurality of groups of physical blocks of the memory system to the plurality of logical blocks of the system block based on the offset;

identifying new system blocks corresponding to the additional plurality of logical blocks;

identifying a further plurality of groups of physical blocks of the memory system based on the offsets and locations associated with the plurality of groups of physical blocks; and

assigning the additional plurality of groups of physical blocks to the additional plurality of logical blocks corresponding to the new system block.

16. The non-transitory computer-readable medium of claim 15, wherein the offset specifies a location of a particular group of physical blocks of a plurality of groups relative to a location of a previous group of physical blocks of a plurality of groups.

17. The non-transitory computer-readable medium of claim 15, wherein the characteristics of the memory system correspond to a number of memory devices included in the memory system and a number of planes included in each of the memory devices included in the memory system.

18. The non-transitory computer-readable medium of claim 15, wherein to identify a further plurality of groups of physical blocks of the memory system based on the offsets and the locations associated with the plurality of groups of physical blocks, the operations further comprise:

identifying a location of a physical block of an initial group of the plurality of groups of the plurality of logical blocks assigned to the system block; and

identifying a location of a particular group of physical blocks of the further plurality of groups relative to the location of the initial group of physical blocks.

19. The non-transitory computer-readable medium of claim 18, wherein to identify a further plurality of groups of physical blocks of the memory system based on the offsets and the locations associated with the plurality of groups of physical blocks, the operations further comprise:

identifying a subsequent group of physical blocks of the further plurality of groups based on the offset and the location of the particular group.

20. The non-transitory computer-readable medium of claim 15, wherein the operations further comprise:

using the system block and the new system block to store data received from a host system to the physical blocks of the memory system.

Technical Field

The present disclosure relates generally to a memory system, and more particularly, to logical block mapping based on offsets in a memory system.

Background

The memory system may be a storage system, such as a Solid State Disk (SSD), and may include one or more memory devices that store data. The memory system may include memory devices such as non-volatile memory devices and volatile memory devices. In general, a host system may utilize a memory system to store data at and retrieve data from memory devices of the memory system.

Drawings

The present invention will be understood more fully from the detailed description given below and from the accompanying drawings of various embodiments of the invention.

FIG. 1 illustrates an example computing environment including a memory system, according to some embodiments of the invention.

FIG. 2 is a flow diagram of an example method of assigning physical blocks of a memory system to logical blocks of system blocks, according to some embodiments.

FIG. 3A illustrates an example block mapping for a system block, according to some embodiments of the invention.

FIG. 3B illustrates another example block mapping for another system block, according to some embodiments of the invention.

FIG. 3C illustrates another example block mapping for another system block, according to some embodiments of the invention.

FIG. 3D illustrates another example block mapping for another system block, according to some embodiments of the invention.

Fig. 4 is a flow diagram of an example method of identifying a second group of physical blocks based on an offset and a location of a first group of physical blocks, according to some embodiments.

FIG. 5 is a block diagram of an example computer system in which embodiments of the present invention may operate.

Detailed Description

A host system may utilize a memory system that includes one or more memory devices. The host system may provide write requests to store data at the memory system and may provide read requests to retrieve data at the memory system. The host system may use the mapping of logical blocks to physical blocks of the memory device to write data to and read data from the memory system. For example, each logical block may map to a particular physical block at a particular memory device of the memory system. When a host system identifies an address of a particular logical block to write data to or read data from, data may be written to or read from a physical block mapped to the identified logical block. Thus, a host system may identify a logical block to store or retrieve data, and corresponding data may be stored at or retrieved from a physical block mapped to the logical block. Different logical blocks may be mapped to different physical blocks included at different memory devices in the memory system.

Conventional memory systems may manage the mapping between logical blocks specified by the host system and physical blocks of the memory device. For example, the memory system may determine which physical blocks should be mapped to particular logical blocks. The memory system may further manage the writing of data from the host system to the memory devices of the memory system by using system blocks, which are groups of logical blocks. The system blocks may correspond to logical blocks operated as groups by the memory system. Such operations may include, but are not limited to, erase operations that, when performed on a system block, may result in an erase operation being performed on each physical block mapped to a logical block of the system block. The system blocks may be data stripes managed by the memory system. For example, a stripe may be a sequence of blocks of user data that have been received from a host system and stored as a group at a memory system. Thus, a system block may be a logical block of user data that has been grouped together by a memory system.

When the memory system receives a write request from the host system, the data may be stored within the logical block assigned to the particular system block. Once the logical blocks assigned to the particular system block are each used to store data at the corresponding physical block (e.g., the particular system block is full), the memory system may store subsequent data at the new system block. For example, a new logical block may be mapped to a new physical block for the new system block. Thus, data may be stored at memory devices of a memory system in different groups of logical blocks.

As previously described, logical blocks may be mapped to physical blocks of a memory device included in a memory system. Logical blocks may be mapped to physical blocks in an order across memory devices in a conventional memory system. For example, logical blocks may be mapped to physical blocks in an order of physical locations of the physical blocks across a memory device (e.g., across a row of physical blocks of a memory device). A particular memory device may include a manufacturing defect, wherein as part of the manufacturing process, a particular physical block may be defective and unable to store data. If logical blocks of a system block are mapped to physical blocks in the order in which the physical blocks are positioned in a row of a memory device, and if a group of physical blocks that are close to each other cannot store data due to a manufacturing defect, a large number of logical blocks of the system block may be mapped to a large number of defective physical blocks that cannot store data. A system block that includes a large number of defective physical blocks may be associated with reduced performance because the processing power of the memory system may be reduced due to the defective physical blocks. For example, when the number of defective physical blocks of a logical block assigned to a particular system block exceeds a threshold number, another mapping of other logical blocks to other physical blocks may be employed to reallocate data at the remaining physical blocks of the logical block assigned to the particular system block to another system block. This reallocation of data from the physical block to other physical blocks mapped to other logical blocks of another system block may take a significant amount of time, during which the data being reallocated may not be accessible in response to a read operation provided by the host system. Further, the reallocation of data may correspond to writing data from a previous physical block to one of the other physical blocks, which may result in delaying other write operations provided by the host system as a result of performing write operations of data from the previous physical block to another physical block for the conventional memory system.

Aspects of the present disclosure address the above and other deficiencies by assigning a diagonal block mapping or arrangement between logical blocks and physical blocks such that physical blocks assigned to logical blocks of system blocks are distributed across different portions of a memory device or different portions of multiple memory devices. For example, instead of mapping logical blocks to physical blocks in a physical order across rows (or columns or other such arrangement) of a memory device, a diagonal block mapping may map logical blocks of system blocks to physical blocks across different locations within a memory device. For example, mapping logical blocks to physical blocks that span different locations at different memory devices may result in a first number of logical blocks of system blocks being mapped to a first number of physical blocks at a first memory device, where the first number of physical blocks are located in a first location or row of the first memory device. A second number of logical blocks may be mapped to a second number of physical blocks at a second memory device, where the second number of physical blocks are located in a second location or row of the second memory device. Thus, a system block may include logical blocks that map to physical blocks distributed across different rows or locations of different memory devices.

In another example, a diagonal block mapping may map logical blocks of a system block to physical blocks across different planes of a single memory device. Each plane of a memory device may correspond to a portion of the memory device (e.g., a portion of a physical block) and may be capable of independently performing the same operation (e.g., a write operation, a read operation, or an erase operation on a physical block in the same plane) that occurs simultaneously. This diagonal block mapping may result in a first number of logical blocks of system blocks being mapped to a first number of physical blocks at a first memory device, where the first number of physical blocks are positioned in a first location or row at a plane of a first group of the first memory device. The second number of logical blocks may be mapped to a second number of physical blocks at the same first memory device, where the second number of physical blocks may be located in a second location or row at a plane of a second group of the same first memory device. Subsequently, a third number of logical blocks may be mapped to a third number of physical blocks at a third location or row (e.g., different from the first or second rows) at a different second memory device. Thus, logical blocks assigned to a single system block may include physical blocks at different planes of different memory devices. Additional details regarding mapping logical blocks to physical blocks are described below.

Mapping logical blocks to physical blocks based on a diagonal block mapping may be based on an offset, which is determined based on characteristics of the memory system. For example, the offset may be determined based on the number of physical blocks included in each memory device and the number of planes included in each memory device. The offset may be used to determine the shape or path of the diagonal block map for the system block. In some embodiments, the diagonal mapping may be based on memory device offsets that define which portions of the memory device may be assigned to the system blocks, plane offsets that may define which portions of the plane are assigned to the system blocks, and/or diagonal offsets that may define which portions of the plane and memory device are assigned to the system blocks. For example, such offset values may specify locations or rows of physical blocks assigned to different groups of system blocks.

Advantages of the present invention include, but are not limited to, improved performance of the memory system. For example, diagonal block mapping may result in defective physical blocks being more evenly distributed among the various system blocks, as such defective physical blocks may be close to each other at a single location within a single memory device. Accordingly, fewer reallocation operations may be performed because fewer system blocks may be indicated as unavailable when a threshold number of defective physical blocks have been assigned to the corresponding system block. Thus, the processing power of the memory system may be increased (e.g., write, read, or erase operations may be performed faster), and additional capacity of the memory system may be utilized when physical blocks assigned to system blocks may not be indicated as being unable to frequently store data.

FIG. 1 illustrates an example computing environment 100 including a memory system 110, according to some implementations of the invention. Memory system 110 may include media, such as memory devices 112A-112N. The memory devices 112A-112N may be volatile memory devices, non-volatile memory devices, or a combination of the like. In some embodiments, the memory system is a storage system. An example of a storage system is an SSD. In general, the computing environment 100 may include a host system 120 that uses a memory system 110. In some implementations, the host system 120 can write data to the memory system 110 and read data from the memory system 110. In some embodiments, memory system 110 is a hybrid memory/storage system.

The host system 120 may be a computing device, such as a desktop computer, a laptop computer, a network server, a mobile device, or such a computing device that includes memory and a processing device. The host system 120 may include or be coupled to the memory system 110 such that the host system 120 can read data from the memory system 110 or write data to the memory system 110. The host system 120 may be coupled to the memory system 110 via a physical host interface. As used herein, "coupled to" generally refers to a connection between components that may be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, and the like. Examples of physical host interfaces include, but are not limited to, serial advanced attachment technology (SATA) interfaces, peripheral component interconnect express (PCIe) interfaces, Universal Serial Bus (USB) interfaces, fibre channel, serial attached scsi (sas), and the like. The physical host interface may be used to transfer data between the host system 120 and the memory system 110. The host system 120 may further utilize an NVM express (NVMe) interface to access the memory devices 112A-112N when the memory system 110 is coupled with the host system 120 over a PCIe interface. The physical host interface may provide an interface for passing control, address, data, and other signals between the memory system 110 and the host system 120.

Examples of non-volatile memory devices include NAND (NAND) type flash memories each of memory devices 112A-112N may include one or more arrays of memory cells, such as single-level cells (S L C) or multi-level cells (M L C), such as three-level cells (T L C) or four-level cells (Q L C), in some implementations, a particular memory device may include both the S L C portion and the M L C portion of memory cells, each of the memory cells may store data bits, such as data blocks, for use by host system 120, although non-volatile memory devices, such as NAND type flash memories, are described, memory devices 112A-112N may be based on any other type of memory, such as volatile memories, in some implementations, memory devices 112A-112N may refer to, but are not limited to, cross-points (cross-point) memory Devices (DRAM), and/or random access memory arrays, where random access memory devices may be based on non-volatile read-access memory cells, read-write-access memory arrays, random access memory devices, random access memory arrays, or non-random access memory arrays, wherein random access memory arrays may be based on the like nonvolatile memory arrays, wherein random access memory cells may be based on non-read-random access memory cells, non-read-random access memory arrays, or non-random access memory arrays, wherein the like nonvolatile memory arrays, wherein nonvolatile memory arrays, non-random access memory arrays, wherein nonvolatile memory arrays may be based on non-random access memory cells may be.

The controller 115 may communicate with the memory devices 112A-112N to perform operations, such as reading data, writing data, or erasing data at the memory devices 112A-112N, and other such operations. The controller 115 may include hardware, such as one or more integrated circuits and/or discrete components, a buffer memory, or a combination thereof. The controller 115 may be a microcontroller, special purpose logic circuitry (e.g., a Field Programmable Gate Array (FPGA), Application Specific Integrated Circuit (ASIC), etc.), or other suitable processor. The controller 115 may include a processor (processing device) 117 configured to execute instructions stored in a local memory 119. In the illustrated example, the local memory 119 of the controller 115 includes embedded memory configured to store instructions for executing various processes, operations, logic flows, and routines that control the operation of the memory system 110, including handling communications between the memory system 110 and the host system 120. In some embodiments, local memory 119 may include memory registers that store memory pointers, fetched data, and so forth. Local memory 119 may also include Read Only Memory (ROM) for storing microcode. Although the example memory system 110 in FIG. 1 has been illustrated as including the controller 115, in another embodiment of the present disclosure, the memory system 110 may not include the controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory system).

In general, the controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory devices 112A-112N. The controller 115 may be responsible for other operations, such as wear leveling operations, garbage collection operations, error detection and Error Correction Code (ECC) operations, encryption operations, high speed access operations, and address translation between logical block addresses and physical block addresses associated with the memory devices 112A-112N. The controller 115 may further include host interface circuitry that communicates with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system into command instructions to access the memory devices 112A-112N and convert responses associated with the memory devices 112A-112N into information for the host system 120.

The memory system 110 may include a map 113 (e.g., circuitry, dedicated logic, programmable logic, firmware, etc.) that performs the operations described herein. In some implementations, mapping component 113 can determine an offset to be used when mapping logical blocks of system blocks to physical blocks of memory devices 112A-112N. For example, mapping component 113 may identify a number of physical blocks in memory devices 112A-112N and/or a number of planes in memory devices 112A-112N. The identified number of physical blocks and/or the number of planes may then be used to specify an offset for mapping the physical blocks in the diagonal position to the logical blocks of the system blocks.

The memory system 110 may also include additional circuits or components not illustrated. In some implementations, the memory system 110 can include a cache or buffer (e.g., DRAM) and address circuitry (e.g., row decoder and column decoder) that can receive addresses from the controller 115 and decode the addresses to access the memory devices 112A-112N.

FIG. 2 is a flow diagram of an example method 200 of assigning physical blocks of a memory system to logical blocks of system blocks, according to some embodiments of the invention. Method 200 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 200 may be performed by the mapping component 113 of FIG. 1.

As shown in fig. 2, at block 210, processing logic may receive an indication that a group of physical blocks associated with the memory system is allocated to a logical block of system blocks. The indication may be that the host system is providing data to be written to a physical block at one or more memory devices of the memory system. In some embodiments, the indication may be that each of the logical blocks of the previous system block has been used to store data from the host system. A system block may be a group of logical blocks that map to physical blocks that store data provided by the host system.

At block 220, processing logic may identify a first group of physical blocks associated with the memory system. The first group of physical blocks may not currently store data from the host system. In some embodiments, the memory system may include a plurality of memory devices, and the first group of physical blocks may be from a single memory device of the plurality of memory devices included in the memory system.

At block 230, processing logic may determine an offset based on the characteristics of the memory system. The offset may be used to specify the location of the other physical block relative to the location of the first group of physical blocks. In some embodiments, the offset may be based on the number of physical blocks included in each memory device and the number of planes included in each memory device in the memory system. In the same or alternative embodiments, the offset may be based on the number of memory devices or dies included in the memory system. The use of offset is described further below.

Referring to FIG. 2, at block 240, processing logic may identify a second group of physical blocks associated with the memory system based on the offset. The physical blocks from the second group may not currently store data from the host system. Further, the data chunks of the second group may be at a location or position in the memory system relative to a location (position) or position (location) of the data chunks of the first group. For example, the location of the first physical block of the second group may be based on the location and offset of the last physical block of the first group. The offset may be used to specify that physical blocks at a particular row of a particular memory device should be included in a second group relative to the location of the first group. The second group of locations may be at different memory devices, different planes and/or different rows of memory devices, as described in further detail with respect to fig. 3A-3D.

Processing logic may then assign the first and second groups of physical blocks to logical blocks of system blocks at block 250. Thus, the assignment of physical blocks to logical blocks of a system block may be based on the offset and the location of physical blocks that have been assigned to previous groups of logical blocks.

At block 260, processing logic may further provide a mapping of logical blocks of system blocks to physical blocks of the first group and the second group to the host system. For example, after assigning a physical block group to each of the logical blocks of the system block, the system block may be used to store data from the host system. For example, when new data is received from a host system for storage at a memory system, the new data may be stored at a physical block of a logical block assigned to the system block. Subsequently, the host system may then retrieve the data stored at the physical block by identifying the logical block address assigned to the corresponding logical block of the physical block.

Although fig. 2 depicts physical blocks of the first and second groups being assigned to logical blocks of the system block, any number of groups of physical blocks may be assigned to logical blocks of the system block.

FIG. 3A illustrates an example block mapping 300 for system blocks, according to some embodiments of the invention. Block mapping 300 can be performed by mapping component 113 of FIG. 1.

As shown in fig. 3A, block map 300 may represent physical blocks at a memory device of a memory system that are assigned to logical blocks of system blocks. For example, a memory system may include a plurality of memory devices, such as memory device 301 (e.g., memory device "0" as represented by the top row), memory device 302 (e.g., memory device "1"), memory device 303 (e.g., memory device "2"), and memory device 304 (e.g., memory device "3"). Each of memory devices 301, 302, 303, and 304 may include a row of physical blocks mapped to a logical block of a system block. For example, a first group of physical blocks 310 at row "0" of the memory device 301 may be assigned to the first four logical blocks of a system block.

The offset of block map 300 may specify that the next physical block assigned to the system block may be at the next row of the next memory device (or another such index location indicating a particular location within the memory device) relative to the first group of physical blocks 310. For example, the offset may specify that the next memory device 302 and the second group of physical blocks 311 at row "1" incremented by a value from row "0" are the next physical blocks assigned to the next four logical blocks of the system block. Similarly, the offset may specify that a third group of physical blocks 312 at the next row "2" at the next memory device 303 should be assigned to the next four logical blocks of the system block, and a fourth group of physical blocks 313 at the next memory device 304 and the next row "3" relative to the third group of physical blocks 312 should be assigned to the last four logical blocks of the system block. Thus, the offset may specify that subsequent groups of physical blocks at the next incremental column at the next memory device relative to the previously assigned groups of physical blocks should be assigned as the next logical blocks of the system block.

Further, after each logical block of a system block has been assigned to a physical block of memory devices 301, 302, 303, and 304, logical blocks of another system block may be assigned to other groups of physical blocks. For example, other groups of physical blocks may be at rows below physical block groups 310, 311, 312, and 313. For example, row "1" of memory device 301, row "2" of memory device 302, row "3" of memory device 303, and row "4" of memory device 304 may be assigned to a logical block of another system block.

FIG. 3B illustrates another example block mapping 320 of another system block, according to some embodiments of the invention. Block mapping 320 can be performed by mapping component 113 of FIG. 1. As shown, the offset may specify that physical blocks of a subsequent group of logical blocks to be assigned to another system block should be located at the next memory device and at two rows of physical blocks from a previous group of logical blocks already assigned to the system block. Thus, the offset may be used to specify physical blocks to be assigned to different rows of the logical block.

FIG. 3C illustrates another example chunk mapping 330 of another system chunk that may be performed by mapping component 113 of FIG. 1, according to some embodiments of the invention. As shown, the offset may specify that physical blocks of a subsequent group of logical blocks to be assigned to the system block should be positioned at a next row relative to physical blocks of a previous group of logical blocks already assigned to the system block. The offset may further specify that the next row may be at a different plane within the same memory device that includes the previous group of physical blocks. For example, each memory device may include two groups of physical blocks to be assigned to system blocks, with a first group at a particular row within the memory device and at two planes of the memory device (e.g., plane "0" and plane "1" as represented by the second row), and a second group at the next row within the same memory device and at the other two planes of the same memory device (e.g., planes "2" and "3"). The subsequent group may then be at the next row relative to the next memory device of the second group at planes similar to the physical blocks of the first group (e.g., planes "0" and "1" of the next memory device). Further, the number of physical blocks in each group in the logical blocks assigned to the system block may be based on the offset. For example, as shown, the offset may further specify that the size of each group of physical blocks is two physical blocks, as opposed to four physical blocks as illustrated in fig. 3B and 3A.

As previously described, each plane of a memory device may correspond to a portion of a physical block of the memory device and may be capable of independently performing the same operations occurring at the same time. In the representations of the memory devices from fig. 3A-3D, a plane may be represented by each column of the memory device. For example, physical blocks "0", "4", "8", "12", "16", "20", "24", and "28" may be within the same plane of a particular memory device.

Fig. 3D illustrates another example block mapping 340 of another system block according to some embodiments of the invention. Block mapping 340 may be performed by mapping component 113 of FIG. 1. As shown, the offset may specify that subsequent physical blocks to be assigned to a logical block of the system block should be located at two rows in the next plane from previous physical blocks already assigned to previous logical blocks of the system block. In some embodiments, the offset may specify that after physical blocks from each plane of the memory device have been assigned to logical blocks of the system blocks, then physical blocks at a first plane of a next memory device may be assigned to a next logical block of the system blocks.

Thus, the offset may specify one or both of a memory device offset for specifying a next memory device of a next group of physical block groups assigned to a logical block of the system block, a plane offset that may be used to specify a next plane in the memory device of the next group of physical blocks to be assigned, and/or a row offset that may be used to specify a new row in the memory device of the next group of physical blocks to be assigned. Thus, the offset may be used to specify different index positions (e.g., rows) between a group of physical blocks and a next group of physical blocks.

Fig. 4 is a flow diagram of an example method 400 of identifying a second group of physical blocks based on an offset and a location of a first group of physical blocks, according to some embodiments of the invention. The method 400 may be performed by processing logic that may comprise hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, integrated circuits, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the method 400 may be performed by the mapping component 113 of FIG. 1.

As shown in fig. 4, at block 410, processing logic may identify a first system block having a logical block that has been assigned to a physical block of the memory system based on the offset. For example, each logical block of a first system block may be mapped to a physical block of the memory system.

At block 420, processing logic may receive a request to assign a physical block to a logical block of a second system block. The request may be assigned to a physical block of the memory system in response to each of the logical blocks of the first system block. For example, the second system block may be identified after the first system block has been assigned to a physical block of the memory system.

At block 430, processing logic may then identify a location of a physical block of the first group of logical blocks assigned to the first system block. For example, a row of a first memory device including a first group of physical blocks may be identified. A first group of physical blocks may be assigned to a first logical block of a first system block.

At block 440, processing logic may assign another group of physical blocks to logical blocks of the second system block based on the location of the first group of physical blocks assigned to logical blocks of the first system block. For example, another group of physical blocks of a logical block assigned to a second system block may be at a row within the same first memory device below a first physical block assigned to a first system block. Further, another group of physical blocks may be assigned to the first logical block of the second system block. The first group of physical blocks and the other group of physical blocks may include the same number of physical blocks.

At block 450, processing logic may determine a subsequent group of physical blocks to assign to subsequent logical blocks of the second system block based on the offset. The offset used to assign the physical block to a subsequent logical block of the second system block may be the same offset used to identify the physical block assigned to the logical block of the first system block. Thus, the same offset may be used to identify a physical block for a subsequent group of different system blocks. For example, the offset may be used to identify the location of the subsequent group of physical blocks relative to the location of the previous group of physical blocks for the subsequent system block.

Fig. 5 illustrates AN example machine of a computer system 500 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed, hi some implementations, the computer system 500 may correspond to a host system (e.g., host system 120 of fig. 1) that includes or utilizes a memory system (e.g., memory system 110 of fig. 1) or may be used to perform operations of a controller (e.g., execute AN operating system to perform operations corresponding to mapping component 113 of fig. 1), hi alternative implementations, a machine may be connected (e.g., networked) to L AN, AN internal network, AN external network, and/or other machines in the internet.

The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Further, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

Example computer system 500 includes a processing device 502, a main memory 504 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM), such as synchronous DRAM (sdram) or Rambus DRAM (RDRAM), etc.), a static memory 506 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a data storage system 518, which communicate with each other via a bus 530.

Processing device 502 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like, more particularly, a processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a very long instruction word (V L IW) microprocessor, or a processor implementing other instruction sets, or a processor implementing a combination of instruction sets, processing device 502 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), a network processor, or the like, processing device 502 is configured to execute instructions 526 for performing the operations and steps discussed herein, computer system 500 may further include a network interface device 508 that communicates via a network 520.

The data storage system 518 may include a machine-readable storage medium 524 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions or software 526 that implement any one or more of the methodologies or functions described herein. The instructions 526 may also reside, completely or at least partially, within the main memory 504 and/or within the processing device 502 during execution thereof by the computer system 500, the main memory 504 and the processing device 502 also constituting machine-readable storage media. The machine-readable storage medium 524, data storage system 518, and/or main memory 504 may correspond to memory system 110 of fig. 1.

In one implementation, the instructions 526 include instructions to implement functionality corresponding to a mapping component (e.g., the mapping component 113 of fig. 1). While the machine-readable storage medium 524 is shown in an example implementation to be a single medium, the term "machine-readable storage medium" should be taken to include a single medium or multiple media that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

Some portions of the preceding detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived to be a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present invention may be directed to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage systems.

The present invention also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the desired purposes, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer readable storage medium, such as, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), Random Access Memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions, and each coupled to a computer system bus.

The algorithms and displays presented herein are not inherently related to any particular computer or other apparatus. Various general-purpose systems may be used with programs in accordance with the teachings herein, or it may prove convenient to construct a more specialized apparatus to perform the methods. The structure for a variety of these systems will appear as set forth in the description below. In addition, the present invention is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages may be used to implement the teachings of the invention as described herein.

The present invention may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to the present invention. A machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some implementations, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) -readable storage medium, such as read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, and so forth.

In the foregoing specification, embodiments of the invention have been described with reference to specific example embodiments thereof. It will be evident that various modifications may be made thereto without departing from the broader spirit and scope of embodiments of the invention as set forth in the following claims. The specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.