阅读说明：本技术 用于在数字信号采样时限制损耗功率的装置 (Device for limiting power loss during digital signal sampling ) 是由 安德烈亚斯·帕策尔特 克里斯蒂安·佛斯 于 2020-01-06 设计创作，主要内容包括：本发明涉及用于在数字信号采样时限制损耗功率的装置。所述装置包括布置在数字信号的信号路径中的电路,其中,所述电路设置成,响应于表明采样暂停的控制信号,减小沿着信号路径的电流。(The invention relates to an arrangement for limiting the power loss when sampling a digital signal. The apparatus comprises a circuit arranged in a signal path of the digital signal, wherein the circuit is arranged to reduce a current along the signal path in response to a control signal indicating a sampling pause.)

1. Apparatus (10) for limiting power loss when sampling a digital signal (D), the apparatus comprising a circuit (16) arranged in a signal path (18) of the digital signal (D), wherein the circuit (16) is arranged to reduce a current (I) along the signal path (18) in response to a control signal (S) indicating a sampling pause (P).

2. The device (10) according to claim 1, wherein the circuit has a current limiting circuit (22) and the current consumption of the current limiting circuit (22) is varied by a switching element, which is controlled by a control signal.

3. The device (10) according to claim 1 or 2, wherein the current limiting circuit (22) has an input resistance (28) and the current (I) through the current limiting circuit (22) is limited by the input resistance (28) in order to reduce the power loss.

4. The device (10) according to any of claims 1 to 3, wherein the digital signal (D) comprises current levels/voltage levels in a low current level range/voltage level range and a high current level range/voltage level range, and the device is arranged to generate the control signal (S) indicating the sampling pause (P) when the sampled value is in the high current level range/voltage level range, and not generate the control signal (S) indicating the sampling pause (P) when the sampled value is in the low current level range/voltage level range.

5. The device (10) according to claim 4, wherein the device (10) is arranged to sample the digital signal (D) at a specific point in time, to detect the sampled values and to generate a control signal (S) indicating a sampling pause when the generated sampled values are in a high current level range/voltage level range, wherein the current level/voltage level of the digital signal (D) along the signal path (18) during the sampling pause (P) is reduced by the device (10) in order to limit the power loss.

6. The apparatus (10) of claim 5, wherein a current level of the digital signal (D) along the signal path (18) during a sampling pause (P) is reduced by the apparatus (10) in order to limit a power loss.

7. The apparatus (10) according to any one of claims 1 to 6, further comprising:

a microcontroller (12); and

a memory element (30) having a memory element,

wherein the device (10) is configured to store a sample value in the storage element (30) in response to a request signal of the microcontroller (12) and to indicate a sampling pause (P) after the storage until a next request signal is generated by the microcontroller (12).

8. The device (10) according to claim 7, wherein the device (10) is arranged to generate the control signal (S) indicating a sampling pause (P) when the sampling pause (P) is indicated and the sample value stored in the storage element (30) corresponds to a high level.

9. The device (10) according to any one of claims 1 to 8, wherein the device (10) comprises a switching element which, when the control signal (S) indicating a sampling pause (P) is applied on a control input of the switching element, closes a conductive connection between the signal path (18) and ground.

10. The device (10) according to any one of claims 1 to 9, wherein the device (10) is arranged to generate a sample value and to determine whether the device (10) is operating erroneously based on the sample value during a sampling pause (P) indicated by the control signal (S).

Technical Field

The invention relates to an arrangement for limiting the power loss when sampling a digital signal.

Background

In the sampling of the digital signal, a voltage representing the digital signal or a current representing the digital signal is measured at a specific point in time and assigned to a signal value representing a value range, for example a high or low level.

Disclosure of Invention

In this respect, the invention enriches the prior art because the arrangement according to the invention reduces the power loss when sampling the digital signal, which is achieved by reducing the current along the signal path when sampling is suspended.

To this end, the device according to the invention comprises a circuit arranged in the signal path of the digital signal, wherein the circuit is arranged to reduce the current along the signal path in response to a control signal indicating a sampling pause.

The term "signal path" as used in the description and claims is understood here to mean, in particular, a conductive connection (during sampling) between a circuit that generates a digital signal (transmitter) and a circuit that receives the digital signal (receiver), through which the sampling takes place. For example, the circuit may be located upstream of the digital input and only "conduct" the digital signal after the signal applied at the input is actually read in. In particular, the signal at the input can be read in periodically (for example, controlled by a timer) so that there is a (sampling) pause during the read-in time, when no signal is read in.

Furthermore, the term "control signal" as used in the description and in the claims is to be understood in particular as an electrical signal, for example a component (for example a transistor) that controls electronics, by means of which the circuit can be switched from a first mode in which a digital signal is (substantially) "conducted" to a second mode in which the current to the input is reduced. The control signal has, for example, a first voltage during the (sampling) pause and a second voltage at the read-in time (which is, for example, higher than the first voltage).

Furthermore, the term "sampling" as used in the description and in the claims is to be understood in particular as measuring a digital signal and assigning a digital signal to a signal value. In this context, the term "sampling pause" as used in the description and in the claims is to be understood in particular as a time interval during which the digital signal is not measured and assigned to a signal value, or during which an already made assignment is not further used (i.e. ignored and covered continuously).

The circuit preferably has a current limiting circuit and the current limiting circuit is varied by means of a switching element, which is controlled by means of a control signal.

The current limiting circuit preferably has an input resistor, wherein the current through the current limiting circuit is limited by the input resistor in order to reduce the power loss.

The digital signal preferably comprises current levels/voltage levels in a low current level range/voltage level range and a high current level range/voltage level range. The device is designed to generate a control signal indicating a sampling pause when the sampled value is in the high current level range/voltage level range, and not to generate a control signal indicating a sampling pause when the sampled value is in the low current level range/voltage level range.

The device is preferably designed to sample the digital signal at a specific point in time, to detect the sampled value and to generate a control signal indicating a sampling pause when the sampled value lies in a high current level range/voltage level range, wherein the current level/voltage level of the digital signal along the signal path during the sampling pause is reduced by the device in order to limit the power loss.

Preferably, the current level of the digital signal along the signal path during the sampling pause is reduced by said means in order to limit the power loss.

The device preferably comprises a microcontroller and a memory element and is configured to store a sample value in the memory element in response to a request signal from the microcontroller and to indicate a pause in sampling after storage until the next request signal is generated by the microcontroller.

The device is preferably configured to generate the control signal indicating a sampling pause when the sampling pause is indicated and the sample value stored in the memory element corresponds to a high level.

The device preferably comprises a switching element which, when a control signal indicating a sampling pause is applied to a control input of the switching element, closes an electrically conductive connection between the signal path and ground.

The device is preferably configured to generate a sample value during a sampling pause indicated by the control signal and to determine whether the device is operating incorrectly based on the sample value.

Drawings

The invention is explained below in the detailed description by means of embodiments, wherein reference is made to the appended drawings, in which:

fig. 1 shows a block diagram of an apparatus according to the invention;

FIG. 2 shows a block diagram of another apparatus according to the invention;

fig. 3 shows a circuit diagram of a current limiting circuit comprised in the device according to the invention;

FIG. 4 illustrates a process of detecting errors;

FIG. 5 illustrates a manner of processing in generating a control signal; and

fig. 6 shows another way of processing when generating the control signal.

Identical or functionally similar elements are denoted by the same reference numerals in the figures.

Detailed Description

Fig. 1 shows a block diagram of an apparatus 10 according to the invention. The device 10 comprises a receiver 12, for example a microcontroller, and a circuit 16 upstream of an input 14 of the receiver 12. The circuit 16 is arranged to reduce the current I along the signal path 18 in response to a control signal S of the receiver 12 indicating a sampling pause P by interrupting the signal path 18 by means of the switch 16 a. Thereby reducing the power loss when the digital signal D output by the transmitter 20 is sampled.

This arrangement is particularly advantageous when it is not possible/suitable to switch off the transmitter 20 (e.g. a sensor) in the sampling pause P, for example because the transmitter 20 requires a constant energy supply in order to function properly. Furthermore, as shown in fig. 2, a resistor is arranged in parallel with the switch 16a, so that the current also does not completely stop during the sampling pause P and the input 14 does not have current during the sampling pause P. The read-in sampled values can then be stored in the memory element 30 of the receiver 12, wherein the memory element 30 is overwritten with the new (current) value at each sampling. In addition, the receiver 12 can read the sampled values from the storage element 30 at any time and further process them.

Fig. 3 shows a circuit diagram of a possible embodiment of the current limiting circuit 22 included in the device 10 according to the invention. The current limiting circuit 22 comprises a first transistor 24 arranged in the signal path, which transistor is opened or closed by means of a control signal S. If a sufficiently high switching voltage is applied to the base of the second transistor 26, said second transistor is turned on, thereby reducing the voltage applied to the base of the first transistor 24. By lowering the base voltage, the first transistor 24 becomes high-resistive and the current I through the first transistor 24 decreases (sampling pause P).

In contrast, if the voltage applied to the base of the second transistor 26 is lowered during the sampling phase a, the second transistor 26 becomes high-resistance, and thus the voltage applied to the base of the first transistor 24 rises. Thereby, the first transistor 24 becomes low-resistance and the current I through the first transistor 24 rises. The current I occurring through the first transistor 24 is adapted to the input 14 of the receiver 12 by means of the parameters of the resistor 28. Thus, an input voltage of, for example, 220 volts is converted into an output voltage of 11 volts, whereby the input 14 is realized with low-power components.

Furthermore, as shown in fig. 4, it is checked whether the input 14 of the receiver 12 functions correctly. For example, if the signal Iein read in by the receiver 12 exhibits no change despite the transition between the sampling pause P and the sampling phase a, it follows that the input 14 of the receiver 12 does not function correctly. This is advantageous in particular when the receiver 12 is safety-relevant.

Furthermore, as shown in fig. 5, if the sample value Iein corresponds to a low level, the display of the respective sample pause P can be suppressed (by means of the control signal S). Thereby, the switching effort can be reduced without a significant increase in the power loss, since the power loss occurring at low levels, at which the current level/voltage level of the digital signal D is in the low current level range/voltage level range, is significantly lower than at high levels, at which the digital signal is in the high current level range/voltage level range. Further, as shown in fig. 6, when a high level is read in and stored in the memory 30 of the receiver 12, the sampling phase a may be terminated immediately, whereby the power loss may be further reduced.

List of reference numerals

10 device

12 receiver (microcontroller)

14 input terminal

16 circuit

18 signal path

20 transmitter (sensor)

22 current limiting circuit

24 transistor

26 transistor

28 resistor

30 storage element

A sampling phase

D digital signal

I current

P sample pause

S control signal

U1 input voltage

U2 output voltage