阅读说明：本技术 一种计算机的无线通讯信号抗干扰装置 (Wireless communication signal anti-jamming device of computer ) 是由 张洪明 张义明 丛琳 于 2020-04-10 设计创作，主要内容包括：本发明的一种计算机的无线通讯信号抗干扰装置,所述帧同步头脉冲判决电路采用异或门U3对接收的帧同步头脉冲信号和帧同步脉冲发生器产生的帧同步脉冲信号进行同出0、异出1的逻辑运算,运算后的0或1驱动互补三极管转换为低电平或高电平的确定脉冲信号后输出到脉冲电压转换电路,经频率电压转换器转换为与脉冲信号线性的直流电压,实现比较匹配的脉冲个数越多、越精确,转换后电压越低,送入增益调节控制电路,通过运算放大器AR2对直流电压和误码率修正后的帧同步头同步电压进行比较,输出高或低电平控制接收器增益调节电路进行相应的非高增益或高增益的接收,以此避免发射方没有数据发射时,接收器高增益接收会收到干扰信号和误码率高问题。(The invention relates to a wireless communication signal anti-interference device of a computer, wherein an XOR gate U3 is adopted by a frame synchronization head pulse judgment circuit to perform logic operation of same-out 0 and different-out 1 on a received frame synchronization head pulse signal and a frame synchronization pulse signal generated by a frame synchronization pulse generator, a 0 or 1 after operation drives a complementary triode to be converted into a low-level or high-level determined pulse signal and then output to a pulse voltage conversion circuit, the determined pulse signal is converted into a direct current voltage which is linear with the pulse signal through a frequency-voltage converter, the more and more accurate the number of the compared and matched pulses is, the lower the converted voltage is, the converted voltage is sent to a gain adjustment control circuit, the direct current voltage is compared with the frame synchronization head synchronization voltage after error rate correction through an operational amplifier AR2, and the high or low level is output to control the receiver gain adjustment circuit to perform corresponding non-high-gain or high-gain reception, therefore, the problems that the receiver receives interference signals and the error rate is high due to high-gain reception when the transmitting party does not transmit data are avoided.)

1. A wireless communication signal anti-interference device of a computer comprises a frame synchronization head pulse decision circuit, a pulse voltage conversion circuit and a gain adjustment control circuit, and is characterized in that the frame synchronization head pulse decision circuit adopts an exclusive-OR gate U3 to carry out logic operation of same output 0 and different output 1 on a received frame synchronization head pulse signal and a frame synchronization pulse signal generated by a frame synchronization pulse generator, the received frame synchronization head pulse signal and the frame synchronization pulse signal are converted into pulse signals through a complementary triode Q3 and a triode Q4 and then output the pulse signals, the pulse voltage conversion circuit receives the pulse signals output by the frame synchronization head pulse decision circuit and converts the pulse signals into linear direct current voltage to output, the gain adjustment control circuit compares the direct current voltage output by the pulse voltage conversion circuit with the frame synchronization head synchronization voltage after correction through an operational amplifier AR2 and outputs high or low level to control a receiver gain adjustment circuit to carry out corresponding non-high-gain or high-gain reception, therefore, the problems that the receiver receives interference signals and the error rate is high due to high-gain reception when the transmitting party does not transmit data are avoided.

2. The apparatus of claim 1, wherein the frame sync header pulse decision circuit comprises a resistor R1 and a time-base chip U5, one end of the resistor R1 is connected to the frame sync pulse signal, the other end of the resistor R1 is connected to the upper end of a capacitor C1, pin 1 of a photocoupler U1, the lower end of a capacitor C1, and pin 2 of the photocoupler U1 are connected to ground, pin 4 of the photocoupler U1 is connected to one end of a resistor R2 and the base of a transistor Q1, the collector of the transistor Q1 is connected to one end of the resistor R3 and the A end of an exclusive-OR gate U3, the other end of the resistor R2 and the other end of the resistor R3 are connected to a power supply +5V, pin 3 of the photocoupler U1 and the emitter of the transistor Q1 are connected to ground, pin 4 and pin 8 of the time-base chip U5 and one end of the resistor R4 are connected to a power supply +5V, pin 2 and pin 6 of the time-base chip U5 are connected to one end of a resistor R5 and one end of a capacitor C2, pin 5 of the time-base chip U5 is connected to one end of a resistor R6 and one end of a capacitor C3, the other end of the resistor R6 is connected to an adjustable end of a potentiometer RM1, pin 1 of the time-base chip U5, one end of a connecting resistor R6, one end of a capacitor C3 and the lower end of a potentiometer RM1 are connected to ground, the upper end of the potentiometer RM1 is connected to +15V, pin 3 of the time-base chip U5 is connected to the other end of a resistor R5 and one end of a resistor R7, the other end of the resistor R7 is connected to the upper end of the capacitor C7 and pin 1 of a photocoupler U7, the lower end of the capacitor C7 and pin 2 of the photocoupler U7 are connected to ground, pin 4 of the photocoupler U7 is connected to one end of the resistor R7 and the base of a triode Q7, the collector of the resistor R7 and, The other end of the resistor R9 is connected with +5V of a power supply, the Y end of the XOR gate U3 is respectively connected with the anode of the diode D1 and the cathode of the diode D2, the anode of the diode D2 and the cathode of the diode D1 are respectively connected with the base of the triode Q4 and the base of the triode Q3, the collector of the triode Q3 is connected with +4.3V of the power supply, the collector of the triode Q4 is connected with the power supply +0.7V through the resistor R10, and the emitter of the triode Q3 and the emitter of the triode Q4 are output signals of a frame synchronization pulse judgment circuit.

3. The apparatus of claim 1 for suppressing interference to wireless communication signals of a computer, the gain adjustment control circuit comprises an operational amplifier AR2, wherein the non-inverting input end of the operational amplifier AR2 is connected with one end of a resistor R13 and one end of a resistor R15 respectively, the other end of the resistor R13 is connected with an output signal of a pulse voltage conversion circuit, the output end of the operational amplifier AR2 and the other end of the resistor R15 are output signals of the gain adjustment control circuit, the output signals control the gain of the receiver gain adjustment circuit, the inverting input end of the operational amplifier AR2 is connected with one end of a grounding resistor R16, one end of a resistor R14 and one end of a resistor R17 respectively, the other end of the resistor R14 is connected with a pin 3 of a multiplier U3, a pin 2 of a multiplier U3 is connected with a bit error rate signal received in real time, and a pin 1 of the multiplier U3 and the other end of the resistor R17 are.

4. The apparatus of claim 1 for suppressing interference to wireless communication signals of a computer, the pulse voltage conversion circuit comprises a chip U4, a pin 16 of a chip U2 is connected with a frame synchronization pulse decision circuit output signal, a pin 12 of a chip U4 is connected with the ground through a capacitor C6, a pin 13 of a chip U4 is respectively connected with one end of a capacitor C5, the anode of a voltage regulator tube Z1 and one end of a resistor R11, the other end of a resistor R11 is connected with +5V, the other end of a capacitor C5 and the cathode of a voltage regulator tube Z1 are connected with the ground, a pin 14 of a chip U4 is respectively connected with one end of a resistor R12, one end of a capacitor C7 and the inverting input end of an operational amplifier AR1, the other end of a resistor R12 is respectively connected with the other end of a capacitor C7 and the output end of an operational amplifier AR1, the output end of the operational amplifier AR1 is the pulse voltage conversion circuit output signal, and the non.

Technical Field

The invention relates to the technical field of wireless communication, in particular to a wireless communication signal anti-interference device of a computer.

Background

With the rapid development of wireless communication technology, the wireless communication technology is widely applied to computers, but in the current increasingly complex electromagnetic environment, serial wireless communication of computers faces the influence of various interferences, especially when a transmitter of a transmitting party does not transmit data, because a receiver of a receiving party usually receives high gain, a plurality of interference signals can be received at the moment, and the existence of the interferences can make a communication port unable to judge the arrival time of communication data.

Disclosure of Invention

In view of the above situation, an object of the present invention is to provide an apparatus for preventing wireless communication signals from being interfered in a computer, which effectively solves the problem that the prior art still receives many interference signals or has a high error rate due to the adoption of a preset precision.

The technical scheme for solving the problem is that the device comprises a frame synchronization head pulse judgment circuit, a pulse voltage conversion circuit and a gain adjustment control circuit, and is characterized in that the frame synchronization head pulse judgment circuit adopts an exclusive-OR gate U3 to carry out logic operation of same output 0 and different output 1 on a received frame synchronization head pulse signal and a frame synchronization pulse signal generated by a frame synchronization pulse generator, the received frame synchronization head pulse signal and the frame synchronization pulse signal are converted into pulse signals through a complementary triode Q3 and a triode Q4 and then output the pulse signals, the pulse voltage conversion circuit receives the pulse signals output by the frame synchronization head pulse judgment circuit and converts the pulse signals into linear direct current voltage and then outputs the linear direct current voltage, the gain adjustment control circuit compares the direct current voltage output by the pulse voltage conversion circuit with the frame synchronization head synchronization voltage after correction through an operational amplifier AR2 and outputs high or low level to control a receiver gain adjustment circuit to carry out corresponding non-high gain or high gain reception, therefore, the problem that the receiver receives interference signals at high gain when the transmitting party does not transmit data is avoided.

Preferably, the frame synchronization header pulse decision circuit includes a resistor R1 and a time-base chip U5, one end of the resistor R1 is connected to a frame synchronization pulse signal, the other end of the resistor R1 is connected to the upper end of a capacitor C1 and a pin 1 of a photocoupler U1, the lower end of the capacitor C1 and a pin 2 of the photocoupler U1 are connected to ground, a pin 4 of the photocoupler U1 is connected to one end of a resistor R2 and the base of a triode Q1, the collector of the triode Q1 is connected to one end of a resistor R3 and an end a of an xor gate U3, the other end of the resistor R2 and the other end of the resistor R3 are connected to a power supply +5V, a pin 3 of the photocoupler U9 and the emitter of the triode Q1 are connected to ground, a pin 4 and a pin 8 of the time-base chip U5 and one end of the resistor R4 are connected to a power supply +5V, a pin 2 and a pin 6 of the time-base chip U5 and a pin 6 and a pin 5 of the capacitor C2 are connected to one end, One end of a capacitor C3, the other end of a resistor R6 is connected with an adjustable end of a potentiometer RM1, a pin 1 and one end of a connecting resistor R6 of a time-base chip U5, one end of a capacitor C3 and the lower end of a potentiometer RM1 are connected with the ground, the upper end of the potentiometer RM1 is connected with a power supply +15V, a pin 3 of the time-base chip U5 is connected with the other end of a resistor R5 and one end of a resistor R7, the other end of a resistor R7 is respectively connected with the upper end of a capacitor C4 and the pin 1 of a photocoupler U2, the lower end of the capacitor C4 and the pin 2 of the photocoupler U2 are connected with the ground, a pin 4 of a resistor U2 is respectively connected with one end of a resistor R8 and the base of a triode Q2, a collector of the triode Q2 is respectively connected with one end of the resistor R2 and the B end of an XOR gate U2, the other end of the resistor R2 and the negative pole 2 of a diode 2D and a diode 2D, the anode of the diode D2 and the cathode of the diode D1 are respectively connected with the base of the triode Q4 and the base of the triode Q3, the collector of the triode Q3 is connected with +4.3V of a power supply, the collector of the triode Q4 is connected with +0.7V of the power supply through a resistor R10, and the emitter of the triode Q3 and the emitter of the triode Q4 are output signals of a frame synchronization pulse judgment circuit.

The invention has the beneficial effects that: the circuit structure is simple, firstly, the exclusive-or gate U3 is adopted to carry out the logic operation of same output 0 and different output 1 on the received frame synchronization head pulse signal and the frame synchronization pulse signal generated by the frame synchronization pulse generator, namely, the result of each pulse matching comparison is converted into 0 or 1, then the complementary triode Q3 and the triode Q4 are driven to be converted into a determined pulse signal with low level or high level, the determined pulse signal is converted into linear direct current voltage by a frequency-voltage converter, the more the number and the more accurate the pulse matched are compared, the lower the voltage after conversion is, the direct current voltage enters an operational amplifier AR2 to be compared with the frame synchronization head synchronization voltage after error rate correction, the high level or the low level is output when the direct current voltage is higher than or lower than the frame synchronization head synchronization voltage after correction, and the receiver gain adjusting circuit is controlled to carry out corresponding non-high gain or high gain reception, therefore, the problems that the receiver receives interference signals and the error rate is high due to high-gain reception when the transmitting party does not transmit data are avoided.

Drawings

Fig. 1 is a schematic diagram of the circuit connection of the present invention.

Detailed Description

The foregoing and other technical and scientific aspects, features and utilities of the present invention will be apparent from the following detailed description of the embodiments, which is to be read in connection with the accompanying drawings of fig. 1. The structural contents mentioned in the following embodiments are all referred to the attached drawings of the specification.

Exemplary embodiments of the present invention will be described below with reference to the accompanying drawings.

An anti-interference device for wireless communication signals of a computer comprises a frame synchronization head pulse decision circuit, a pulse voltage conversion circuit and a gain adjustment control circuit, wherein the frame synchronization head pulse decision circuit performs logic operation of a same output 0 and a different output 1 on a received frame synchronization head pulse signal and a frame synchronization pulse signal generated by a frame synchronization pulse generator by adopting an exclusive-or gate U3, the operated 0 or 1 converts the result of matching and comparison of each pulse into 0 or 1, then a complementary triode Q3 and a triode Q4 are driven to convert the result into a low-level or high-level determined pulse signal and output the pulse signal to the pulse voltage conversion circuit, the pulse voltage conversion circuit receives the pulse signal output by the frame synchronization head pulse decision circuit, the pulse signal is converted into a direct current voltage linear with the pulse signal by a chip U4 with the model of TC 26, an operational amplifier AR1, a resistor R11, a resistor R4, a capacitor C5-capacitor C7 and a voltage stabilizing tube Z1, the frequency voltage converter is converted into the direct current voltage linear with the pulse signal, the more pulses are compared, the more the number of the matched, the voltage is more accurate, the voltage is converted, the voltage is output by the low-gain adjustment circuit, the high-gain adjustment circuit, the receiver control circuit, the receiver receives the high-gain-bit-error-rate-error-rate-error-rate-corrected data-;

the frame synchronization head pulse decision circuit performs same-out 0 and different-out 1 logic operation on a received frame synchronization head pulse signal and a frame synchronization pulse signal generated by a frame synchronization pulse generator by adopting an exclusive-or gate U3, wherein the received frame synchronization head pulse signal is subjected to phase inversion by a photoelectric coupler U1 and is finally added to an A end of an exclusive-or gate U3 after phase inversion by a triode Q1, the frame synchronization pulse generator consists of a time base chip U5, a resistor R4, a resistor R6, a potentiometer RM1, a capacitor C2 and a capacitor C3, the frame synchronization pulse signal is also the frame synchronization pulse signal of 1 or 0, the frequency of the square wave pulse signal can be adjusted by the potentiometer 1, the square wave signal is added to a B end of the exclusive-or gate U3 after phase inversion by the photoelectric coupler U73725 and is finally added to a B end of the exclusive-or gate U3 after phase inversion by the triode Q3, and the exclusive-or gate U3 performs same-out 0 (low level) logic operation, The circuit comprises a resistor R1 and a time-base chip U5, wherein one end of the resistor R1 is connected with a frame synchronization pulse signal, the other end of the resistor R1 is respectively connected with the upper end of a capacitor C1 and a pin 1 of a photocoupler U1, the lower end of the capacitor C1 and a pin 2 of the photocoupler U1 are connected with the ground, a pin 4 of the photocoupler U1 is respectively connected with one end of a resistor R2 and a base of a triode Q1, a collector of the triode Q1 is respectively connected with one end of a resistor R3 and an A end of an XOR gate U3, the other end of the resistor R2 and the other end of the resistor R3 are connected with a power supply +5V, and a pin 3 of the photocoupler U1, The emitter of the triode Q1 is connected to the ground, one end of a pin 4, a pin 8 and a resistor R4 of the time-base chip U5 are connected to +5V of a power supply, a pin 2 and a pin 6 of the time-base chip U5 are connected to one end of the resistor R5 and one end of the capacitor C2, a pin 5 of the time-base chip U5 is connected to one end of the resistor R6 and one end of the capacitor C3, the other end of the resistor R6 is connected to the adjustable end of the potentiometer RM1, a pin 1 of the time-base chip U5, one end of the resistor R6, one end of the capacitor C3 and the lower end of the potentiometer RM1 are connected to the ground, the upper end of the potentiometer RM1 is connected to +15V of the power supply, a pin 3 of the time-base chip U5 is connected to the other end of the resistor R5 and one end of the resistor R7, the other end of the resistor R7 is connected to the upper end of the capacitor C4, a pin 1 of the photoelectric coupler U2, the lower end of the capacitor C, A base electrode of a triode Q2, a collector electrode of a triode Q2 is respectively connected with one end of a resistor R9 and a B end of an exclusive-or gate U3, the other end of a resistor R8 and the other end of a resistor R9 are respectively connected with +5V of a power supply, a Y end of the exclusive-or gate U3 is respectively connected with an anode of a diode D1 and a cathode of a diode D2, an anode of a diode D2 and a cathode of a diode D1 are respectively connected with a base electrode of a triode Q4 and a base electrode of a triode Q3, a collector electrode of a triode Q3 is connected with +5V of the power supply, a collector electrode of a triode Q4 is connected with-0.7V of the power supply through a resistor R10, and an emitter electrode of a triode Q3 and an;

the gain adjustment control circuit inputs the direct current voltage output by the pulse voltage conversion circuit and the corrected frame synchronization head synchronization voltage (specifically, the error rate tester detects that the error rate received by the receiver is completely synchronous with the frame synchronization head, namely, the voltage signal +5V corresponding to the total code number is input into the analog multiplier U3 to be multiplied, the multiplied voltage is coupled with the synchronization voltage +5V through the resistor R14 to obtain, the higher the error rate is, the higher the corrected voltage is, the fewer the number of pulses allowed to be compared are, the higher the direct current voltage is higher than the corrected frame synchronization head synchronization voltage is, the high level is output, the receiver gain adjustment circuit is controlled to perform corresponding non-high gain reception, otherwise, the low level is output, the receiver gain adjustment circuit is controlled to perform high gain reception, so as to avoid that when the transmitting side has no data transmission, the receiver receives interference signals with high gain and has high error rate, and comprises an operational amplifier AR2, wherein the non-inverting input end of the operational amplifier AR2 is respectively connected with one end of a resistor R13 and one end of a resistor R15, the other end of the resistor R13 is connected with an output signal of a pulse voltage conversion circuit, the output end of the operational amplifier AR2 and the other end of a resistor R15 are output signals of a gain adjustment control circuit, the output signals control the gain of the receiver gain adjustment circuit, the inverting input end of the operational amplifier AR2 is respectively connected with one end of a grounding resistor R16, one end of a resistor R14 and one end of a resistor R17, the other end of a resistor R14 is connected with a pin 3 of a multiplier U3, a pin 2 of the multiplier U3 is connected with an error rate signal received in real time, and the other ends of a pin 1 of the multiplier U3 and the resistor R17;

the pulse voltage conversion circuit receives pulse signals output by the frame synchronization head pulse judgment circuit, the pulse signals are converted into direct current voltage linear with the pulse signals through a frequency voltage converter consisting of a chip U4 with the model number of L TC1013, an operational amplifier AR1, a resistor R11, a resistor R12, a capacitor C5-a capacitor C7 and a voltage regulator tube Z1, the more and more accurate the number of the pulses which are compared and matched are, the lower the voltage after conversion is, the gain adjustment control circuit comprises a chip U4, a pin 16 of a chip U2 is connected with the output signals of the frame synchronization pulse judgment circuit, a pin 12 of a chip U4 is connected with the ground through a capacitor C6, a pin 13 of a chip U4 is respectively connected with one end of a capacitor C5, the anode of a voltage regulator tube Z1 and one end of a resistor R11, the other end of the resistor R11 is connected with a power supply +5V, the other end of the capacitor C11 and the cathode of the voltage regulator tube Z11 are respectively connected with one end of a pin 14 of the operational amplifier R11, the operational amplifier is connected with the in-phase operational amplifier, the operational amplifier is connected with the same-phase operational amplifier, the operational amplifier and the other end of the operational amplifier and the operational amplifier is connected with the operational amplifier.

When the invention is used in concrete, the frame synchronization head pulse decision circuit adopts an exclusive-or gate U3 to carry out logical operation of same-out 0 and different-out 1 on a received frame synchronization head pulse signal and a frame synchronization pulse signal generated by a frame synchronization pulse generator, wherein the received frame synchronization head pulse signal is subjected to logical operation of same-out 0 and different-out 1 by a data stream output by a serial/parallel converter of a Barker code recognizer, then is subjected to an electric pulse signal inverted by a photoelectric coupler U1 and finally is added to an A end of an exclusive-or gate U3 after being inverted by a triode Q1, the frame synchronization pulse generator consists of a time base chip U5, a resistor R4-resistor R6, a potentiometer RM1, a capacitor C2 and a capacitor C3, outputs a frame synchronization pulse signal which is a square wave pulse signal of 0 or 1, then is subjected to inverse isolation by the photoelectric coupler U2 and is finally added to a B end of the exclusive-or gate U3 after being inverted by the triode Q1, and the exclusive-or gate U3 carries out logical operation of same-out 0 (low level), the calculated 0 or 1 is that the result of each pulse matching comparison is converted into 0 or 1, then the complementary triode Q3 and the triode Q4 are driven to be converted into a determined pulse signal with low level or high level and then output to a pulse voltage conversion circuit, a frequency voltage converter is adopted to convert the determined pulse signal into a linear direct current voltage, the more the number of the pulses matched for comparison is, the more accurate the converted voltage is, the lower the converted voltage is, the more accurate the converted voltage is, the gain adjustment control circuit is sent, the direct current voltage output by the pulse voltage conversion circuit is compared with the frame synchronization head synchronization voltage through an operational amplifier AR2, when the direct current voltage is higher than the frame synchronization head synchronization voltage after correction, the high level is output, the receiver gain adjustment circuit is controlled to carry out corresponding non-high gain receiving, otherwise, the low level is output, the receiver gain adjustment circuit is controlled to carry out high gain receiving, therefore, the problems that the receiver receives interference signals and the error rate is high due to high-gain reception when the transmitting party does not transmit data are avoided.