阅读说明：本技术 处理方法和等离子体处理装置 (Processing method and plasma processing apparatus ) 是由 及川翔 横山政司 冈野太一 河崎俊一 于 2020-01-10 设计创作，主要内容包括：本发明提供一种抑制外周构件的消耗并且去除外周构件之上的沉积物的处理方法和等离子体处理装置。所述处理方法使用等离子体处理装置来对被处理体进行处理,所述等离子体处理装置具有：载置台,其在腔室内载置被处理体；外周构件,其配置于所述载置台的周围；以及第一电源,其向所述外周构件施加电压,所述处理方法包括以下工序：一边从所述第一电源向所述外周构件施加电压,一边使被处理体暴露在具有沉积性的前体的等离子体中；以及在暴露于所述等离子体中的工序期间中,观测沉积在所述外周构件之上的包含碳的沉积膜的状态,基于观测到的所述沉积膜的状态来控制向所述外周构件施加的电压。(The invention provides a processing method and a plasma processing apparatus for suppressing consumption of an outer peripheral member and removing deposits on the outer peripheral member. The processing method uses a plasma processing apparatus to process an object to be processed, the plasma processing apparatus having: a mounting table for mounting a target object in the chamber; an outer peripheral member disposed around the mounting table; and a first power supply that applies a voltage to the outer peripheral member, the treatment method including: exposing the object to be processed to plasma of a precursor having a deposition property while applying a voltage from the first power supply to the outer peripheral member; and observing a state of a deposited film containing carbon deposited on the outer peripheral member during the process of exposure to the plasma, and controlling a voltage applied to the outer peripheral member based on the observed state of the deposited film.)

1. A processing method for processing an object to be processed by using a plasma processing apparatus, the plasma processing apparatus comprising: a mounting table for mounting a target object in the chamber; an outer peripheral member disposed around the mounting table; and a first power supply that applies a voltage to the outer peripheral member, the treatment method including:

exposing the object to be processed to plasma of a precursor having a deposition property while applying a voltage from the first power supply to the outer peripheral member; and

during the process of exposure to the plasma, a state of a deposited film containing carbon deposited on the outer peripheral member is observed, and a voltage applied to the outer peripheral member is controlled based on the observed state of the deposited film.

2. The processing method according to claim 1, further comprising the steps of:

correcting a process parameter based on a voltage applied to an outer peripheral member with reference to a storage section storing correlation information between the voltage applied to the outer peripheral member and a correction value of the process parameter; and

performing plasma processing according to the process conditions including the corrected process parameter.

3. The processing method according to claim 2,

the process parameters are process conditions that cause the density of the generated plasma to vary.

4. The processing method according to claim 2 or 3,

the process parameter is a process condition that causes a variation in etch rate.

5. The processing method according to any one of claims 2 to 4,

the process parameter is at least one of a first frequency high-frequency power applied from a first high-frequency power source, a second frequency high-frequency power lower than the first frequency high-frequency power applied from a second high-frequency power source, a gas supplied into the chamber, and a voltage applied from the second power source to the upper electrode facing the stage.

6. The processing method according to any one of claims 1 to 5,

in the step of controlling the voltage applied to the outer peripheral member, the voltage is applied to the outer peripheral member when the state of the deposited film is observed to be equal to or greater than a predetermined threshold value.

7. The processing method according to any one of claims 1 to 6,

in the step of controlling the voltage applied to the outer peripheral member, when the observed state of the deposited film is smaller than a predetermined threshold value, the voltage is not applied to the outer peripheral member.

8. The processing method according to any one of claims 1 to 7,

the plasma of the deposition precursor is generated from a process gas capable of producing the deposition precursor.

9. The processing method according to claim 8,

the process gas comprises carbon.

10. A plasma processing apparatus includes: a mounting table for mounting a target object in the chamber; an outer peripheral member disposed around the mounting table; a first power supply that applies a voltage to the outer peripheral member; and a control part for controlling the operation of the motor,

wherein the control section executes the following steps:

exposing an object to be processed to plasma of a processing gas containing carbon while applying a voltage from the first power supply to the outer peripheral member;

observing a state of a deposited film containing carbon deposited over the outer peripheral member during a process of being exposed to the plasma of the process gas, controlling a voltage applied to the outer peripheral member based on the observed state of the deposited film; and

the process parameter is corrected based on the voltage applied to the outer peripheral member with reference to a storage section that stores correlation information between the voltage applied to the outer peripheral member and a correction value of the process parameter.

Technical Field

The present disclosure relates to a processing method and a plasma processing apparatus.

Background

The following procedure is present: by-products generated by the plasma treatment are deposited on the wafer to form a deposited film. For example, patent document 1 proposes a technique of alternately repeating the following steps: etching a region composed of silicon oxide and forming a deposition containing a fluorocarbon on the region; and etching the region by radicals of fluorocarbon contained in the deposit. The byproducts are deposited on the wafer and also on an outer peripheral member (hereinafter also referred to as an "edge ring") disposed around the wafer.

Disclosure of Invention

Problems to be solved by the invention

The present disclosure provides a technique capable of suppressing consumption of an outer peripheral member and removing deposits on the outer peripheral member.

Means for solving the problems

According to one aspect of the present disclosure, there is provided a processing method for processing an object to be processed using a plasma processing apparatus including: a mounting table for mounting a target object in the chamber; an outer peripheral member disposed around the mounting table; and a first power supply that applies a voltage to the outer peripheral member, the treatment method including: exposing the object to be processed to plasma of a precursor having a deposition property while applying a voltage from the first power supply to the outer peripheral member; and observing a state of a deposited film containing carbon deposited on the outer peripheral member during the process of exposure to the plasma, and controlling a voltage applied to the outer peripheral member based on the observed state of the deposited film.

ADVANTAGEOUS EFFECTS OF INVENTION

According to one aspect, it is possible to suppress consumption of the outer peripheral member and remove deposits on the outer peripheral member.

Drawings

Fig. 1 is a schematic cross-sectional view showing an example of a plasma processing apparatus according to an embodiment.

Fig. 2 is a diagram for explaining the deposition process and the sputtering process.

Fig. 3 is a diagram showing an example of a method for monitoring the deposition state of the edge ring.

Fig. 4 is a graph showing an example of the correlation between the monitored value and the deposition state of the edge ring according to the embodiment.

Fig. 5 is a flowchart showing an example of the voltage application control process according to the embodiment.

Fig. 6 is a diagram illustrating an example of the effect of the voltage application control according to the embodiment.

Fig. 7 is a graph showing an example of the etching rate when a voltage is applied to the edge ring.

Fig. 8 is a graph showing an example of the etching rate when a voltage is applied to the edge ring.

Fig. 9 is a diagram showing an example of a processing result of the processing method according to the embodiment.

Fig. 10 is a flowchart showing an example of the processing method according to the embodiment.

Fig. 11 is a flowchart showing an example of the correction processing according to the embodiment.

Detailed Description

Hereinafter, a mode for carrying out the present disclosure will be described with reference to the drawings. In the drawings, the same components are denoted by the same reference numerals, and redundant description may be omitted.

[ plasma processing apparatus ]

A plasma processing apparatus 1 according to an embodiment will be described with reference to fig. 1. Fig. 1 is a schematic cross-sectional view showing an example of a plasma processing apparatus 1 according to an embodiment. The plasma processing apparatus 1 according to one embodiment is a capacitive coupling parallel plate processing apparatus and includes a chamber 10. The chamber 10 is a cylindrical container made of, for example, aluminum having an anodized surface, and the chamber 10 is grounded.

A cylindrical support table 14 is disposed on the bottom of the chamber 10 via an insulating plate 12 made of ceramic or the like, and a stage 16, for example, is provided on the support table 14. The mounting table 16 includes an electrostatic chuck 20 and a base 16a, and a wafer W is mounted on an upper surface of the electrostatic chuck 20. An annular edge ring 24 made of, for example, silicon is disposed around the wafer W. The edge ring 24 is also referred to as a focus ring. The edge ring 24 is an example of an outer peripheral member disposed around the mounting table 16. An annular insulating ring 26 made of, for example, quartz is provided around the susceptor 16a and the support base 14. A first electrode 20a including a conductive film is interposed in the insulating layer 20b inside the center side of the electrostatic chuck 20. The first electrode 20a is connected to a power source 22. An electrostatic force is generated by a dc voltage applied from the power source 22 to the first electrode 20a, and the wafer W is attracted to the wafer mounting surface of the electrostatic chuck 20. In addition, the electrostatic chuck 20 may have a heater, thereby controlling the temperature.

An annular or spiral refrigerant chamber 28 is formed inside the support base 14. The coolant of a predetermined temperature supplied from the cooling unit (not shown), for example, cooling water, is returned to the cooling unit through the pipe 30a, the coolant chamber 28, and the pipe 30 b. The temperature of the wafer W can be controlled by the temperature of the refrigerant by circulating the refrigerant through the path. The heat transfer gas, for example, He gas supplied from the heat transfer gas supply mechanism is supplied to the gap between the front surface of the electrostatic chuck 20 and the back surface of the wafer W through the gas supply line 32. By this heat transfer gas, the heat transfer coefficient between the front surface of the electrostatic chuck 20 and the back surface of the wafer W is reduced, and the control of the temperature of the wafer W by the temperature of the refrigerant becomes more effective. In addition, when the electrostatic chuck 20 includes a heater, the temperature of the wafer W can be controlled with high responsiveness and high accuracy by heating with the heater and cooling with the refrigerant.

The upper electrode 34 is provided on the top of the chamber 10 so as to face the stage 16. A plasma processing space is formed between the upper electrode 34 and the stage 16. The upper electrode 34 closes the opening at the top of the chamber 10 through an insulating shielding member 42. The upper electrode 34 includes an electrode plate 36 and an electrode support 38. The electrode plate 36 has a large number of gas ejection holes 37 formed in the opposing surface facing the mounting table 16, and the electrode plate 36 is formed of a silicon-containing material such as silicon or SiC. The electrode support 38 supports the electrode plate 36 in a detachable manner, and the electrode support 38 is formed of a conductive material, for example, aluminum having an anodized surface. Inside the electrode support 38, a large number of gas flow holes 41a and 41b extend downward from the gas diffusion chambers 40a and 40b, and these gas flow holes 41a and 41b communicate with the gas ejection holes 37.

The gas introduction port 62 is connected to a process gas supply source 66 via a gas supply pipe 64. A Mass Flow Controller (MFC)68 and an on-off valve 70 are provided in this order from the upstream side of the process gas supply source 66 on the gas supply pipe 64. The process gas is supplied from the process gas supply source 66, and the flow rate and opening/closing of the process gas are controlled by the mass flow controller 68 and the opening/closing valve 70, and the process gas is sprayed in a shower shape from the gas spray holes 37 after passing through the gas diffusion chambers 40a and 40b and the gas flow holes 41a and 41b via the gas supply pipe 64.

The plasma processing apparatus 1 has a first high-frequency power supply 90 and a second high-frequency power supply 48. The first high-frequency power supply 90 is a power supply that generates first high-frequency power (hereinafter also referred to as "HF power"). The first high-frequency power has a frequency suitable for generating plasma. The frequency of the first high-frequency power is, for example, a frequency in the range of 27MHz to 100 MHz. The first high-frequency power supply 90 is connected to the base 16a via the matching unit 88 and the power supply line 89. The matching unit 88 has a circuit for matching the output impedance of the first high-frequency power supply 90 with the impedance on the load side (the base 16a side). The first high-frequency power source 90 may be connected to the upper electrode 34 via the matching box 88.

The second radio-frequency power supply 48 is a power supply that generates second radio-frequency power (hereinafter also referred to as "L F power") having a frequency lower than that of the first radio-frequency power, and when the second radio-frequency power is used together with the first radio-frequency power, the second radio-frequency power is used as bias radio-frequency power for attracting ions to the wafer W, the frequency of the second radio-frequency power is, for example, a frequency in the range of 400kHz to 13.56MHz, the second radio-frequency power supply 48 is connected to the susceptor 16a via the matching box 46 and the power supply line 47, and the matching box 46 has a circuit for matching the output impedance of the second radio-frequency power supply 48 with the impedance on the load side (susceptor 16a side).

In addition, the plasma may be generated using the second high-frequency power, that is, only the single high-frequency power, instead of the first high-frequency power. In this case, the frequency of the second high-frequency power may be a frequency greater than 13.56MHz, for example, 40 MHz. The plasma processing apparatus 1 may not include the first high-frequency power supply 90 and the matching unit 88. With this configuration, the mounting table 16 also functions as a lower electrode. The upper electrode 34 also functions as a shower head for supplying gas.

The second variable power supply 50 is connected to the upper electrode 34, and applies a dc voltage to the upper electrode 34. The first variable power supply 55 is connected to the edge ring 24, and applies a dc voltage to the edge ring 24. The first variable power source 55 is an example of a first power source that applies a voltage to the peripheral member. The second variable power supply 50 is an example of a second power supply that applies a voltage to the upper electrode 34.

The exhaust device 84 is connected to the exhaust pipe 82. The exhaust unit 84 has a vacuum pump such as a turbo molecular pump, and exhausts gas from an exhaust port 80 formed in the bottom of the chamber 10 through an exhaust pipe 82 to reduce the pressure in the chamber 10 to a desired vacuum level. The exhaust device 84 controls the pressure in the chamber 10 to be constant by using the value of a not-shown pressure gauge for measuring the pressure in the chamber 10. A carrying-in/out port 85 is provided in a side wall of the chamber 10. The wafers W are carried in and out from the carry-in/out port 85 by opening and closing the gate valve 86.

A baffle 83 is annularly provided between the insulating ring 26 and the sidewall of the chamber 10. The baffle 83 is made of aluminum and has a plurality of through holes, and the surface of the baffle 83 is covered with a cover Y₂O₃And the like.

In the plasma processing apparatus 1 having this configuration, when a predetermined plasma process such as a plasma etching process is performed, the gate valve 86 is opened, the wafer W is carried into the chamber 10 through the carrying-in/out port 85 and placed on the mounting table 16, and then the gate valve 86 is closed. A process gas is supplied into the chamber 10, and the inside of the chamber 10 is exhausted by an exhaust unit 84.

The first high-frequency power and the second high-frequency power are applied to the stage 16. A dc voltage is applied from the power source 22 to the first electrode 20a, whereby the wafer W is attracted to the stage 16. Further, a dc voltage may be applied from the second variable power supply 50 to the upper electrode 34.

The surface to be processed of the wafer W is subjected to plasma processing, such as etching, by radicals and ions in the plasma generated in the plasma processing space.

The plasma processing apparatus 1 is provided with a control unit 200 for controlling the operation of the entire apparatus. The CPU provided in the control unit 200 executes a desired plasma process such as etching in accordance with a process stored in a memory such as a ROM or a RAM. The process time, pressure (gas exhaust), first and second high-frequency power, voltage, and various gas flow rates, which are control information of the apparatus for the process conditions, may be set during the process. In addition, the temperature in the chamber (the upper electrode temperature, the chamber sidewall temperature, the wafer W temperature, the electrostatic chuck temperature, etc.), the temperature of the coolant output from the cooler, and the like may be set during the process. In addition, these programs and processes indicating the processing conditions may be stored in a hard disk or a semiconductor memory. In addition, the process can be carried out in a state of being stored in a portable computer-readable storage medium such as a CD-ROM, a DVD, or the like, at a predetermined position for reading.

[ deposition step and sputtering step ]

In recent years, for example, in a technique such as a L E in which deposition etching and non-deposition etching are repeated a predetermined number of times, it is important to control the deposition amount, and particularly, in very low temperature etching in which etching is performed by controlling the temperature of the stage 16 to, for example, about-several tens ℃ to-one hundred and several tens ℃, the deposition amount of by-products generated by etching increases.

Next, a step of depositing by-products by etching and a step of sputtering while depositing the by-products will be described with reference to fig. 2. Fig. 2 is a diagram for explaining a deposition process and a sputtering process.

For example, there are the following procedures: a region made of silicon oxide on the wafer W is etched to form a deposit containing carbon on the region. In the deposition process, C containing carbon is supplied from the process gas supply source 66₄F₈Iso-fluorocarbon gas, CH₄And a hydrocarbon gas. The process gas may be CH₂F₂And the like hydrofluorocarbon gases. The process gas may also contain an inert gas. In the following, it is assumed that argon gas is included as an inert gas.

The processing gas is converted into plasma by the first high-frequency power and the second high-frequency power. As shown in FIG. 2, the plasma contains, for example, CH_xFree radical (CH)_x ^*)、C_yF_zFree radical (C)_yF_z ^*) Plasma radical 102 and argon ion (Ar)⁺)101。

Here, fig. 2 (a) shows a case where no dc voltage is applied to the edge ring 24, and fig. 2 (b) shows a case where a dc voltage is applied to the edge ring 24. The argon ions 101 have anisotropy, and in fig. 2 (a), the argon ions 101 move toward the stage 16 to which the second high-frequency power is applied as indicated by an arrow a1, and contribute to etching of silicon oxide on the wafer W. The radicals 102 act isotropically on the wafer W. Thereby, a by-product containing carbon generated at the time of the etching process is deposited on the wafer W. In the process, the edge ring 24 is exposed to the plasma. Thereby, by-products containing carbon are deposited not only on the wafer W but also on the edge ring 24 (d in fig. 2 (a)).

When the deposition etching to the non-deposition etching is performed in a state where the by-products containing carbon are deposited on the edge ring 24, for example, sequentially or alternately, the plasma is deviated by the deposition on the edge ring 24, and the etching may not be performed properly. Therefore, a dc voltage is applied from the first variable power supply 55 to the edge ring 24, and argon ions 101 in the plasma are attracted to the edge ring 24 as indicated by an arrow a2 in fig. 2 (b), whereby sputtering is performed on the edge ring 24. As such, byproducts including carbon deposited over the edge ring 24 are sputtered away.

However, when the direct-current voltage is always applied to the edge ring 24, the consumption of the edge ring 24 is fast as compared with the case where the direct-current voltage is not applied. When the edge ring 24 is new, the upper surface of the edge ring 24 and the upper surface of the wafer W are at the same height. In contrast, when the edge ring 24 is consumed, the thickness of the edge ring 24 becomes thin, and the upper surface of the edge ring 24 becomes lower than the upper surface of the wafer W. As a result, a height difference is generated between the sheath on the edge ring 24 and the sheath on the wafer W.

Due to this height difference, the irradiation angle of the ions is inclined at the edge portion of the wafer W, and the shape of the concave portion formed on the wafer W is inclined. Thus, it is desirable to suppress the consumption of the edge ring 24 so as not to generate the inclination, and to remove the deposits on the edge ring 24. Therefore, the plasma processing apparatus 1 according to the present embodiment provides a processing method for removing deposits on the edge ring 24 while suppressing the consumption of the edge ring 24. Therefore, in the present embodiment, the deposition state of by-products (hereinafter also referred to as "deposits") generated during the etching process on the edge ring 24 is monitored, and whether or not the dc voltage is applied to the edge ring 24 is controlled according to the deposition state. Further, the deposition state of the deposition is not limited to the deposition amount, and may be, for example, the thickness of the deposition film or the coverage of the deposition film.

[ monitoring of deposition State ]

Next, a method of monitoring the thickness of the deposit on the edge ring 24 is described with reference to FIG. 3. Fig. 3 is a diagram showing an example of a method for monitoring the deposition state of the edge ring. In the present monitoring method, a current meter 100 is connected to a power supply line connecting the first variable power supply 55 and the edge ring 24. When a predetermined dc voltage Vdc is applied to the first variable power supply 55, a potential difference Vdc is generated in a plasma sheath between the edge ring 24 and the plasma, and a current value i flowing through the ammeter 100 according to the amount of ions attracted to the edge ring 24 is measured.

When there is no deposit on the edge ring 24 as shown in fig. 3 (a), the value of the current i1 flowing through the ammeter 100 when the dc voltage is applied from the first variable power supply 55 to the edge ring 24 is calculated as i1 — Vdc/Rs … (1) when the resistance component of the plasma sheath is Rs.

On the other hand, when the deposit d is present on the edge ring 24 as shown in fig. 3 (b), the resistance component is a total resistance component (Rs' + Rd) obtained by adding the resistance component Rd based on the deposit d. Thus, the current value i2 that flows through the ammeter 100 when the dc voltage Vdc is applied to the edge ring 24 is calculated as i2 ═ Vdc/(Rs' + Rd) … (2).

The resistance component Rd of the deposit d is sufficiently large as compared with the resistance component Rs' of the edge ring 24, and when Rd > > Rs, it is predicted that the current value i decreases due to deposition of the deposit on the edge ring 24 according to the equations (1) and (2), i2< < i 1. Thus, by collecting data on the correlation between the amount of deposition on the edge ring and the current value i in advance and storing it in a memory in advance, it is possible to determine whether or not there is deposition on the edge ring 24 by monitoring the current value i during plasma processing.

For example, the correlation information with the coverage of the deposited film on the edge ring 24 can be calculated by monitoring the current value i, and data of the correlation between the coverage of the deposited film on the edge ring and the current value i is prepared in advance as shown in an example shown in the graph of fig. 4. Thus, the timing of applying the voltage to the edge ring 24 can be determined based on the current value i.

The threshold I shown in FIG. 4 is preset₁And a threshold value I₂As a timing for sputtering on the edge ring 24. However, only the threshold I may be set in advance₁Or threshold value I₂. For example, the current value I may be set to the threshold value I₁When the coverage of the deposited film on the edge ring 24 is determined to be equal to or more than the predetermined value, the application of the dc voltage to the edge ring is started. In this case, the current value I may be larger than the threshold value I₁When the coverage of the deposited film on the edge ring 24 is determined to be less than the predetermined value, the application of the DC voltage to the edge ring 24 is stopped。

The application of the dc voltage to the edge ring is not limited to two values of On (On) and Off (Off). for example, the application of the dc voltage to the edge ring may be controlled to be low (L ow) and High (High)₁In the following, the dc voltage applied to the edge ring is controlled to be low. In addition, the current value I may be the threshold value I₂In the following, the dc voltage applied to the edge ring is controlled to be high. In addition, when the current value I becomes larger than the threshold value I₁When the voltage is large, the application of the dc voltage to the edge ring is stopped.

Further, the method of monitoring the deposits on the edge ring 24 is not limited to the method shown in FIG. 3. For example, the thickness of the deposit on the edge ring 24 can be determined by illuminating the edge ring 24 with light and monitoring the reflected light thereof. Other known techniques may be used to monitor the state of the deposit.

[ Voltage application control treatment ]

Next, a voltage application control process of the edge ring according to one embodiment will be described with reference to fig. 5. Fig. 5 is a flowchart showing an example of the voltage application control process. This process is controlled by the control unit 200. Further, a program for causing the control unit 200 to execute the voltage application control processing method of the edge ring is stored in the memory of the control unit 200, and the program is read out from the memory by the CPU and executed.

Further, in the plasma processing apparatus 1, the voltage application control process is performed while the plasma of the process gas containing carbon is generated and the wafer W and the edge ring 24 are exposed to the plasma of the process gas.

When the present process is started, the control unit 200 acquires a current value i by using the ammeter 100 connected to the first variable power supply 55 (step S11). Next, control unit 200 determines whether or not current value I is equal to predetermined threshold value I₁Thereafter (step S12).

When the current value I is a predetermined threshold value I₁In the following case, the control unit 200 applies a dc voltage to the edge ring 24 (step S13). On the other hand, when the current value I is larger than the predetermined threshold value I₁If the voltage is large, the control unit 200 does not apply the dc voltage to the edge ring 24 (step S14).

Next, the control unit 200 determines whether or not to end the process (step S15). The controller 200 returns to step S11 and performs the processing after step S11 before determining that the present processing is ended in step S15.

Fig. 6 is a diagram showing an example of the effect of the voltage application control described above. In fig. 6 (a), the horizontal axis represents the application time of the dc voltage to the edge ring 24, and the vertical axis represents the consumption amount of the edge ring 24.

A line a in fig. 6 (a) shows an example of the consumption amount of the edge ring 24 when the dc voltage is continuously applied to the edge ring 24. In this case, the edge ring 24 is consumed according to the application time of the dc voltage to the edge ring 24.

On the other hand, a line B in fig. 6 (a) shows an example of the consumption amount of the edge ring 24 when the dc voltage is intermittently applied to the edge ring 24 as shown in fig. 6 (B) by the voltage application control according to the present embodiment. In this case, since the dc voltage is not continuously applied to the edge ring 24, the consumption amount of the edge ring 24 can be reduced compared to the line a to which the dc voltage is continuously applied. Thereby, the consumption of the edge ring 24 can be minimized.

[ variation in etching Rate ]

As described above, the consumption amount of the edge ring 24 can be reduced by intermittently applying the dc voltage to the edge ring 24. However, when a dc voltage is applied to the edge ring 24, process characteristics of the wafer W may be affected.

Fig. 7 shows an example of an experimental result when a dc voltage is applied to the edge ring 24 and a plasma etching process is performed on the wafer W. The process conditions in this experiment are shown below.

< Process conditions >

Gas CF₄Gas, C₄F₈Gas, N₂Gas (es)

Fixed value of HF power

L F fixed value of power

In fig. 7, the horizontal axis represents the DC voltage applied to the edge ring (edge ring DC voltage), and the vertical axis represents the etching rate (E/R) of the center portion (center) of the wafer W. As can be seen from this, the dc voltage is applied to the edge ring 24, so that the etching rate of the central portion of the wafer W increases, and the etching rate increases as the dc voltage applied to the edge ring 24 increases.

In fig. 8, the HF power and the L F power are changed in three stages to perform the plasma etching process, and the process conditions other than the HF power and the L F power are the same as those in fig. 7.

Line B shown in fig. 8 is a result of the etching rate when the HF power and the L F power are "medium" as the reference power for convenience of explanation, line a is a result of the etching rate when the HF power and the L F power are set higher than the reference power, and line C is a result of the etching rate when the HF power and the L F power are set lower than the reference power.

From this result, it is found that the etching rate increases in the center portion of the wafer W and the controllability of the etching rate deteriorates when the HF power and the L F power are varied in the three stages.

[ correction of HF Power and L F Power ]

Therefore, the amount of deviation of the etching rate at the center portion of the wafer W when the dc voltage is applied to the edge ring 24 from the etching rate when the dc voltage is not applied to the edge ring 24 is predicted from the relationship among the dc voltage applied to the edge ring 24, the etching rate, the HF power, and the L F power, and an approximate expression for not causing the etching rate to deviate is calculated for the obtained amount of deviation of the etching rate, and the correction value of the HF power and the correction value of the L F power are obtained from the approximate expressions.

Accordingly, when the dc voltage is applied to the edge ring 24, the HF power and the L F power applied during the plasma processing are corrected by the correction value of the HF power and the correction value of the L F power, whereby variations in the etching rate at the center portion of the wafer W can be suppressed, whereby the in-plane uniformity and controllability of the etching rate can be improved, and a reduction in the process characteristics for the wafer W when the voltage is applied to the edge ring 24 can be prevented.

In fig. 9 (a), the horizontal axis represents the number of wafers, and the vertical axis represents the etching rate at the center of the wafer W. The "measured value" in fig. 9 (a) is a result of measuring the etching rate at the center of the wafer W by changing the process parameters for each wafer using the experimental planning method.

The "evaluation value (calculated value)" in fig. 9 (a) is a result of obtaining an approximate expression indicating a relationship between the etching rate of the central portion of the wafer W and the process parameter by using multivariate analysis based on the "actually measured value", and calculating the etching rate of the central portion of the wafer W by changing the process parameter for each wafer in the same manner as the "actually measured value". Accordingly, the "evaluation value" is substantially the same as the "measured value", and therefore the accuracy of the approximate expression can be said to be high.

Fig. 9 (b) is correlation information obtained by calculating the correlation between the voltage applied to the edge ring 24 and the correction values of the HF power and the L F power, when the etching rate of the center portion of the wafer W is the same, from the approximate expression obtained based on the "actually measured value".

Thus, by correcting the HF power and the L F power according to the present embodiment, even when a dc voltage is applied to the edge ring 24, the etching rate at the center of the wafer W does not vary, and controllability of the etching rate can be ensured.

Fig. 9 (b) shows the correlation between the applied voltage of the edge ring and the HF power and the L F power in the case where the HF power and the L F power are changed at the same ratio, but the correlation is not limited to the case where the HF power and the L F power are changed at the same ratio.

[ correction of Process parameters ]

The approximate expression used may be an approximate expression using a linear function as long as it is an approximate expression approximating the actual measurement value, or may be an approximate expression using a function other than the linear function (such as a quadratic function).

The HF power and the L F power are corrected to what extent the variation (difference) of the dc voltage applied to the edge ring 24 should be corrected by the approximate expression, and therefore, the relevant information is stored in advance in the memory of the control unit 200.

For example, in the graph shown in fig. 9 b, the vertical axis (left) represents the ratio of the DC voltage applied to the edge ring 24 to the maximum output value (described as the edge ring DC voltage) of the first variable power supply 55 on the horizontal axis, the ratio of the correction to the set value of the HF power when the DC voltage is not applied to the edge ring 24 is represented by the vertical axis (right) represents the ratio of the correction to the set value of the L F power when the DC voltage is not applied to the edge ring 24.

In this example, when the dc voltage applied to the edge ring 24 is increased by "30%", the HF power is subtracted by "12.5%" from the set value, and the L F power is subtracted by "12.5%" from the set value.

By correcting the HF power and the L F power in accordance with the dc voltage applied to the edge ring 24 or the fluctuation thereof in this manner, it is possible to suppress an increase in the etching rate at the central portion of the wafer W even when the dc voltage is applied to the edge ring 24, and thus, it is possible to suppress the edge portion of the wafer W from being inclined by the dc voltage applied to the edge ring 24, and to improve controllability of the etching rate.

In the present embodiment, the HF power and the L F power are corrected based on the dc voltage applied to the edge ring 24 or the fluctuation amount thereof, but the process parameters to be corrected based on the dc voltage applied to the edge ring 24 are not limited to the HF power and the L F power.

The process parameter to be corrected may be, for example, a direct-current voltage applied from the second variable power supply 50 to the upper electrode 34, the type of gas supplied from the process gas supply source 66, the flow rate of the gas, or the pressure in the chamber 10.

That is, the process parameter may be at least any one of the high-frequency power of the first frequency applied from the first high-frequency power source 90, the high-frequency power of the second frequency lower than the first frequency applied from the second high-frequency power source 48, the gas supplied into the chamber 10, the pressure in the chamber 10, and the voltage applied from the second variable power source 50 to the upper electrode 34.

[ processing method and correction processing ]

Finally, a processing method and a correction process performed by the control unit 200 according to one embodiment will be described with reference to fig. 10 and 11. Fig. 10 is a flowchart showing an example of the processing method according to the embodiment. Fig. 11 is a flowchart showing an example of the correction processing according to the embodiment. Further, a program for causing the control unit 200 to execute the processing method and the correction processing method is stored in a memory of the control unit 200, and the CPU reads the program from the memory and executes the program.

When the process shown in fig. 10 is started, the voltage application control process of the edge ring is executed (step S10). In this voltage application control process, as shown in fig. 5, it is determined whether or not a direct current voltage is applied to the edge ring 24 based on the current value i (i.e., the state of the deposits on the edge ring 24), and the timing of applying the direct current voltage is controlled. At this time, in the determination as to whether or not to end the process of step S15 in fig. 5, when determining that the dc voltage is applied to the edge ring 24, the control unit 200 determines to end the process in fig. 5.

When the voltage application control process of the edge ring of fig. 5 ends, the process returns to fig. 10, and the correction process is executed (step S20). An example of the correction process will be described with reference to fig. 11. When the present correction process is started, the control section 200 acquires the value of the direct current voltage (DC voltage) applied to the edge ring 24 (step S21). Next, the control unit 200 calculates the difference between the current dc voltage value and the previous dc voltage value among the dc voltage values applied to the edge ring 24 (step S22). Further, the interval between the current dc voltage value and the previous dc voltage value may be set arbitrarily. The difference between the current dc voltage value and the previous dc voltage value is not limited to the difference, and may be a difference between the current dc voltage value and a previous or previous dc voltage value. For example, the difference between the current dc voltage value and the average value of the previous and last dc voltage values may be used.

Next, the control unit 200 refers to the memory in which the correlation information between the difference in the dc voltage applied to the edge ring 24 and the correction values of the HF power and the L F power shown in fig. 9 (b) is stored, and calculates the correction values of the HF power and the L F power with respect to the difference in the dc voltage value (step S23).

In the latter case, the step S22 may be skipped and the correction values of the HF power and the correction values of the L F power with respect to the current dc voltage value acquired in the step S21 may be calculated with reference to the correlation information stored in the memory in the step S23, instead of the step S22.

Next, the control unit 200 subtracts the correction value of the HF power calculated in step S23 from the set value of the HF power set in the process and sets the result as the corrected HF power (step S24), and subtracts the correction value of the L F power calculated in step S23 from the set value of the L F power set in the process and sets the result as the corrected L F power (step S24).

The controller 200 then applies the corrected HF power and L F power, controls other process conditions to set values set in the process, performs plasma processing (step S25), ends the correction processing, returns to FIG. 10, and ends the entire processing.

As described above, according to the correction processing of the present embodiment, the consumption of the edge ring 24 can be suppressed by intermittently controlling the timing of applying the dc voltage to the edge ring 24. When the dc voltage is applied to the edge ring 24, the process parameters (for example, the HF power) are corrected based on the applied dc voltage, whereby the increase in the etching rate at the center of the wafer W can be suppressed. This can suppress the consumption of the edge ring 24, suppress the inclination of the edge portion of the wafer W due to the dc voltage applied to the edge ring 24, suppress the increase in the etching rate of the central portion of the wafer W, and remove the deposits on the edge ring 24.

In particular, in the very low temperature etching in which the temperature of the stage 16 is controlled to be, for example, about-several tens ℃ to-one hundred and several tens ℃ to perform etching, the deposition amount of by-products generated by etching increases. Therefore, the processing method according to the present embodiment can be used as a more effective technique in the very low temperature etching. However, it is needless to say that the processing method according to the present embodiment is not limited to the extremely low temperature etching.

The processing method and the plasma processing apparatus according to one embodiment of the present disclosure are not limited to the above embodiments, but are all illustrative in all aspects. The above-described embodiments can be modified and improved in various ways without departing from the scope of the appended claims and the gist thereof. The features described in the above embodiments may be combined in other configurations as long as they are not contradictory, and in other ranges as long as they are not contradictory.

The voltage applied to the edge ring 24 is not limited to a direct current voltage, and may be an alternating current voltage. When an ac voltage is applied to the edge ring 24, the ac voltage is connected to an ac power supply via a matching unit and a dc blocking capacitor instead of the variable dc power supply 55. The AC power supply outputs an AC having a frequency f that ions in the plasma can follow, that is, a low-frequency or high-frequency AC having a frequency lower than the ion plasma frequency, and can change its power, voltage peak value, or effective value. When an ac voltage from an ac power source is applied to the edge ring 24 via a dc blocking capacitor in an etching process, a self-bias voltage is generated at the edge ring 24. That is, a negative dc voltage component is applied to the edge ring 24.

In the embodiments of the present disclosure, the etching process is explained, but not limited thereto. In the embodiment, a deposited film is formed on a substrate in an etching process, but the same effect can be obtained in a process of forming a deposited film on a substrate in a Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), or the like.

In addition, although the processing gas containing carbon is used in the deposition process of the present disclosure, the present disclosure is not limited thereto. For example, when plasma of a process gas capable of generating a deposition precursor (precursor) such as TEOS gas used in CVD is used, deposition is also generated in the edge ring. In PVD, precursors generated from a target are deposited on a process substrate by plasma sputtering, but they are also deposited on an edge ring. That is, deposition occurs also in the edge ring, as in the case where a precursor having deposition properties is present in the plasma space. In these processes, too, the occurrence of deposition on the edge ring can be prevented by applying a voltage to the edge ring, and the consumption of the edge ring can be minimized by observing the state of the deposited film and adjusting the applied voltage.

The Plasma processing apparatus of the present disclosure can be applied to any type of Plasma processing apparatus such as Capacitatively Coupled Plasma (CCP), Inductively Coupled Plasma (ICP), Radial L e Slot Antenna (R L SA), Electron Cyclotron Resonance Plasma (ECR), Helicon Wave Plasma (HWP), and the like.

In the present specification, a wafer W is described as an example of the object to be processed. However, the object to be processed is not limited to this, and various substrates and printed circuit boards used for FPD (Flat Panel Display) may be used.