阅读说明：本技术 一种增强体二极管的碳化硅功率mosfet器件 (Silicon carbide power MOSFET device of enhanced body diode ) 是由 盛况 任娜 郭清 朱郑允 于 2020-03-25 设计创作，主要内容包括：本发明提出一种增强体二极管的碳化硅功率MOSFET器件,元胞在第一表面为多边形或圆形布局设计,结构包含衬底、源极和漏极,还包括第一N型碳化硅区域,位于衬底上方；与所述第一N型碳化硅区域相邻的JFET区域；第一P型碳化硅区域,位于所述第一N型碳化硅区域上方、JFET区域的一侧；第一源极区域,位于所述第一N型碳化硅区域上方、JFET区域的另一侧；第一隔离栅极区域,位于第一P型碳化硅区域、JFET区域和第一源极区域上方。这种结构能实现在不牺牲MOSFET的工作性能的同时,增强体二极管的导通性能和抗浪涌电流能力,获得器件性能与可靠性之间的优化与平衡。(The invention provides a silicon carbide power MOSFET device of an enhanced body diode, wherein cells are designed in a polygonal or circular layout mode on a first surface, the structure comprises a substrate, a source electrode and a drain electrode, and the silicon carbide power MOSFET device also comprises a first N-type silicon carbide area positioned above the substrate; a JFET region adjacent to the first N-type silicon carbide region; the first P-type silicon carbide region is positioned above the first N-type silicon carbide region and on one side of the JFET region; the first source electrode region is positioned above the first N-type silicon carbide region and on the other side of the JFET region; a first isolated gate region over the first P-type silicon carbide region, the JFET region, and the first source region. The structure can enhance the conduction performance and the surge current resistance of the body diode without sacrificing the working performance of the MOSFET, and optimize and balance the performance and the reliability of the device.)

1. A silicon carbide power MOSFET device for enhancing body diodes, comprising:

at least one body diode enhancement cell arranged in the silicon carbide power MOSFET device in a polygonal or circular shape, the body diode enhancement cell comprising:

a substrate;

an N-type silicon carbide region having a first N-type doping and located over the substrate;

a JFET region or a trench isolation region located within the N-type silicon carbide region;

a metallization layer over the N-type silicon carbide region;

a P-type silicon carbide region or a schottky region, the P-type silicon carbide region having a P-type doping and being located on one side of the JFET region or the trench isolation region, the P-type silicon carbide region being in direct contact with the metallization layer to form an ohmic contact, the schottky region having an N-type doping and being located on one side of the JFET region or the trench isolation region, the schottky region being in direct contact with the metallization layer to form a schottky contact; and

a conventional source region on the other side of the JFET region.

2. The silicon carbide power MOSFET device of claim 1, further comprising: traditional silicon carbide MOSFET cells, traditional silicon carbide MOSFET cells are arranged in the silicon carbide power MOSFET device in a polygonal or circular shape.

3. The silicon carbide power MOSFET device of claim 1 or 2, wherein the polygon is a quadrilateral, a hexagon, or an octagon.

4. The silicon carbide power MOSFET device of claim 1, wherein the trench isolation region comprises a gate oxide layer between the N-type silicon carbide region and the gate electrode layer, a gate electrode layer, and a passivation layer on an upper surface of the gate electrode layer.

5. The silicon carbide power MOSFET device of claim 1, comprising a plurality of the body diode enhancement cells, the plurality of body diode enhancement cells being periodically arranged in a plurality of directions.

6. The silicon carbide power MOSFET device as claimed in claim 5, wherein the body diode enhancement cells in each direction are interleaved with conventional silicon carbide MOSFET cells.

7. The silicon carbide power MOSFET device of claim 5, wherein the minimum number of cells in one of the plurality of directions has a period of 4.

8. A silicon carbide power MOSFET device for enhancing body diodes, comprising:

a plurality of body diode enhancement cells arranged in the silicon carbide power MOSFET device in a polygonal or circular pattern, each body diode enhancement cell comprising:

a substrate;

an N-type silicon carbide region having a first N-type doping and located over the substrate;

a JFET region or a trench isolation region located within the N-type silicon carbide region;

a metallization layer over the N-type silicon carbide region;

a P-type silicon carbide region or a schottky region, the P-type silicon carbide region having a P-type doping and being located on one side of the JFET region or the trench isolation region, the P-type silicon carbide region being in direct contact with the metallization layer to form an ohmic contact, the schottky region having an N-type doping and being located on one side of the JFET region or the trench isolation region, the schottky region being in direct contact with the metallization layer to form a schottky contact; and

the conventional source region is positioned on the other side of the JFET region and comprises a P-type body region and an N-type source region, and the conventional source region is in direct contact with the metallization layer to form ohmic contact; wherein

When two body diode enhancement unit cells are adjacently arranged, the conventional source regions of the two body diode enhancement unit cells are in contact with each other, or the P-type silicon carbide regions or schottky regions of the two body diode enhancement unit cells are in contact with each other.

9. The silicon carbide power MOSFET device of claim 8, wherein the plurality of body diode enhancement unit cells are arranged in the same shape or in different shapes.

10. A method of fabricating a silicon carbide power MOSFET device for an enhanced body diode, comprising:

growing a layer of first N-type silicon carbide region on a substrate, wherein the first N-type silicon carbide region has a first N-type doping concentration;

injecting and generating a first P-type silicon carbide region on the first N-type silicon carbide region, wherein the first P-type silicon carbide region has a first P-type doping concentration;

implanting for multiple times on a first N-type silicon carbide region to generate a first source region, forming a JFET region between the first source region and a first P-type region, wherein the first source region comprises a second N-type silicon carbide region, a second P-type silicon carbide region and a third P-type silicon carbide region, the second N-type silicon carbide region has a second N-type doping concentration, the second P-type silicon carbide region has a second P-type doping concentration, and the third P-type silicon carbide region has a third P-type doping concentration;

preparing an isolation gate region on the first N-type silicon carbide region;

growing a first metallization layer on the first N-type silicon carbide region and the isolation gate region; and

a second metallization layer is grown below the substrate.

Technical Field

The present invention relates to semiconductor devices, and more particularly to a silicon carbide power MOSFET device for an enhancement body diode.

Background

The performance of traditional silicon-based semiconductor devices has gradually approached the physical limit of materials, and devices made of third-generation semiconductor materials represented by silicon carbide have excellent working capabilities of high frequency, high voltage, high temperature resistance, radiation resistance and the like, and can realize higher power density and higher efficiency.

The SiC MOSFET is taken as a representative of SiC switching devices, has the advantages of low switching loss, high working frequency, easiness in driving, suitability for parallel connection and the like, and is gradually popularized and used in application scenes of electric vehicles, charging piles, new energy power generation, industrial control, flexible direct-current power transmission and the like. Fig. 1 is a cross-sectional view 000 of a conventional power MOSFET cell. The conventional power MOSFET device comprises a drain electrode 1, a source electrode 11, a first isolation gate region 13, a substrate 2, a first N-type silicon carbide region 3, a first source electrode region 12 and a JFET region 7. The substrate 2 has a second surface 15. The first N-type silicon carbide region 3 is positioned above the substrate 2, has a first surface 14 and has a first N-type doping concentration; the JFET region 7 is adjacent to the first N-type silicon carbide region 3; the first source region 12 is located above the first N-type silicon carbide region 3 and on two sides of the JFET region 7, the first source region 12 includes a second N-type silicon carbide region 5, a second P-type silicon carbide region 4 and a third P-type silicon carbide region 6, the second N-type silicon carbide region 5 has a second N-type doping concentration, the second P-type silicon carbide region 4 has a second P-type doping concentration, and the third P-type silicon carbide region 6 has a third P-type doping concentration; the first isolation gate region 13 is positioned above the JFET region 7 and the first source region 12, and the first isolation gate region 13 comprises a gate oxide layer 8, a gate electrode layer 9 and a passivation layer 10; the source 11 comprises a first metallization layer extending over the first surface 14 and forming an ohmic contact 001 in direct contact with the first source region 12. The drain 1 comprises a second metallization layer extending below the second surface 15 and forming an ohmic contact 002 with the substrate 2.

Compared with the traditional Si IGBT module, the SiC MOSFET has lower conduction loss and faster switching frequency, can improve the system efficiency, and can avoid an external freewheeling diode due to the self-contained body diode inside the SiC MOSFET, thereby reducing the circuit design complexity and the system cost. However, in the development of power electronic equipment technology, the stability and reliability of the system are another important consideration while pursuing the work efficiency and power density. When a power electronic system has a fault, under the condition that a protection circuit has no time to react or the protection circuit is not available, the SiC MOSFET device needs to bear the impact of surge, and surge current mainly flows through a body diode of the SiC MOSFET. Research shows that when surge current exceeds the bearing capacity of the device, the SiC MOSFET device generates gate-source short circuit, and after dissection, phenomena of melting of an aluminum electrode on the surface of a chip, disappearance of a source ohmic contact layer, degradation of a P well region and the like are found.

Disclosure of Invention

To solve one or more of the above technical problems of the prior art, the present invention provides a silicon carbide power MOSFET device with an enhanced body diode.

According to an embodiment of the invention, there is provided a silicon carbide power MOSFET device for an enhanced body diode, comprising: at least one body diode enhancement cell arranged in the silicon carbide power MOSFET device in a polygonal or circular shape, the body diode enhancement cell comprising: a substrate; an N-type silicon carbide region having a first N-type doping and located over the substrate; a JFET region or a trench isolation region located within the N-type silicon carbide region; a metallization layer over the N-type silicon carbide region; a P-type silicon carbide region or a schottky region, the P-type silicon carbide region having a P-type doping and being located on one side of the JFET region or the trench isolation region, the P-type silicon carbide region being in direct contact with the metallization layer to form an ohmic contact, the schottky region having an N-type doping and being located on one side of the JFET region or the trench isolation region, the schottky region being in direct contact with the metallization layer to form a schottky contact; and a conventional source region on the other side of the JFET region.

According to an embodiment of the invention, there is provided a silicon carbide power MOSFET device for an enhanced body diode, comprising: a plurality of body diode enhancement cells arranged in the silicon carbide power MOSFET device in a polygonal or circular pattern, each body diode enhancement cell comprising: a substrate; an N-type silicon carbide region having a first N-type doping and located over the substrate; a JFET region or a trench isolation region located within the N-type silicon carbide region; a metallization layer over the N-type silicon carbide region; a P-type silicon carbide region or a schottky region, the P-type silicon carbide region having a P-type doping and being located on one side of the JFET region or the trench isolation region, the P-type silicon carbide region being in direct contact with the metallization layer to form an ohmic contact, the schottky region having an N-type doping and being located on one side of the JFET region or the trench isolation region, the schottky region being in direct contact with the metallization layer to form a schottky contact; the conventional source electrode region is positioned on the other side of the JFET region and comprises a P-type body region and an N-type source region, and the conventional source electrode region is directly contacted with the metallization layer to form ohmic contact; wherein when two body diode enhancement unit cells are adjacently arranged, the traditional source electrode regions of the two body diode enhancement unit cells are contacted, or the P-type silicon carbide regions or Schottky regions of the two enhancement type unit cells are contacted.

According to another embodiment of the invention, a method for manufacturing a silicon carbide power MOSFET device of an enhanced body diode is provided, which comprises the following steps: growing a layer of first N-type silicon carbide region on a substrate, wherein the first N-type silicon carbide region has a first N-type doping concentration; injecting and generating a first P-type silicon carbide region on the first N-type silicon carbide region, wherein the first P-type silicon carbide region has a first P-type doping concentration; implanting for multiple times on a first N-type silicon carbide region to generate a first source region, forming a JFET region between the first source region and a first P-type region, wherein the first source region comprises a second N-type silicon carbide region, a second P-type silicon carbide region and a third P-type silicon carbide region, the second N-type silicon carbide region has a second N-type doping concentration, the second P-type silicon carbide region has a second P-type doping concentration, and the third P-type silicon carbide region has a third P-type doping concentration; preparing an isolation gate region on the first N-type silicon carbide region; growing a first metallization layer on the first N-type silicon carbide region and the isolation gate region; and growing a second metallization layer below the substrate.

The silicon carbide power MOSFET power device of the enhanced body diode and the manufacturing method thereof can obviously improve the area of the body diode, enhance the conduction performance and the anti-surge capacity of the body diode, simultaneously can not influence the conduction capacity of the silicon carbide MOSFET, realize the enhancement of the conduction performance and the anti-surge current capacity of the body diode without sacrificing the working performance of the MOSFET, obtain the optimization and balance between the performance and the reliability of the device, have higher feasibility under the conditions of laboratories and industrial production and have better application prospect.

Drawings

FIG. 1 is a cross-sectional view of a conventional silicon carbide power MOSFET cell 000;

fig. 2-1 is a cross-sectional view of a body diode enhanced cell 100 according to an embodiment of the present invention;

fig. 2-2 is a top view of a silicon carbide power MOSFET device 100-1 according to an embodiment of the invention, the MOSFET device 100-1 comprising a plurality of body diode enhancement cells 100 as shown in fig. 2-1, the body diode enhancement cells being hexagonal and periodically arranged in the silicon carbide power MOSFET device 100-1 in a plurality of directions;

fig. 3-1 is a cross-sectional view of a body diode enhanced cell 200 according to yet another embodiment of the present invention;

fig. 3-2 is a top view of a silicon carbide power MOSFET device 200-1 according to yet another embodiment of the invention, the MOSFET device 200-1 including a plurality of body diode reinforcing cells 200 as shown in fig. 3-1, the body diode reinforcing cells being hexagonal and periodically arranged in the silicon carbide power MOSFET device 200-1 in a plurality of directions;

fig. 4-1 is a top view of a silicon carbide power MOSFET device 300 according to yet another embodiment of the invention, the MOSFET device 300 including a plurality of body diode enhancement cells 100 as shown in fig. 2-1 and a conventional silicon carbide MOSFET cell 000 that are hexagonally shaped and periodically arranged in a plurality of directions within the silicon carbide power MOSFET device 300;

fig. 4-2 is a cross-sectional view of a silicon carbide power MOSFET device 300-1 according to yet another embodiment of the invention, the MOSFET device 300-1 including at least one body diode enhancing cell 100 as shown in fig. 2-1;

fig. 5 is a top view of a silicon carbide power MOSFET device 400 according to yet another embodiment of the invention, the MOSFET device 400 including a plurality of body diode reinforcing cells 100 as shown in fig. 2-1, the body diode reinforcing cells 100 having a quadrilateral shape and being periodically arranged in the silicon carbide power MOSFET device 400 in a plurality of directions;

fig. 6 is a top view of a silicon carbide power MOSFET device 500 according to yet another embodiment of the invention, the MOSFET device 500 comprising a plurality of body diode enhancement cells 100 as shown in fig. 2-1, the body diode enhancement cells 100 being circular and periodically arranged in a plurality of directions within the silicon carbide power MOSFET device 500;

fig. 7 is a top view of a silicon carbide power MOSFET device 600 according to another embodiment of the invention, the MOSFET device 600 comprising a plurality of body diode reinforcing cells 100 as shown in fig. 2-1, the body diode reinforcing cells 100 having an octagonal or quadrilateral shape and being periodically arranged in the same shape or different shapes in multiple directions within the silicon carbide power MOSFET device 600;

fig. 8-1 is a cross-sectional view of a body diode enhanced cell 700 according to yet another embodiment of the present invention;

fig. 8-2 is a top view of a silicon carbide power MOSFET device 700-1 according to yet another embodiment of the invention, the MOSFET device 700-1 including a plurality of body diode reinforcing cells 700 as shown in fig. 8-1, the body diode reinforcing cells 700 having a hexagonal shape and being periodically arranged in the silicon carbide power MOSFET device 700-1 in a plurality of directions;

fig. 9 is a cross-sectional view of a body diode enhanced cell 800 according to yet another embodiment of the present invention;

fig. 10 is a flow chart 900 of a silicon carbide power MOSFET device with an enhancement body diode fabricated according to an embodiment of the present invention.

Detailed Description

Specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings, and it should be noted that the embodiments described herein are only for illustration and are not intended to limit the present invention. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those of ordinary skill in the art that these specific details are not required in order to practice the present invention. In other instances, well-known circuits, materials, or methods have not been described in detail in order to avoid obscuring the present invention.

Throughout the specification, reference to "one embodiment," "an embodiment," "one example," or "an example" means: the particular features, structures, or characteristics described in connection with the embodiment or example are included in at least one embodiment of the invention. Thus, the appearances of the phrases "in one embodiment," "in an embodiment," "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. Further, those of ordinary skill in the art will appreciate that the figures provided herein are for illustrative purposes, and wherein like reference numerals refer to like elements throughout. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.

The power MOSFET device of the invention includes but is not limited to a planar MOSFET, a trench MOSFET and a split gate MOSFET, the parasitic diode includes but is not limited to a pin diode and a Schottky diode, and the material includes but is not limited to silicon carbide, gallium nitride and silicon.

Fig. 2-1 is a cross-sectional view of a body diode enhanced cell 100 according to an embodiment of the present invention. In the embodiment shown in fig. 2-1, the body diode enhancement cell 100 includes a drain 16, a source 27, a first isolation gate region 29, a substrate 17, a first N-type silicon carbide region 18, a first P-type silicon carbide region 22, a first source region 28, and a JFET region 23. The substrate 17 has a second surface 31. The first N-type silicon carbide region 18, located above the substrate 17, having a first surface 30 with a first N-type doping concentration; the JFET region 23 is adjacent to the first N-type silicon carbide region 18; the first P-type silicon carbide region 22 is positioned on one side of the JFET region 23 and has a first P-type doping concentration; the first source region 28 is located above the first N-type silicon carbide region 18 and on the other side of the JFET region 23, the first source region 28 includes a second N-type silicon carbide region 20, a second P-type silicon carbide region 19 and a third P-type silicon carbide region 21, the second N-type silicon carbide region 20 has a second N-type doping concentration, the second P-type silicon carbide region 19 has a second P-type doping concentration, and the third P-type silicon carbide region 21 has a third P-type doping concentration; in one embodiment, the first P-type doping concentration is heavily doped, the second N-type doping concentration is heavily doped, the third P-type doping concentration may be the same as the first P-type doping concentration, or slightly higher or slightly lower than the first P-type doping concentration, and the second P-type doping concentration should be lower than the first P-type doping concentration and the third P-type doping concentration; the first isolation gate region 29 is located above the JFET region 23, the first P-type silicon carbide region 22 and the first source region 28, and the first isolation gate region 29 comprises a gate oxide layer 24, a gate electrode layer 25 and a passivation layer 26; the source 27 comprises a first metallization layer extending over the first surface 30 and forming ohmic contacts 101, 102 in simultaneous contact with the first P-type silicon carbide region 22 and the first source region 28. The drain 16 comprises a second metallization layer extending below the second surface 31 and forming an ohmic contact 103 with the substrate 17.

The substrate 17 may be 4H-silicon carbide or 6H-silicon carbide.

The JFET region 23 may be the same N-type silicon carbide epitaxial layer as the first N-type silicon carbide layer 18, may be a different N-type silicon carbide epitaxial layer, or may be formed by ion implantation in the first N-type silicon carbide layer 18.

The gate electrode layer 25 may be N-type or P-type doped polysilicon, a metal such as nickel or tungsten, or a compound such as titanium nitride.

The source electrode 27 and the drain electrode 16 may be made of copper, aluminum, nickel, titanium, or the like.

In one embodiment, when a negative voltage is applied to the gate electrode layer 25 of the device, the first P-type silicon carbide region 22 and the first N-type silicon carbide region can provide a P-i-N body diode when the source 27 conducts a large forward current or inrush surge current, and due to the large area of the first P-type silicon carbide region 22, the on-resistance of the device at the moment can be greatly reduced, and the capability of conducting a large forward current or resisting surge current is improved.

Fig. 2-2 is a top view of a sic power MOSFET device 100-1 according to an embodiment of the invention, where the MOSFET device 100-1 includes a plurality of body diode enhancement cells 100 as shown in fig. 2-1, and in one embodiment, the first P-type sic region and the first source region are both of a hexagonal design and are all periodically arranged in the first direction α 1001, the second direction β 1002, and the third direction γ 1003. compared with a conventional stripe cell design, the hexagonal design can increase the integration of the device, and the capability of obtaining a higher conducting current in the same device area is also beneficial to improve the surge resistance of the body diode, and the JFET region 23 is flanked by the first source region 28 and the first P-type sic region 22, respectively, the first source region 28 includes a second N-type sic region 20, a second P-type sic region 19, a third P-type sic region 21, where the second N-type sic region 20, the second P-type sic region 19, and the third P-type sic region 21 are all of the hexagonal structure in the first embodiment, and the second P-type sic region 20 is the hexagonal structure 22, and the first P-type sic region 22 is also the hexagonal structure 2-2.

The arrangement of the first source region 28 and the first P-type silicon carbide region 22 should be designed according to actual requirements, and the following two design principles should be followed: at most, only one first P-type silicon carbide region 22 is arranged on two sides of the JFET region, so that the current path in the first N-type silicon carbide region 18 cannot be narrowed due to the addition of the first P-type silicon carbide region 22 when the MOSFET is switched on; the first P-type silicon carbide regions 22 should be uniformly distributed on the first surface 30 to prevent local overheating caused by current maldistribution when the body diode or MOSFET is turned on.

Fig. 3-1 is a cross-sectional view of a body diode enhanced cell 200 according to yet another embodiment of the present invention. In the embodiment shown in fig. 3-1, the body diode enhancement cell 200 includes a drain 16, a source 27, a first isolated gate region 29, a substrate 17, a first N-type silicon carbide region 18, a first source region 28, and a schottky region 32. The substrate 17 has a second surface 31. The first N-type silicon carbide region 18, located above the substrate 17, having a first surface 30 with a first N-type doping concentration; the schottky region 32 is adjacent to the first N-type silicon carbide region 18 and has a third N-type doping concentration, which may be equal to or greater than the first N-type doping concentration; the first source region 28 is located above the first N-type silicon carbide region 18, the first source region 28 includes a second N-type silicon carbide region 20, a second P-type silicon carbide region 19 and a third P-type silicon carbide region 21, the second N-type silicon carbide region 20 has a second N-type doping concentration, the second P-type silicon carbide region 19 has a second P-type doping concentration, and the third P-type silicon carbide region 21 has a third P-type doping concentration; in one embodiment, the first P-type doping concentration is heavily doped, the second N-type doping concentration is heavily doped, the third P-type doping concentration may be the same as the first P-type doping concentration, or slightly higher or slightly lower than the first P-type doping concentration, and the second P-type doping concentration should be lower than the first P-type doping concentration and the third P-type doping concentration; the first isolation gate region 29 is located above the first N-type silicon carbide region 18 and the first source region 28, and the first isolation gate region 29 includes a gate oxide layer 24, a gate electrode layer 25 and a passivation layer 26; the source 27 includes a first metallization layer that extends over the first surface 30 and forms a schottky contact 201 with the schottky region 32 while simultaneously contacting the first source region 28 to form an ohmic contact 102. The drain 16 comprises a second metallization layer extending below the second surface 31 and forming an ohmic contact 103 with the substrate 17.

Fig. 3-2 is a top view of a sic power MOSFET device 200-1 according to a further embodiment of the present invention, where the MOSFET device 200-1 includes a plurality of body diode enhancement cells 200 as shown in fig. 3-1, and the schottky regions 32 and the first source regions 28 are both of a hexagonal design and are all periodically arranged in a first direction α 1001, a second direction β 1002, and a third direction γ 1003. compared to a conventional stripe cell design, the hexagonal design increases the integration of the device, achieves a higher on-state current capability in the same device area, and also facilitates the surge resistance of the body diode.a first source region 28 includes a second N-type sic region 20, a second P-type sic region 19, and a third P-type sic region 21. the second N-type sic region 20, the second P-type sic region 19, and the third P-type sic region 21 are all of a hexagonal structure.a schottky region 32 is also a hexagonal structure in one embodiment, and the number of the first N-type sic regions 20, the second P-type sic region 19, and the third P-type sic region 21 is greater than the first source region 32.

The body diode enhanced cell 200 and the silicon carbide power MOSFET device 200-1 shown in fig. 3-1 and 3-2 differ from the body diode enhanced cell 100 and the silicon carbide power MOSFET device 100-1 shown in fig. 2-1 and 2-2 in that the first P-type silicon carbide region 22 is replaced with a schottky region 32, and the schottky region 32 contacts the source 27 at the first surface 30 as a schottky contact 201. The structure enables the diode formed by the Schottky contact to be conducted in preference to the body diode when the device is turned off, and the turn-off speed of the device is greatly improved.

Fig. 4-1 is a top view of a silicon carbide power MOSFET device 300 according to yet another embodiment of the present invention, the MOSFET device 300 including a plurality of body diode enhancement cells 100 as shown in fig. 2-1 and conventional silicon carbide MOSFET cells 000. the silicon carbide power MOSFET device 300 shown in fig. 4-1 differs from the silicon carbide power MOSFET device 100-1 shown in fig. 2-2 in that the body diode enhancement cells 100 are periodically arranged in a first direction α, a second direction β, and a third direction γ 1003 with the conventional silicon carbide MOSFET cells 000 interposed therebetween, in one embodiment, the number of two types of cells in any one of the first direction α 1001, the second direction 3957, and the third direction γ 1003 is 1: 1. the minimum number of cells in the α direction shown in fig. 4-1 is 4, the number of 4 cells is 000a, 000b, 100a, and 100b, respectively, in one embodiment, the first and second directions are equivalent to the number of cells in a first direction 28, a first direction P28, a second direction P28, a third direction P28, a P22, a P28, a P22, a P28, a P22, a P20, a P1, a P20, a P22, a P20, a P1, a P22, a P1, a.

Fig. 4-2 is a cross-sectional view of four neighboring cells 000a, 000b, 100a and 100b in the direction α 1001 in accordance with another embodiment of the present invention, the MOSFET device 300-1 includes a plurality of body diode enhancement cells 100 as shown in fig. 2-1 and conventional silicon carbide MOSFET cells 000.000 a and 000b as shown in fig. 1. 000a includes a drain 1a, a source 11a, a substrate 2a, a first N-type silicon carbide region 3a, a JFET region 7a, a second N-type silicon carbide region 5a, a second P-type silicon carbide region 4a, a third P-type silicon carbide region 6a, a gate oxide layer 8a, a gate electrode layer 9a, a passivation layer 10 a.000b having the same structure as 000 a. 100a and 100b are body diode enhancement cells.100 a includes a drain 16a, a source 27a, a substrate 17a, a first N-type silicon carbide region 18a, a second P-type silicon carbide region 20a, a passivation layer 20a, P-type silicon carbide region 26a, P-type silicon carbide region b.

Fig. 5 is a top view of a silicon carbide power MOSFET device 400 according to yet another embodiment of the present invention, the MOSFET device 400 including a plurality of body diode reinforcing cells 100 as shown in fig. 2-1. the silicon carbide power MOSFET device 400 shown in fig. 5 differs from the silicon carbide power MOSFET device 100-1 shown in fig. 2-2 in that the first source region 28 and the first P-type silicon carbide region 22 of the silicon carbide power MOSFET device 400 are quadrilateral in shape and are both periodically arranged in the first direction α 1001 and the fourth direction 1004.

Fig. 6 is a cross-sectional view of a silicon carbide power MOSFET device 500 according to yet another embodiment of the present invention, the MOSFET device 500 including a plurality of body diode reinforcing cells 100 as shown in fig. 2-1. the silicon carbide power MOSFET device 500 shown in fig. 6 differs from the silicon carbide power MOSFET device 100-1 shown in fig. 2-2 in that the first source region 28 and the first P-type silicon carbide region 22 of the silicon carbide power MOSFET device 500 are circular in shape and are periodically arranged in the first direction α 1001, the second direction β 1002, and the third direction γ 1003.

Fig. 7 is a cross-sectional view of a silicon carbide power MOSFET device 600 according to yet another embodiment of the present invention, the MOSFET device 600 including a plurality of body diode enhancement cells 100 as shown in fig. 2-1, the body diode enhancement cells 100 being octagonal or quadrilateral, the periodic arrangement being the same or different in shape in multiple directions within the silicon carbide power MOSFET device 600. the silicon carbide power MOSFET device 600 shown in fig. 7 differs from the silicon carbide power MOSFET device 100-1 shown in fig. 2-2 in that the first source region 28 and the first P-type silicon carbide region 22 of the silicon carbide power MOSFET device 600 are octagonal, are periodically arranged in both the first direction α 1001 and the fourth direction 1004, and the octagonal dense arrangement fills the quadrilateral first source region, it is noted that the ratio of the first source region 28 to the first P-type silicon carbide region 22 may include other ratios than that of fig. 7. in an embodiment, the first source region 28 and the first P-type silicon carbide region 22 are not filled with the first octagonal dense arrangement, the first source region 28 and the first P-type silicon carbide region 22 may include a higher percentage of breakdown voltage than the octagonal dense arrangement, and the higher percentage of the integrated silicon carbide devices may include the octagonal dense arrangement of the octagonal first source region 28 and the octagonal high breakdown voltage-resistance of the integrated JFET device 28.

Fig. 8-1 is a cross-sectional view of a body diode enhanced cell 700 according to yet another embodiment of the present invention. In the embodiment shown in fig. 8-1, the body diode enhancement cell 700 includes a drain 16, a source 27, a second isolation gate region 37, a substrate 17, a first N-type silicon carbide region 18, a fourth P-type silicon carbide region 33, a first source region 28, and a JFET region 23. The substrate 17 has a second surface 31. The first N-type silicon carbide region 18, located above the substrate 17, having a first surface 30 with a first N-type doping concentration; the JFET region 23 is adjacent to the first N-type silicon carbide region 18; the fourth P-type silicon carbide region 33 is located on one side of the JFET region 23 and has a first P-type doping concentration; the first source region 28 is located above the first N-type silicon carbide region 18 and on the other side of the JFET region 23, the first source region 28 includes a second N-type silicon carbide region 20, a second P-type silicon carbide region 19 and a third P-type silicon carbide region 21, the second N-type silicon carbide region 20 has a second N-type doping concentration, the second P-type silicon carbide region 19 has a second P-type doping concentration, and the third P-type silicon carbide region 21 has a third P-type doping concentration; in one embodiment, the first P-type doping concentration is heavily doped, the second N-type doping concentration is heavily doped, the third P-type doping concentration may be the same as the first P-type doping concentration, or slightly higher or slightly lower than the first P-type doping concentration, and the second P-type doping concentration should be lower than the first P-type doping concentration and the third P-type doping concentration; the second isolation gate region 37 is located above the JFET region 23, the fourth P-type silicon carbide region 33 and the first source region 28, and the second isolation gate region 37 comprises a gate oxide layer 34, a gate electrode layer 35 and a passivation layer 36; the source 27 comprises a first metallization layer extending over the first surface 30 and forming ohmic contacts 101, 102 in simultaneous contact with the fourth P-type silicon carbide region 33 and the first source region 28. The drain 16 comprises a second metallization layer extending below the second surface 31 and forming an ohmic contact 103 with the substrate 17.

Fig. 8-2 is a top view of a sic power MOSFET device 700-1 according to an embodiment of the invention, where the MOSFET device 700-1 includes a plurality of body diode enhancement cells 700 as shown in fig. 8-1, the fourth P-type sic region 33 and the first source region 28 are both of hexagonal design and are all periodically arranged in a first direction α 1001, a second direction β 1002, and a third direction γ 1003, the JFET region 23 is flanked by the first source region 28 and the fourth P-type sic region 33, respectively, the first source region 28 includes a second N-type sic region 20, a second P-type sic region 19, and a third P-type sic region 21, where the second N-type sic region 20, the second P-type sic region 19, and the third P-type sic region 21 are all of hexagonal structure, and the fourth P-type sic region 33 is also of hexagonal structure, and in one embodiment, the number ratio of the first source region 28 to the fourth P-type sic region 33 is 1: 2.

The body diode enhancement cell 700 and the silicon carbide power MOSFET device 700-1 shown in fig. 8-1 and 8-2 are different from the body diode enhancement cell 100 and the silicon carbide power MOSFET device 100-1 shown in fig. 2-1 and 2-2 in that the body diode enhancement cell 700 is further characterized by comprising a fourth P-type silicon carbide region 33 and a second isolation gate region 37, the fourth P-type silicon carbide region 33 having a longer length than the first P-type silicon carbide region 22 in the first direction α 1001, and the second isolation gate region 37 having a shorter length than the first isolation gate region 29 in the first direction α 1001.

Fig. 9 is a cross-sectional view of a body diode enhanced cell 800 according to yet another embodiment of the present invention. In the embodiment shown in fig. 9, the body diode enhanced cell 800 includes a drain 16, a source 27, a third isolated gate region 41, a substrate 17, a first N-type silicon carbide region 18, a first P-type silicon carbide region 22, and a first source region 28. The substrate 17 has a second surface 31. The first N-type silicon carbide region 18, located above the substrate 17, having a first surface 30 with a first N-type doping concentration; the third isolation gate region 41 is located above the first N-type silicon carbide region 18, and the third isolation gate region 41 includes a gate oxide layer 38, a gate electrode layer 39 and a passivation layer 40; the first P-type silicon carbide region 22 is located on one side of the third isolation gate region 41 and has a first P-type doping concentration; the first source region 28 is located above the first N-type silicon carbide region 18 and on the other side of the third isolation gate region 41, the first source region 28 includes a second N-type silicon carbide region 20, a second P-type silicon carbide region 19 and a third P-type silicon carbide region 21, the second N-type silicon carbide region 20 has a second N-type doping concentration, the second P-type silicon carbide region 19 has a second P-type doping concentration, and the third P-type silicon carbide region 21 has a third P-type doping concentration; in one embodiment, the first P-type doping concentration is heavily doped, the second N-type doping concentration is heavily doped, the third P-type doping concentration may be the same as the first P-type doping concentration, or slightly higher or slightly lower than the first P-type doping concentration, and the second P-type doping concentration should be lower than the first P-type doping concentration and the third P-type doping concentration; the source 27 includes a first metallization layer that extends over the first surface 30 and forms a schottky contact 201 with the schottky region 38 while simultaneously contacting the first source region 28 to form an ohmic contact 102. The drain 16 comprises a second metallization layer extending below the second surface 31 and forming an ohmic contact 103 with the substrate 17.

The body diode enhanced cell 800 shown in fig. 9 differs from the body diode enhanced cell 100 shown in fig. 2-1 in that the body diode enhanced cell 800 is further characterized by having a third isolated gate region 41. The JFET resistor can be removed through the structural design, and the conduction performance and the surge resistance of the body diode are maintained, and meanwhile, the conduction capability of the MOSFET is improved.

It should be understood that, in the embodiments shown in fig. 1 to 9, not all of the single polygonal arrangements or the multiple polygonal combinations including the body diode enhanced cells are listed, and the shapes and the arrangements may be determined according to actual requirements.

Fig. 10 is a flow chart 900 of fabricating a silicon carbide power MOSFET for an enhancement body diode according to an embodiment of the invention. The manufacturing method comprises steps S1-S6.

Step S1, growing a first N-type silicon carbide region on the substrate, wherein the first N-type silicon carbide region has a first N-type doping concentration;

step S2, injecting and generating a first P type silicon carbide region on the first N type silicon carbide region, wherein the first P type silicon carbide region has a first P type doping concentration; in one embodiment, a mask is used for carrying out high-temperature ion implantation on the first N-type silicon carbide region to form a P-type region;

step S3, implanting a first N-type silicon carbide region a plurality of times to form a first source region, forming a JFET region between the first source region and the first P-type region, the first source region including a second N-type silicon carbide region having a second N-type doping concentration, a second P-type silicon carbide region having a second P-type doping concentration, and a third P-type silicon carbide region having a third P-type doping concentration, wherein in one embodiment, the JFET region is formed by ion implantation on the first N-type silicon carbide region using a mask and has a fourth N-type doping concentration;

step S4, forming an isolation gate region on the first N-type silicon carbide region, the oxide layer being grown by thermal oxygen, in one embodiment, the method further comprises forming thermal oxygen by chemical vapor deposition;

step S5, growing a first metallization layer on the first N-type silicon carbide region and on the first isolation gate region; in one embodiment, the first metallization layer is grown by using a Cu metal material to replace a traditional Al metal so as to improve the melting temperature of an electrode material, thereby improving the surge current resistance of the device;

step S6, a second metallization layer is grown under the substrate.

While the present invention has been described with reference to several exemplary embodiments, it is understood that the terminology used is intended to be in the nature of words of description and illustration, rather than of limitation. As the present invention may be embodied in several forms without departing from the spirit or essential characteristics thereof, it should also be understood that the above-described embodiments are not limited by any of the details of the foregoing description, but rather should be construed broadly within its spirit and scope as defined in the appended claims, and therefore all changes and modifications that fall within the meets and bounds of the claims, or equivalences of such meets and bounds are therefore intended to be embraced by the appended claims.