阅读说明：本技术 一种功率拓扑电路、控制方法及控制装置 (Power topology circuit, control method and control device ) 是由 赵龙 曹炳 李爱刚 于 2020-04-22 设计创作，主要内容包括：本发明适用于功率拓扑电路技术领域,提供了一种功率拓扑电路、控制方法及控制装置,功率拓扑电路包括：一直流电源、一升压电感、驱动单元、箝位单元、输出母线滤波单元、母线输出端；直流电源的正极与升压电感一端连接,直流电源的负极分别与驱动单元、输出母线滤波单元以及母线输出端的负极连接,升压电感另一端与驱动单元连接,箝位单元分别与驱动单元以及滤波单元连接,输出母线滤波单元还分别与母线输出端的正极以及负极连接,输出母线滤波单元设置有一母线中心节点以及一端与母线中心节点连接的第一输出母线滤波电容,箝位单元设置有一箝位电容。本发明的功率拓扑电路控制简单以及成本低。(The invention is suitable for the technical field of power topological circuits, and provides a power topological circuit, a control method and a control device, wherein the power topological circuit comprises: the device comprises a direct current power supply, a boost inductor, a driving unit, a clamping unit, an output bus filtering unit and a bus output end; the direct-current power supply comprises a direct-current power supply, a driving unit, an output bus filtering unit, a bus output end, a clamping unit, a bus central node, a first output bus filtering capacitor and a clamping unit, wherein the positive electrode of the direct-current power supply is connected with one end of a boosting inductor, the negative electrode of the direct-current power supply is respectively connected with the driving unit, the output bus filtering unit and the negative electrode of the bus output end, the other end of the boosting inductor is connected with the driving unit, the clamping unit is respectively connected with the driving unit and the filtering unit, the output bus filtering unit is also respectively connected with the positive electrode and the negative electrode. The power topology circuit of the invention has simple control and low cost.)

1. A power topology circuit, comprising: the device comprises a direct current power supply, a boost inductor, a driving unit, a clamping unit, an output bus filtering unit and a bus output end; the positive electrode of the direct current power supply is connected with one end of the boost inductor, the negative electrode of the direct current power supply is respectively connected with the driving unit, the output bus filtering unit and the negative electrode of the bus output end, the other end of the boost inductor is connected with the driving unit, the clamping unit is respectively connected with the driving unit and the filtering unit, the output bus filtering unit is also respectively connected with the positive electrode and the negative electrode of the bus output end, the output bus filtering unit is provided with a bus center node and a first output bus filtering capacitor, one end of the first output bus filtering capacitor is connected with the bus center node, and the clamping unit is provided with a clamping capacitor;

the driving unit comprises a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube, wherein the first power switch tube is respectively connected with the output bus filtering unit, the anode of the bus output end, one end of a clamping capacitor and the second power switch tube, the second power switch tube is also respectively connected with one end of the clamping capacitor, a boosting inductor and the third power switch tube, the third power switch tube is also respectively connected with the other end of the clamping capacitor and the fourth power switch tube, and the fourth power switch tube is also respectively connected with the cathode of the direct-current power supply, the other end of the first output bus filtering capacitor and the cathode of the bus output end;

the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube respectively meet a preset first driving time sequence, a preset second driving time sequence, a preset third driving time sequence and a preset fourth driving time sequence.

2. The power topology circuit according to claim 1, wherein said clamping unit comprises a first clamping diode and a second clamping diode, wherein a cathode of said first clamping diode is connected to one end of said clamping capacitor, said first power switch and said second power switch respectively, an anode of said first clamping diode is connected to said bus bar center node and a cathode of said second clamping diode respectively, and an anode of said second clamping diode is connected to the other end of said clamping capacitor, said third power switch and said fourth power switch respectively.

3. The power topology circuit according to claim 2, wherein said output bus filter unit further comprises a second output bus filter capacitor, one end of said second output bus filter capacitor is connected to said first power switch tube and the anode of said bus output terminal, and the other end of said second output bus filter capacitor is connected to one end of said first output bus filter capacitor, said bus center node, and the connection point between said first clamping diode and said second clamping diode.

4. The power topology circuit of claim 3, wherein the first power switch, the second power switch, the third power switch and the fourth power switch correspond to a first transistor, a second transistor, a third transistor and a fourth transistor, respectively, a collector of the first transistor is connected to a connection line between the first output bus filter capacitor and the positive electrode of the bus output terminal, an emitter of the first transistor is connected to a connection line between a collector of the second transistor, one end of a clamping capacitor and the negative electrode of the first clamping diode, an emitter of the second transistor is connected to a connection line between the boost inductor and a collector of the third transistor, and an emitter of the third transistor is connected to a connection line between the other end of the clamping capacitor, the positive electrode of the second clamping diode and a collector of the fourth power switch, and an emitter of the fourth triode is connected to a connecting wire among the negative electrode of the direct-current power supply, the other end of the second output bus filter capacitor and the negative electrode of the bus output end.

5. The power topology circuit of claim 4, wherein the driving unit further comprises a first diode, a second diode, a third diode, and a fourth diode, wherein an anode of the first diode is connected to an emitter of the first transistor, a cathode of the first diode is connected to a collector of the first transistor, an anode of the second diode is connected to an emitter of the second transistor, the second diode is connected to a collector of the second transistor, an anode of the third diode is connected to an emitter of the third transistor, a cathode of the third diode is connected to a collector of the third transistor, an anode of the fourth diode is connected to an emitter of the fourth transistor, and a cathode of the fourth diode is connected to a collector of the fourth transistor.

6. A control method of a power topology circuit, for controlling the power topology circuit of any one of claims 1-5, the control method of the power topology circuit comprising the steps of:

respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence corresponding to a first power switching tube, a second power switching tube, a third power switching tube and a fourth power switching tube in the driving unit;

and outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube to be switched on or switched off, so that the amount of electric charge discharged from the clamping capacitor to the bus output end in each period is equal to the amount of electric charge charged to the first output bus filter capacitor in each period, and the potential of a bus center node is kept unchanged so as to control the bus output end to output stable voltage.

7. The method according to claim 6, wherein the first driving signal and the second driving signal are both high level on the whole control time axis, so that the first power switch tube and the second power switch tube are in a normally-on state;

in an initial state in each period, the third driving signal and the fourth driving signal are both at a low level, so that the third power switch tube is in an off state;

in a first time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

in a second time period in each period, the third driving signal and the fourth driving signal are both at a high level, so that the third power switch tube and the fourth power switch tube are both in an on state;

in a third time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

during a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in an off state until the next cycle arrives.

8. A control apparatus for a power topology circuit, the control apparatus for controlling the power topology circuit according to any one of claims 1 to 5, the control apparatus for the power topology circuit comprising:

the acquisition unit is used for respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence corresponding to a first power switching tube, a second power switching tube, a third power switching tube and a fourth power switching tube in the driving unit;

and the switching tube driving unit is used for outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switching tube, the second power switching tube, the third power switching tube and the fourth power switching tube to be switched on or switched off, so that the amount of electric charge discharged from the clamping capacitor to the bus output end in each period is equal to the amount of electric charge charged to the first output bus filter capacitor in each period, and the potential of a bus center node is kept unchanged so as to control the bus output end to output stable voltage.

9. The control device of the power topology circuit according to claim 8, wherein the first driving signal and the second driving signal are both high level on the whole control time axis, so that the first power switch tube and the second power switch tube are in a normally-on state;

in an initial state in each period, the third driving signal and the fourth driving signal are both at a low level, so that the third power switch tube is in an off state;

in a first time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

in a second time period in each period, the third driving signal and the fourth driving signal are both at a high level, so that the third power switch tube and the fourth power switch tube are both in an on state;

in a third time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

during a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in an off state until the next cycle arrives.

Technical Field

The invention belongs to the technical field of power topology circuits, and particularly relates to a power topology circuit, a control method and a control device.

Background

In power electronic topologies, Boost is the most basic DC/DC topology, and is applied to various power electronic devices. The photovoltaic inverter comprises a DC/DC part and a DC/AC part, wherein the DC/DC part not only can stabilize the input voltage of the DC/AC side, but also can lead the solar panel to output with Maximum Power Point Tracking (MPPT), thereby improving the generating capacity of the photovoltaic inverter, so the DC/DC part has a vital effect on the performance and the efficiency of the photovoltaic inverter.

The Boost circuit is simple in topology and simple in control, is widely applied to a DC/DC side of a photovoltaic inverter, and can meet the voltage withstanding requirement of a low-voltage system by using a two-level Boost.

Now the three-level boost circuit comprises: the three-level Boost circuit of symmetry Boost, flying capacitor three-level Boost circuit.

Wherein, the symmetry Boost three-level Boost circuit: as shown in fig. 1 and fig. 2, because a diode D1 and a diode D2 exist between the bus output and the DC source DC, the switching transistors Q1 and Q2 cannot guarantee simultaneous on and off, and when the midpoint voltages of the capacitor C1 and the capacitor C2 have a deviation, the driving timings of the switching transistor Q1 and the switching transistor Q2 need to be adjusted to stabilize the midpoint voltages of the capacitor C1 and the capacitor C2, so that a severe common-mode signal exists between the output voltage and the ground, and a common-mode interference is formed between the output voltage and the ground, which causes a high leakage current and affects the normal operation of the system. The symmetrical Boost three-level Boost voltage requires two inductors and two independent driving circuits, which also increase the system cost.

Wherein, flying capacitor three-level boost circuit: as shown in fig. 3 and 4, although the flying capacitor tri-level does not have the problem of common mode interference, the flying capacitor C3 needs to be precharged by the flying capacitor tri-level, the precharge circuit is relatively complex in design, and in steady-state operation, the voltage on the capacitor C3 needs to be controlled at any time, so that the control is cumbersome, the capacitance value of the capacitor C3 is relatively large, the cost is relatively high, and the flying capacitor tri-level is difficult to be widely applied in engineering.

Disclosure of Invention

The embodiment of the invention provides a power topology circuit, aiming at solving the problems of complicated control and high cost of the power topology circuit in the prior art.

An embodiment of the present invention provides a power topology circuit, where the power topology circuit includes: the device comprises a direct current power supply, a boost inductor, a driving unit, a clamping unit, an output bus filtering unit and a bus output end; the positive electrode of the direct current power supply is connected with one end of the boost inductor, the negative electrode of the direct current power supply is respectively connected with the driving unit, the output bus filtering unit and the negative electrode of the bus output end, the other end of the boost inductor is connected with the driving unit, the clamping unit is respectively connected with the driving unit and the filtering unit, the output bus filtering unit is also respectively connected with the positive electrode and the negative electrode of the bus output end, the output bus filtering unit is provided with a bus center node and a first output bus filtering capacitor, one end of the first output bus filtering capacitor is connected with the bus center node, and the clamping unit is provided with a clamping capacitor;

the driving unit comprises a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube, wherein the first power switch tube is respectively connected with the output bus filtering unit, the anode of the bus output end, one end of a clamping capacitor and the second power switch tube, the second power switch tube is also respectively connected with one end of the clamping capacitor, a boosting inductor and the third power switch tube, the third power switch tube is also respectively connected with the other end of the clamping capacitor and the fourth power switch tube, and the fourth power switch tube is also respectively connected with the cathode of the direct-current power supply, the other end of the first output bus filtering capacitor and the cathode of the bus output end;

the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube respectively meet a preset first driving time sequence, a preset second driving time sequence, a preset third driving time sequence and a preset fourth driving time sequence.

Furthermore, the clamping unit includes a first clamping diode and a second clamping diode, wherein a cathode of the first clamping diode is connected to one end of the clamping capacitor, the first power switch tube and the second power switch tube, respectively, an anode of the first clamping diode is connected to the bus bar center node and a cathode of the second clamping diode, and an anode of the second clamping diode is connected to the other end of the clamping capacitor, the third power switch tube and the fourth power switch tube, respectively.

Furthermore, the output bus filter unit further comprises a second output bus filter capacitor, one end of the second output bus filter capacitor is connected to the first power switch tube and the anode of the bus output end, and the other end of the second output bus filter capacitor is connected to one end of the first output bus filter capacitor, the bus center node and a connection point between the first clamping diode and the second clamping diode.

Furthermore, the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube are respectively corresponding to a first triode, a second triode, a third triode and a fourth triode, wherein a collector of the first triode is connected to a connecting wire between the first output bus filter capacitor and the positive electrode of the bus output end, an emitter of the first triode is connected to a connecting wire between a collector of the second triode, one end of a clamping capacitor and the negative electrode of the first clamping diode, an emitter of the second triode is connected to a connecting wire between the boosting inductor and the collector of the third triode, and an emitter of the third triode is connected to a connecting wire between the other end of the clamping capacitor, the positive electrode of the second clamping diode and the collector of the fourth power switch tube, and an emitter of the fourth triode is connected to a connecting wire among the negative electrode of the direct-current power supply, the other end of the second output bus filter capacitor and the negative electrode of the bus output end.

Furthermore, the driving unit further comprises a first diode, a second diode, a third diode and a fourth diode, wherein the anode of the first diode is connected with the emitter of the first triode, the cathode of the first diode is connected with the collector of the first triode, the anode of the second diode is connected with the emitter of the second triode, the second diode is connected with the collector of the second triode, the anode of the third diode is connected with the emitter of the third triode, the cathode of the third diode is connected with the collector of the third triode, the anode of the fourth diode is connected with the emitter of the fourth triode, and the cathode of the fourth diode is connected with the collector of the fourth triode.

The embodiment of the present invention further provides a control method for a power topology circuit, which is used for controlling the power topology circuit provided in the above embodiment, and the control method for the power topology circuit includes the following steps:

respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence corresponding to a first power switching tube, a second power switching tube, a third power switching tube and a fourth power switching tube in the driving unit;

and outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube to be switched on or switched off, so that the amount of electric charge discharged from the clamping capacitor to the bus output end in each period is equal to the amount of electric charge charged to the first output bus filter capacitor in each period, and the potential of a bus center node is kept unchanged so as to control the bus output end to output stable voltage.

Furthermore, the first driving signal and the second driving signal are both at a high level on the whole control time axis, so that the first power switch tube and the second power switch tube are in a normally-on state;

in an initial state in each period, the third driving signal and the fourth driving signal are both at a low level, so that the third power switch tube is in an off state;

in a first time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

in a second time period in each period, the third driving signal and the fourth driving signal are both at a high level, so that the third power switch tube and the fourth power switch tube are both in an on state;

in a third time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

during a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in an off state until the next cycle arrives.

An embodiment of the present invention further provides a control device for a power topology circuit, configured to control the power topology circuit provided in the foregoing embodiment, where the control device for the power topology circuit includes:

the acquisition unit is used for respectively acquiring a first driving time sequence, a second driving time sequence, a third driving time sequence and a fourth driving time sequence corresponding to a first power switching tube, a second power switching tube, a third power switching tube and a fourth power switching tube in the driving unit;

and the switching tube driving unit is used for outputting a first driving signal, a second driving signal, a third driving signal and a fourth driving signal based on the first driving time sequence, the second driving time sequence, the third driving time sequence and the fourth driving time sequence so as to drive the first power switching tube, the second power switching tube, the third power switching tube and the fourth power switching tube to be switched on or switched off, so that the amount of electric charge discharged from the clamping capacitor to the bus output end in each period is equal to the amount of electric charge charged to the first output bus filter capacitor in each period, and the potential of a bus center node is kept unchanged so as to control the bus output end to output stable voltage.

Furthermore, the first driving signal and the second driving signal are both at a high level on the whole control time axis, so that the first power switch tube and the second power switch tube are in a normally-on state;

in an initial state in each period, the third driving signal and the fourth driving signal are both at a low level, so that the third power switch tube is in an off state;

in a first time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

in a second time period in each period, the third driving signal and the fourth driving signal are both at a high level, so that the third power switch tube and the fourth power switch tube are both in an on state;

in a third time period in each cycle, the third driving signal is at a high level, and the fourth driving signal is at a low level, so that the third power switch tube is in an on state, and the fourth power switch tube is in an off state;

during a fourth period of time in each cycle, the third driving signal and the fourth driving signal are at a low level, so that the third power switch tube and the fourth power switch tube are in an off state until the next cycle arrives.

The invention achieves the following beneficial effects: the switching on or off of a first power switch tube, a second power switch tube, a third power switch tube and a fourth power switch tube in a driving unit is controlled through a preset first driving time sequence, a preset second driving time sequence, a preset third driving time sequence and a preset fourth driving time sequence, so that the discharging charge quantity of the clamping capacitor to the bus output end in each period is equal to the charging charge quantity of the first output bus filter capacitor in each period, and the potential of a bus center node is kept unchanged to control the bus output end to output stable voltage. Can be stable like this transmit the voltage of boost inductance output to the bus output for power topology circuit can provide stable voltage, and this power topology circuit has following advantage simultaneously:

1. the first power switch tube and the second power switch tube are in a normally-on state through the first driving time sequence and the second driving time sequence, the third power switch tube and the fourth power switch tube only need to meet the third driving time sequence and the fourth driving time sequence, and the driving of the third power switch tube and the fourth power switch tube does not need independent control, so that the control of the first power switch tube, the second power switch tube, the third power switch tube and the fourth power switch tube is simple.

2. In the power topological circuit, the output ends of the direct-current power supply and the bus are in common negative polarity, so that the power topological circuit does not have the problem of work mode interference.

3. In the power topological circuit, only one boost inductor is needed, so the cost in the power topological circuit is low.

Drawings

Fig. 1 is a circuit diagram of a symmetrical Boost three-level Boost circuit provided in the prior art;

fig. 2 is a driving timing diagram of a symmetrical Boost three-level Boost circuit provided in the prior art;

FIG. 3 is a circuit diagram of a flying capacitor three-level boost circuit provided by the prior art;

FIG. 4 is a timing diagram illustrating the driving of a flying capacitor three-level boost circuit according to the prior art;

FIG. 5 is a circuit diagram of a power topology circuit provided by an embodiment of the invention;

fig. 6 is a driving timing diagram of a power topology circuit according to an embodiment of the present invention;

fig. 7 is a flowchart of a control method of a power topology circuit according to an embodiment of the present invention;

fig. 8 is a schematic structural diagram of a control device of a power topology circuit according to an embodiment of the present invention.

Detailed Description

In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

The power topology circuit comprises a direct-current power supply DC, a boosting inductor L, a power switch tube Q1, a power switch tube Q2, a power switch tube Q3, a power switch tube Q4, a capacitor Cx, an output bus filter capacitor C2 and a bus output end, wherein the positive pole of the direct-current power supply DC is connected with one end of the boosting inductor L, the negative pole of the direct-current power supply DC is connected with the emitter of the power switch tube Q4 and one end of the output bus filter capacitor C2, the other end of the boosting inductor L is connected with the emitter of the power switch tube Q2 and the negative pole of the collector of the power switch tube Q3, the emitter of the power switch tube Q3 is connected with the collector of the power switch tube Q4 and one end of the capacitor Cx, the collector of the power switch tube Q2 is connected with the emitter of the power switch tube Q1, the other end of the capacitor Cx is connected, the collector of the power switch tube Q1 is connected with the positive pole of the power switch tube Q3645, the other end of the power switch tube Q1 is connected, the boost circuit is realized by controlling the logic circuit, the power switch tube Q5848, the power switch tube has the advantages of a single-time-sequence circuit, the power switch tube Q-switch tube and the power-switch tube power topology circuit can be controlled by the common-switch tube, the power-output power switch tube, the power switch tube Q-output power-output.