阅读说明：本技术 一种GaInP/GaAs/HIT三结叠层太阳能电池及其制备方法 (GaInP/GaAs/HIT triple-junction laminated solar cell and preparation method thereof ) 是由 方亮 肖祖峰 黄嘉敬 何键华 胡丹 于 2020-04-20 设计创作，主要内容包括：本发明公开了一种GaInP/GaAs/HIT三结叠层太阳能电池及其制备方法,包括依次叠层设置的底电池、中间电池和顶电池,所述底电池和中间电池通过第一隧穿结连接,所述中间电池和顶电池通过第二隧穿结连接；所述底电池为HIT太阳能电池,即HIT子电池；所述中电池为GaAs太阳能电池,所述顶电池为GaInP太阳能电池,所述顶电池和中电池形成为GaInP/GaAs双结子电池。本发明的GaInP/GaAs/HIT三结叠层太阳能电池具有电转换效率高、稳定性好、成本低的优点。(The invention discloses a GaInP/GaAs/HIT three-junction laminated solar cell and a preparation method thereof, wherein the GaInP/GaAs/HIT three-junction laminated solar cell comprises a bottom cell, a middle cell and a top cell which are sequentially laminated, wherein the bottom cell and the middle cell are connected through a first tunneling junction, and the middle cell and the top cell are connected through a second tunneling junction; the bottom cell is an HIT solar cell, namely an HIT sub-cell; the middle cell is a GaAs solar cell, the top cell is a GaInP solar cell, and the top cell and the middle cell are formed into a GaInP/GaAs double-junction cell. The GaInP/GaAs/HIT triple-junction laminated solar cell has the advantages of high electric conversion efficiency, good stability and low cost.)

1. A GaInP/GaAs/HIT triple-junction tandem solar cell, characterized in that: the battery pack comprises a bottom battery, a middle battery and a top battery which are sequentially stacked, wherein the bottom battery and the middle battery are connected through a first tunneling junction, and the middle battery and the top battery are connected through a second tunneling junction; the bottom cell is an HIT solar cell, namely an HIT sub-cell; the middle cell is a GaAs solar cell, the top cell is a GaInP solar cell, and the top cell and the middle cell are formed into a GaInP/GaAs double-junction cell.

2. The GaInP/GaAs/HIT triple-junction solar cell of claim 1, wherein: the bottom cell comprises a TCO layer, a p-type amorphous silicon BSF layer (p-a-SiBSF layer), a first intrinsic amorphous silicon passivation layer (first i-a-Si passivation layer), a p-type Si substrate, a second intrinsic amorphous silicon passivation layer (second i-a-Si passivation layer) and an n-type amorphous silicon emission layer (n-a-Si emission layer) which are sequentially stacked from bottom to top; the thickness of the TCO layer is 50nm-150 nm; the thickness of the p-type amorphous silicon BSF layer is 5nm-20 nm; the thicknesses of the first intrinsic amorphous silicon passivation layer and the second intrinsic amorphous silicon passivation layer are 1nm-10 nm; the thickness of the n-type amorphous silicon emission layer is 10nm-100 nm.

3. The GaInP/GaAs/HIT triple-junction solar cell of claim 1, wherein: the middle cell comprises p-type doped Al which is sequentially stacked from bottom to top_xGa_1-xAs back field layer, p-type doped GaAs base region, n-type doped GaAs emitter region and n-type doped Al_xGa_1-xAn As window layer; the p-type doped Al_xGa_1-xThe thickness of the As back field layer is 100nm-200nm, and the doping concentration is1×10¹⁷-1×10¹⁹cm^-3The thickness of the p-type doped GaAs base region is 1000nm-2000nm, and the doping concentration is 1 × 10¹⁶-1×10¹⁷cm^-3The thickness of the n-type doped GaAs emission region is 50nm-200nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3(ii) a The n-type doped Al_xGa_1-xThe thickness of the As window layer is 30nm-100nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3(ii) a Wherein x is more than or equal to 0.3 and less than or equal to 0.5.

4. The GaInP/GaAs/HIT triple-junction stacked solar cell of claim 1, wherein the top cell comprises a p-type doped AlGaInP back field layer, a p-type doped GaInP base region, an n-type doped GaInP emitter region and an n-type doped AlInP window layer which are stacked from bottom to top in sequence, the thickness of the p-type doped AlGaInP back field layer is 100nm-200nm, and the doping concentration of the p-type doped AlGaInP back field layer is 1 × 10nm¹⁷-1×10¹⁹cm^-3The thickness of the p-type doped GaInP base region is 500nm-1000nm, and the doping concentration is 1 × 10¹⁶-1×10¹⁷cm^-3The thickness of the n-type doped GaInP emitting region is 50nm-100nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3The thickness of the n-type doped AlInP window layer is 30nm-100nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3。

5. The GaInP/GaAs/HIT triple-junction solar cell of claim 1, wherein: the top cell has a forbidden band width of 1.86eV, the middle cell has a forbidden band width of 1.4eV, and the bottom cell has a forbidden band width of 1.1 eV.

6. The GaInP/GaAs/HIT triple-junction solar cell of claim 1, wherein: the first tunneling junction comprises a tunneling layer and a bonding layer which are arranged in a stacked mode, the tunneling layer is connected with the middle battery, and the bonding layer is connected with the bottom battery; the tunneling layer comprises a first p type layer sequentially arranged from bottom to top in a laminated mannerAlGaAs layer and first n-type GaInP layer, the thickness of the first p-type AlGaAs layer is 10nm-100nm, and the doping concentration is 1 × 10¹⁸-1×10²⁰cm^-3The thickness of the first n-type GaInP layer is 10nm-100nm, and the doping concentration is 1 × 10¹⁸-1×10²⁰cm^-3(ii) a The first p-type AlGaAs layer is connected with the bonding layer; the first n-type GaInP layer and the p-type doped Al of the middle cell_xGa_1-xThe As back field layer is connected, wherein x is more than or equal to 0.3 and less than or equal to 0.5.

7. The GaInP/GaAs/HIT triple-junction solar cell of claim 6, wherein the bonding layer is an n-type doped GaAs layer with a doping concentration of 1 × 10¹⁸-1×10²⁰cm^-3The thickness is 50nm-100 nm.

8. The GaInP/GaAs/HIT triple-junction stacked solar cell of claim 1, wherein the second tunneling junction comprises a second p-type AlGaAs layer and a second n-type GaInP layer which are stacked from bottom to top, the second p-type GaInP layer is connected with the middle cell, the second n-type GaInP layer is connected with the top cell, the thickness of the second p-type AlGaAs layer is 10nm-100nm, and the doping concentration of the second p-type AlGaAs layer is 1 × 10nm¹⁸-1×10²⁰cm^-3The thickness of the second n-type GaInP layer is 10nm-100nm, and the doping concentration is 1 × 10¹⁸-1×10²⁰cm^-3(ii) a The second p-type AlGaAs layer and the n-type doped Al of the middle cell_xGa_1-xThe As window layers are connected, wherein x is more than or equal to 0.3 and less than or equal to 0.5; the second n-type GaInP layer is connected with the p-type doped AlGaInP back field layer of the top cell.

9. A method for fabricating a GaInP/GaAs/HIT triple junction tandem solar cell according to any one of claims 1 to 8, comprising the steps of:

s10, growing and preparing the GaInP/GaAs double-junction battery by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy technology;

sequentially epitaxially growing a GaAs buffer layer, an AlAs sacrificial layer, a GaInP corrosion stop layer, a GaInP top battery, a second tunneling junction, a middle battery and a first tunneling junction on the surface of the GaAs substrate to form a GaInP/GaAs double-junction sub-battery; an n-type doped GaAs cap layer is further arranged between the GaInP corrosion stop layer and the GaInP top battery;

s20, preparing the HIT sub-battery through chemical vapor deposition or physical vapor deposition;

s30, bonding the GaInP/GaAs double-junction sub-cell with an HIT sub-cell to generate a GaInP/GaAs/HIT cell;

and S40, stripping the substrate of the GaInP/GaAs double-junction sub-cell in the GaInP/GaAs/HIT cell to form the three-junction laminated solar cell.

10. The method of claim 9, wherein the GaInP/GaAs/HIT triple-junction tandem solar cell is specifically generated as follows at S10:

selecting an n-type doped GaAs substrate, wherein the thickness of the GaAs substrate is 300-600 um, and the doping concentration of the GaAs substrate is 1 × 10¹⁷-1×10¹⁸cm^-3The method comprises the steps of placing an n-type doped GaAs substrate in an MOCVD (metal organic chemical vapor deposition) operation chamber, and sequentially and reversely growing a GaAs buffer layer, an AlAs sacrificial layer, a GaInP corrosion stop layer, an n-type doped GaAs cap layer, a GaInP top battery, a second tunneling junction, a GaAs middle battery, a tunneling layer and a bonding layer on the surface of the GaAs substrate, wherein the epitaxial reverse growth temperature is set to be 500-800 ℃, the GaAs buffer layer is a nucleating layer used for growing a GaAs base material and has a thickness of 0.1-0.3 um, the AlAs sacrificial layer is an etched layer used for realizing stripping of the epitaxial growth substrate and has a thickness of 0.1-0.3 um, the GaInP corrosion stop layer is a corrosion control layer used for stripping of the epitaxial growth substrate and has a thickness of 0.1-0.3 um, and the n-type doped GaAs cap layer is a heavy doping layer used for forming ohmic contact with a metal electrode and has a thickness of 100-500 nm and a doping concentration of 1 × 10¹⁸-1×10¹⁹cm^-3(ii) a The thickness of the bonding layer is 50nm to 100 nm;

the S20 includes the steps of:

s210, after cleaning the surface of a p-type Si substrate, depositing deposition layers with the thickness of 1nm-10nm on two sides of the p-type Si substrate respectively by adopting a chemical vapor deposition process to form a first intrinsic amorphous silicon passivation layer and a second intrinsic amorphous silicon passivation layer;

s220, depositing an n-type amorphous silicon emission layer with the thickness of 10nm-100nm on the surface of the first intrinsic amorphous silicon passivation layer by adopting a chemical vapor deposition process;

s230, depositing a p-type amorphous silicon BSF layer with the thickness of 5nm-20nm on the surface of the second intrinsic amorphous silicon passivation layer by adopting a chemical vapor deposition process;

s240, depositing a TCO layer with the thickness of 50nm-150nm on the surface of the p-type amorphous silicon BSF layer by adopting a physical vapor deposition process or a magnetron sputtering process;

the S30 includes the steps of:

s310, polishing the surfaces of the GaInP/GaAs double-junction sub-cell and the HIT sub-cell;

carrying out surface treatment on the bonding layer of the GaInP/GaAs double-junction sub-battery and the n-type amorphous silicon emitting layer of the HIT sub-battery through a chemical mechanical polishing process, so that the surface roughness of the bonding layer and the n-type amorphous silicon emitting layer is reduced to be within 1 nm;

s320, activating the surfaces of the polished GaInP/GaAs double-junction sub-battery and the polished HIT sub-battery, and attaching;

cleaning the polished bonding layer and the surface of the n-type amorphous silicon emitting layer, performing surface activation treatment by using plasma, and then attaching the bonding layer and the n-type amorphous silicon emitting layer together, so that the GaInP/GaAs double-junction battery and the HIT sub-battery are attached together by Van der Waals force;

s330, bonding the attached GaInP/GaAs double-junction sub-battery and HIT sub-battery at low temperature;

placing the bonded GaInP/GaAs double-junction sub-battery and HIT sub-battery into a bonding cavity of a bonding machine, wherein the bonding cavity is filled with N₂Heating the bonding cavity to 80-120 ℃, preheating the bonded GaInP/GaAs double-junction sub-battery and HIT sub-battery for 60-120 seconds, applying bonding pressure of 1-5 KN to the bonded GaInP/GaAs double-junction sub-battery and HIT sub-battery, heating the temperature in the bonding cavity to 150-250 ℃ at a heating rate of 15 ℃/min, and heating to the temperature of the bonding cavity to the temperature of 150-250 ℃ at a heating rate of 15 ℃/minKeeping the constant temperature, bonding for 1-2 hours, and finally cooling the temperature in the bonding cavity to room temperature at a cooling speed of 3 ℃/min to realize low-temperature bonding;

the S40 includes the steps of:

s410, corroding the AlAs sacrificial layer by using corrosive liquid;

s420, stripping the GaAs substrate and the GaAs buffer layer;

after the AlAs sacrificial layer is corroded, the GaAs substrate and the GaAs buffer layer can be stripped from the GaInP/GaAs/HIT cell, the stripped GaAs substrate can be reused, and the preparation cost of the three-laminated solar cell is reduced;

s430, etching and stripping the GaInP etching stop layer;

with HC 1: h₂O is 1: 1, corroding the GaInP corrosion stop layer by using the corrosive liquid, stripping the GaInP corrosion stop layer from the GaInP/GaAs/HIT battery to complete substrate stripping, and finally ultrasonically cleaning the stripped battery by using deionized water to obtain the required three-laminated-layer solar battery.

Technical Field

The invention relates to the technical field of photovoltaic power generation, in particular to a GaInP/GaAs/HIT triple-junction laminated solar cell and a preparation method thereof.

Background

Solar photovoltaic power generation has been developed in great quantities worldwide. Commonly used solar cells generally include crystalline silicon solar cells, thin film solar cells, gallium arsenide (GaAs) solar cells, and the like. The forward lattice matching three-junction laminated gallium arsenide solar cell has been widely applied to space power systems due to high photoelectric conversion efficiency and good radiation resistance. The conversion efficiency of the forward lattice matching three-junction laminated gallium arsenide solar cell under the AM 0 spectrum is close to 30.0%.

The forward lattice mismatched triple-junction tandem solar cell of the traditional technology is mainly a GaInP/GaAs/Ge triple-junction tandem solar cell. However, the forward lattice matching three-junction gallium arsenide three-junction stacked cell in the conventional technology has the problem of high cost.

Disclosure of Invention

The invention aims to overcome the defects in the prior art and provides a GaInP/GaAs/HIT triple-junction laminated solar cell with high electrical conversion efficiency, good stability and low cost and a preparation method thereof.

In order to achieve the purpose, the technical scheme provided by the invention is as follows: a GaInP/GaAs/HIT three-junction laminated solar cell comprises a bottom cell, a middle cell and a top cell which are sequentially laminated, wherein the bottom cell and the middle cell are connected through a first tunneling junction, and the middle cell and the top cell are connected through a second tunneling junction; the bottom cell is an HIT solar cell, namely an HIT sub-cell; the middle cell is a GaAs solar cell, the top cell is a GaInP solar cell, and the top cell and the middle cell are formed into a GaInP/GaAs double-junction cell.

Further, the bottom cell comprises a TCO layer, a p-type amorphous silicon BSF layer (p-a-SiBSF layer), a first intrinsic amorphous silicon passivation layer (first i-a-Si passivation layer), a p-type Si substrate, a second intrinsic amorphous silicon passivation layer (second i-a-Si passivation layer) and an n-type amorphous silicon emission layer (n-a-Si emission layer) which are sequentially stacked from bottom to top; the thickness of the TCO layer is 50nm-150 nm; the thickness of the p-type amorphous silicon BSF layer is 5nm-20 nm; the thicknesses of the first intrinsic amorphous silicon passivation layer and the second intrinsic amorphous silicon passivation layer are 1nm-10 nm; the thickness of the n-type amorphous silicon emission layer is 10nm-100 nm.

Further, the middle battery comprises p-type doped Al which is sequentially stacked from bottom to top_xGa_1-xAs back field layer, p-type doped GaAs base region, n-type doped GaAs emitter region and n-type doped Al_xGa_1-xAn As window layer; the p-type doped Al_xGa_1-xThe thickness of the As back field layer is 100nm-200nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3The thickness of the p-type doped GaAs base region is 1000nm-2000nm, and the doping concentration is 1 × 10¹⁶-1×10¹⁷cm^-3The thickness of the n-type doped GaAs emission region is 50nm-200nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3(ii) a The n-type doped Al_xGa_1-xThe thickness of the As window layer is 30nm-100nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3(ii) a Wherein x is more than or equal to 0.3 and less than or equal to 0.5.

Further, the top cell comprises a p-type doped AlGaInP back field layer, a p-type doped GaInP base region, an n-type doped GaInP emitting region and an n-type doped AlInP window layer which are sequentially stacked from bottom to top, wherein the thickness of the p-type doped AlGaInP back field layer is 100nm-200nm, and the doping concentration of the p-type doped AlGaInP back field layer is 1 × 10¹⁷-1×10¹⁹cm^-3The thickness of the p-type doped GaInP base region is 500nm-1000nm, and the doping concentration is 1 × 10¹⁶-1×10¹⁷cm^-3The thickness of the n-type doped GaInP emitting region is 50nm-100nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3The thickness of the n-type doped AlInP window layer is 30nm-100nm, and the doping concentration is 1 × 10¹⁷-1×10¹⁹cm^-3。

Further, the top cell has a forbidden band width of 1.86eV, the middle cell has a forbidden band width of 1.4eV, and the bottom cell has a forbidden band width of 1.1 eV.

Further, the first tunneling junction comprises a tunneling layer and a bonding layer which are stacked, the tunneling layer is connected with the middle battery, and the bonding layer is connected with the middle batteryThe bottom cell is connected, the tunneling layer comprises a first p-type AlGaAs layer and a first n-type GaInP layer which are sequentially stacked from bottom to top, the thickness of the first p-type AlGaAs layer is 10nm-100nm, and the doping concentration of the first p-type AlGaAs layer is 1 × 10¹⁸-1×10²⁰cm^-3The thickness of the first n-type GaInP layer is 10nm-100nm, and the doping concentration is 1 × 10¹⁸-1×10²⁰cm^-3(ii) a The first p-type AlGaAs layer is connected with the bonding layer; the first n-type GaInP layer and the p-type doped Al of the middle cell_xGa_1-xThe As back field layer is connected, wherein x is more than or equal to 0.3 and less than or equal to 0.5.

Further, the bonding layer is an n-type doped GaAs layer, and the doping concentration of the bonding layer is 1 × 10¹⁸-1×10²⁰cm^-3The thickness is 50nm-100 nm.

The second tunneling junction comprises a second p-type AlGaAs layer and a second n-type GaInP layer which are sequentially stacked from bottom to top, the second p-type GaInP layer is connected with the middle cell, the second n-type GaInP layer is connected with the top cell, the thickness of the second p-type AlGaAs layer is 10-100 nm, and the doping concentration of the second p-type AlGaAs layer is 1 × 10¹⁸-1×10²⁰cm^-3The thickness of the second n-type GaInP layer is 10nm-100nm, and the doping concentration is 1 × 10¹⁸-1×10²⁰cm^-3(ii) a The second p-type AlGaAs layer and the n-type doped Al of the middle cell_xGa_1-xThe As window layers are connected, wherein x is more than or equal to 0.3 and less than or equal to 0.5; the second n-type GaInP layer is connected with the p-type doped AlGaInP back field layer of the top cell.

The invention also provides a preparation method of the GaInP/GaAs/HIT triple-junction laminated solar cell, which comprises the following steps:

s10, growing and preparing the GaInP/GaAs double-junction battery by adopting a metal organic chemical vapor deposition technology or a molecular beam epitaxy technology;

sequentially epitaxially growing a GaAs buffer layer, an AlAs sacrificial layer, a GaInP corrosion stop layer, a GaInP top battery, a second tunneling junction, a middle battery and a first tunneling junction on the surface of the GaAs substrate to form a GaInP/GaAs double-junction sub-battery; an n-type doped GaAs cap layer is further arranged between the GaInP corrosion stop layer and the GaInP top battery;

s20, preparing the HIT sub-battery through chemical vapor deposition or physical vapor deposition;

s30, bonding the GaInP/GaAs double-junction sub-cell with an HIT sub-cell to generate a GaInP/GaAs/HIT cell;

and S40, stripping the substrate of the GaInP/GaAs double-junction sub-cell in the GaInP/GaAs/HIT cell to form the three-junction laminated solar cell.

Further, in S10, the GaInP/GaAs double-junction cell is specifically generated as follows:

selecting an n-type doped GaAs substrate, wherein the thickness of the GaAs substrate is 300-600 um, and the doping concentration of the GaAs substrate is 1 × 10¹⁷-1×10¹⁸cm^-3The method comprises the steps of placing an n-type doped GaAs substrate in an MOCVD (metal organic chemical vapor deposition) operation chamber, and sequentially and reversely growing a GaAs buffer layer, an AlAs sacrificial layer, a GaInP corrosion stop layer, an n-type doped GaAs cap layer, a GaInP top battery, a second tunneling junction, a GaAs middle battery, a tunneling layer and a bonding layer on the surface of the GaAs substrate, wherein the epitaxial reverse growth temperature is set to be 500-800 ℃, the GaAs buffer layer is a nucleating layer used for growing a GaAs base material and has a thickness of 0.1-0.3 um, the AlAs sacrificial layer is an etched layer used for realizing stripping of the epitaxial growth substrate and has a thickness of 0.1-0.3 um, the GaInP corrosion stop layer is a corrosion control layer used for stripping of the epitaxial growth substrate and has a thickness of 0.1-0.3 um, and the n-type doped GaAs cap layer is a heavy doping layer used for forming ohmic contact with a metal electrode and has a thickness of 100-500 nm and a doping concentration of 1 × 10¹⁸-1×10¹⁹cm^-3(ii) a The thickness of the bonding layer is 50nm to 100 nm;

the S20 includes the steps of:

s210, after cleaning the surface of a p-type Si substrate, depositing deposition layers with the thickness of 1nm-10nm on two sides of the p-type Si substrate respectively by adopting a chemical vapor deposition process to form a first intrinsic amorphous silicon passivation layer and a second intrinsic amorphous silicon passivation layer;

s220, depositing an n-type amorphous silicon emission layer with the thickness of 10nm-100nm on the surface of the first intrinsic amorphous silicon passivation layer by adopting a chemical vapor deposition process;

s230, depositing a p-type amorphous silicon BSF layer with the thickness of 5nm-20nm on the surface of the second intrinsic amorphous silicon passivation layer by adopting a chemical vapor deposition process;

s240, depositing a TCO layer with the thickness of 50nm-150nm on the surface of the p-type amorphous silicon BSF layer by adopting a physical vapor deposition process or a magnetron sputtering process;

the S30 includes the steps of:

s310, polishing the surfaces of the GaInP/GaAs double-junction sub-cell and the HIT sub-cell;

carrying out surface treatment on the bonding layer of the GaInP/GaAs double-junction sub-battery and the n-type amorphous silicon emitting layer of the HIT sub-battery through a chemical mechanical polishing process, so that the surface roughness of the bonding layer and the n-type amorphous silicon emitting layer is reduced to be within 1 nm;

s320, activating the surfaces of the polished GaInP/GaAs double-junction sub-battery and the polished HIT sub-battery, and attaching;

cleaning the polished bonding layer and the surface of the n-type amorphous silicon emitting layer, performing surface activation treatment by using plasma, and then attaching the bonding layer and the n-type amorphous silicon emitting layer together, so that the GaInP/GaAs double-junction battery and the HIT sub-battery are attached together by Van der Waals force;

s330, bonding the attached GaInP/GaAs double-junction sub-battery and HIT sub-battery at low temperature;

placing the bonded GaInP/GaAs double-junction sub-battery and HIT sub-battery into a bonding cavity of a bonding machine, wherein the bonding cavity is filled with N₂Heating the bonding cavity to 80-120 ℃, preheating the bonded GaInP/GaAs double-junction sub-battery and HIT sub-battery for 60-120 seconds, applying bonding pressure of 1-5 KN to the bonded GaInP/GaAs double-junction sub-battery and HIT sub-battery, heating the temperature in the bonding cavity to 150-250 ℃ at a heating rate of 15 ℃/min, keeping the temperature constant, bonding for 1-2 hours, and finally cooling the temperature in the bonding cavity to room temperature at a cooling rate of 3 ℃/min to realize low-temperature bonding;

the S40 includes the steps of:

s410, corroding the AlAs sacrificial layer by using corrosive liquid;

s420, stripping the GaAs substrate and the GaAs buffer layer;

after the AlAs sacrificial layer is corroded, the GaAs substrate and the GaAs buffer layer can be stripped from the GaInP/GaAs/HIT cell, the stripped GaAs substrate can be reused, and the preparation cost of the three-laminated solar cell is reduced;

s430, etching and stripping the GaInP etching stop layer;

with HC 1: h₂O is 1: 1, corroding the GaInP corrosion stop layer by using the corrosive liquid, stripping the GaInP corrosion stop layer from the GaInP/GaAs/HIT battery to complete substrate stripping, and finally ultrasonically cleaning the stripped battery by using deionized water to obtain the required three-laminated-layer solar battery.

Compared with the prior art, the invention has the following advantages and beneficial effects:

compared with the three-junction laminated solar cell taking Ge as a bottom cell in the prior art, the three-junction laminated solar cell takes the HIT solar cell as the bottom cell, and the HIT solar cell has high photoelectric conversion efficiency, good stability, simple preparation process and low cost. Therefore, the three-junction laminated solar cell provided by the invention has the advantages of high electric conversion efficiency, good stability and low cost. In addition, the substrate of the GaInP/GaAs double-junction battery stripped during preparation can be recycled, and the preparation cost of the battery is obviously reduced.

Drawings

Fig. 1 is a schematic structural diagram of a triple-junction tandem solar cell according to an embodiment.

Fig. 2 is a schematic structural diagram of a bottom cell according to an embodiment.

Fig. 3 is a schematic structural diagram of an intermediate battery according to an embodiment.

Fig. 4 is a schematic structural diagram of a top battery according to an embodiment.

Fig. 5 is a second schematic view of a triple-junction tandem solar cell according to an embodiment.

Fig. 6 is a schematic view of a tunneling layer structure according to an embodiment.

Fig. 7 is a schematic structural diagram of a second tunneling junction according to an embodiment.

Fig. 8 is a schematic flow chart of a method for manufacturing a triple-junction tandem solar cell according to an embodiment.

Fig. 9 is a schematic structural diagram of a GaInP/GaAs double-junction sub-cell according to an embodiment.

Fig. 10 is a schematic flow chart of a method for bonding a GaInP/GaAs double-junction sub-cell and a HIT sub-cell according to an embodiment.

Fig. 11 is a schematic flow chart of a method for stripping a substrate of a GaInP/GaAs double-junction cell according to an embodiment.

Fig. 12 is a third schematic structural view of a triple-tandem solar cell according to the embodiment.

Detailed Description

The present invention will be further described with reference to the following specific examples.

Referring to fig. 1, the present embodiment provides a triple-junction tandem solar cell including a bottom cell 100, a middle cell 200, and a top cell 300, which are sequentially stacked. The bottom cell 100 and the middle cell 200 are connected by a first tunnel junction 400. The middle cell 200 and the top cell 300 are connected by a second tunneling junction 500. Wherein the bottom cell 100 is a HIT (copper indium gallium selenide) solar cell.

The middle cell 200, the top cell 300, and the second tunneling junction 500 may be sequentially fabricated by epitaxial reverse growth. The bottom cell 100 is a silicon solar cell having an HIT structure. The bottom cell 100 is a hybrid solar cell made of a crystalline silicon substrate and an amorphous silicon thin film. The bottom cell 100 may be fabricated by Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) processes, or by other methods. The present embodiment does not limit the manufacturing method and operation of the bottom cell 100, and may be selected according to actual requirements. The bottom cell 100 and the middle cell 200 are connected by a first tunnel junction 400. The bottom cell 100 and the middle cell 200 may be connected by bonding or the like.

Referring to fig. 2, the bottom cell 100 includes a TCO layer 110, a p-type amorphous silicon BSF layer 120 (i.e., a p-a-SiBSF layer), a first intrinsic amorphous silicon passivation layer 130 (i.e., a first i-a-Si passivation layer), a p-type Si substrate 140, a second intrinsic amorphous silicon passivation layer 150 (i.e., a second i-a-Si passivation layer), and an n-type amorphous silicon emitter layer 160 (i.e., an n-a-Si emitter layer) stacked in this order from bottom to top. Wherein the thickness of the TCO layer 110 can be 50nm-150 nm. The thickness of the p-type amorphous silicon BSF layer 120 may be 5nm to 20 nm. The first and second intrinsic amorphous silicon passivation layers 130 and 150 may have a thickness of 1nm to 10 nm. The n-type amorphous silicon emission layer 150 may have a thickness of 10nm to 100 nm.

The top cell 300 may have a forbidden band width of about 1.86 eV. The intermediate cell 200 may have a forbidden band width of about 1.4 eV. The bottom cell 100 may have a forbidden band width of about 1.1 eV. The top cell 300, the middle cell 200 and the bottom cell 100 can realize the basic matching of the band gap and the AM 0 solar spectrum through the combination of the band gaps, and the photoelectric conversion efficiency is consistent with that of an inverted lattice mismatch (IMM) triple-junction gallium arsenide cell. The triple-junction tandem solar cell provided by the embodiment can realize 32% (AM1.5) of photoelectric conversion efficiency. The three-junction laminated solar cell based on the ultra-thin (<100 mu m) HIT bottom cell can be applied to the fields of unmanned aerial vehicles, stratospheric airships, electric vehicles and the like, and has wide application prospect.

Compared with a three-junction laminated gallium arsenide solar cell taking Ge as a bottom cell in the traditional technology, the photocurrent density of the forward lattice matching three-junction gallium arsenide solar cell in the traditional technology is generally limited by a top cell, and the redundant photocurrent density on the Ge bottom cell cannot be effectively utilized, so that the full-spectrum absorption utilization cannot be realized; and the cost of the forward lattice matching three-junction gallium arsenide solar cell in the traditional technology is higher, wherein the Ge substrate accounts for 30% -50% of the cost. The three-junction tandem solar cell provided by the embodiment uses the HIT solar cell as a bottom cell. The HIT solar cell has the advantages that the photocurrent density can be effectively utilized, the photoelectric conversion efficiency is high, and the stability is good, so that the three-junction tandem solar cell has the advantages of high electric conversion efficiency and good stability. Meanwhile, the HIT solar cell is simple in preparation process and low in cost. Therefore, the triple-junction tandem solar cell provided by the embodiment has the advantage of low cost.

Referring to fig. 3, the intermediate cell 200 is a GaAs solar cell. The middle cell 200 is made of GaAs semiconductor material. The GaAs solar cell packComprises p-type doped Al which is sequentially stacked from bottom to top_xGa_1-xAs back field layer 210, p-type doped GaAs base region 220, n-type doped GaAs emitter region 230 and n-type doped Al_xGa_1-xAn As window layer 240.

Wherein the p-type is doped with Al_xGa_1-xThe thickness of the As back field layer 210 may be 100nm-200 nm; the thickness of the p-type doped GaAs base region 220 can be 1000nm-2000 nm; the thickness of the n-type doped GaAs emitter region 230 may be 50nm to 200 nm; the n-type doped Al_xGa_1-xThe thickness of the As window layer 240 may be 30nm to 100 nm.

The p-type doped Al_xGa_1-xThe doping concentration of the As back field layer 210 may be 1 × 10¹⁷-1×10¹⁹cm^-3The doping concentration of the p-type doped GaAs base region can be 1 × 10¹⁶-1×10¹⁷cm^-3The doping concentration of the n-type doped GaAs emission region can be 1 × 10¹⁷-1×10¹⁹cm^-3(ii) a The n-type doped Al_xGa_1-xThe doping concentration of the As window layer 240 may be 1 × 10¹⁷-1×10¹⁹cm^-3. Wherein x is more than or equal to 0.3 and less than or equal to 0.5.

Referring to fig. 4, the top cell 300 is a GaInP solar cell. The top cell 300 is made of GaInP semiconductor material. The top cell 300 comprises a p-type doped AlGaInP back field layer 310, a p-type doped GaInP base region 320, an n-type doped GaInP emitter region 330 and an n-type doped AlInP window layer 340 which are sequentially stacked from bottom to top.

Wherein the thickness of the p-type doped AlGaInP back field layer 310 may be 100nm to 200 nm; the thickness of the p-type doped GaInP base region 320 may be 500nm to 1000 nm; the thickness of the n-type doped GaInP emitter region 330 may be 50nm to 100 nm; the n-type doped AlInP window layer 340 may have a thickness of 30nm to 100 nm.

The doping concentration of the p-type doped AlGaInP back field layer 310 may be 1 × 10¹⁷-1×10¹⁹cm^-3The doping concentration of the p-type doped GaInP base region 320 can be 1 × 10¹⁶-1×10¹⁷cm^-3(ii) a Doping concentration of the n-type doped GaInP emitter 330May be 1 × 10¹⁷-1×10¹⁹cm^-3The n-type doped AlInP window layer 340 may have a doping concentration of 1 × 10¹⁷-1×10¹⁹cm^-3。

Referring to fig. 5, the first tunneling junction 400 includes a tunneling layer 410 and a bonding layer 420 stacked in a stacked manner. The tunneling layer 410 is connected to the intermediate cell 200. The bonding layer 420 is connected to the bottom cell 100. The thickness of the first tunnel junction 400 is increased by the bonding layer 420 to facilitate bonding of the first tunnel junction 400 to the bottom cell 100.

The tunneling layer 410 and the bonding layer 420 may be prepared by reverse extension growth. The tunneling layer 410 is used to realize the connection between the intermediate cell 200 and the bonding layer 420. The bonding layer 420 is used to realize the connection between the tunneling layer 410 and the bottom cell 100. The bonding layer 420 may have a thickness of 50nm to 100 nm.

Referring to fig. 6, the tunneling layer 410 includes a first p-type AlGaAs layer 411 and a first n-type GaInP layer 412 stacked in this order from bottom to top. The first n-type GaInP layer 412 is connected to a bonding layer 420.

The thickness of the first p-type AlGaAs layer 411 may be 10nm to 100nm and the doping concentration of the first p-type AlGaAs layer 411 may be 1 × 10¹⁸-1×1020cm^-3The thickness of the first n-type GaInP layer 412 may be 10nm-100nm the doping concentration of the first n-type GaInP layer 412 may be 1 × 10¹⁸-1×10²⁰cm^-3. The first p-type AlGaAs layer 411 is connected to a bonding layer 420. The first n-type GaInP layer 412 and the p-type doped Al of the middle cell 200_xGa_1-xThe As back field layer 210 is connected.

Bonding layer 420 is made of GaAs material, bonding layer 420 may have a thickness of 50nm to 100nm, bonding layer 420 may be an n-type doped GaAs layer, and the doping concentration of the n-type doped GaAs layer may be 1 × 10¹⁸-1×10²⁰cm^-3. In the present embodiment, the bonding layer 420 is made of GaAs material, which is more favorable for bonding the bottom cell 100 and for bonding and connecting with the tunneling layer 410.

Referring to fig. 7, the second tunnel junction 500 includes a second p-type AlGaAs layer 510 and a second n-type GaInP layer 520 stacked in this order from bottom to top. The second p-type GaInP layer 510 is connected to the intermediate cell 200. The second n-type GaInP layer 520 is connected to the top cell 300.

The thickness of the second p-type AlGaAs layer 510 may be 10nm to 100nm and the doping concentration of the second p-type AlGaAs layer 510 may be 1 × 10¹⁸-1×10²⁰cm^-3The thickness of the second n-type GaInP layer 520 may be 10nm to 100nm the doping concentration of the second n-type GaInP layer 520 may be 1 × 10¹⁸-1×10²⁰cm^-3. The second p-type AlGaAs layer 510 and the n-type doped Al of the middle cell 200_xGa_1-xThe As window layer 240 is connected. The second n-type GaInP layer 520 is connected to the p-type doped AlGaInP back field layer 310 of the top cell 300.

Referring to fig. 8, the present embodiment provides a method for manufacturing a triple-junction tandem solar cell, including:

and S10, epitaxially growing to prepare the GaInP/GaAs double-junction sub-cell 11.

The GaInP/GaAs double-junction cell 11 may be formed by growing using a Metal Organic Chemical Vapor Deposition (MOCVD) technique or a Molecular Beam Epitaxy (MBE) technique. The GaInP/GaAs double junction subcell 11 includes a GaInP subcell and a GaAs subcell. The GaInP subcell and GaAs subcell are connected by the second tunnel junction 500. Specifically, the GaInP sub-cell includes a p-type doped AlGaInP back-field layer 310, a p-type doped GaInP base region 320, an n-type doped GaInP emitter region 330, and an n-type doped AlInP window layer 340, which are stacked in sequence from bottom to top. The GaAs sub-battery comprises p-type doped Al which is sequentially stacked from bottom to top_xGa_1-xAs back field layer 210, p-type doped GaAs base region 220, n-type doped GaAs emitter region 230 and n-type doped Al_xGa_1-xAn As window layer 240. The GaInP/GaAs double junction sub-cell 11 includes a substrate, which may be a GaAs substrate 111. The specific preparation method and process of the GaInP/GaAs double-junction sub-cell 11 are not limited in this embodiment, as long as the preparation of the GaInP/GaAs double-junction sub-cell 11 can be realized.

S20, preparing the HIT sub-cell 12.

The HIT sub-cell 12 may be fabricated by Chemical Vapor Deposition (CVD) and Physical Vapor Deposition (PVD) processes, or by other methods. The preparation method and the work of the HIT sub-battery 12 are not limited, and can be selected according to actual requirements. The HIT sub-cell 12 includes a TCO layer 110, a p-type amorphous silicon BSF layer 120 (i.e., a p-a-SiBSF layer), a first intrinsic amorphous silicon passivation layer 130 (i.e., a first i-a-Si passivation layer), a p-type Si substrate 140, a second intrinsic amorphous silicon passivation layer 140 (i.e., a second i-a-Si passivation layer), and an n-type amorphous silicon emitter layer 150 (i.e., an n-a-Si emitter layer) stacked in sequence from bottom to top. Wherein the thickness of the TCO layer 110 can be 50nm-150 nm. The thickness of the p-type amorphous silicon BSF layer 120 may be 5nm to 20 nm. The first and second intrinsic amorphous silicon passivation layers 130 and 140 may have a thickness of 1nm to 10 nm. The n-type amorphous silicon emission layer 150 may have a thickness of 10nm to 100 nm.

The method of making the HIT sub-cell 12 includes:

s210, after cleaning the surface of the p-type Si substrate 140, respectively depositing deposition layers with the thickness of about 1nm to 10nm on the two sides of the p-type Si substrate 140 by adopting a CVD (chemical vapor deposition) process to form a first intrinsic amorphous silicon passivation layer 130 and a second intrinsic amorphous silicon passivation layer 140; the CVD process can be PECVD or hotwire CVD.

S220, depositing an n-type amorphous silicon emitting layer 150 with the thickness of 10nm-100nm on the surface of the first intrinsic amorphous silicon passivation layer 130 by adopting a CVD (chemical vapor deposition) process; the CVD process can be PECVD or hotwire CVD.

S230, depositing a p-type amorphous silicon BSF layer 120 with the thickness of 5nm-20nm on the surface of the second intrinsic amorphous silicon passivation layer 150 by adopting a CVD (chemical vapor deposition) process; the CVD process can be PECVD or hotwire CVD.

S240, depositing the TCO layer 110 with the thickness of 50nm-150nm on the surface of the p-type amorphous silicon BSF layer 120 by adopting a PVD process or a magnetron sputtering process.

The HIT sub-cell 12 formed by the method provided by the embodiment has high photoelectric conversion efficiency, simple preparation process, good stability and low cost.

And S30, bonding the GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 to generate the GaInP/GaAs/HIT cell 13.

The GaInP/GaAs double junction subcell 11 generated at S10 and the HIT subcell 12 generated at S20 were bonded. The specific method, step, process, etc. adopted for bonding are not limited in this application, as long as the bonding of the GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 can be realized to generate the GaInP/GaAs/HIT cell 13.

And S40, stripping the substrate of the GaInP/GaAs double-junction sub-cell 11 in the GaInP/GaAs/HIT cell 13 to form the required three-junction laminated solar cell.

Since the bonding-generated GaInP/GaAs/HIT cell 13 includes the substrate of the GaInP/GaAs double-junction sub-cell 11 and also includes the substrate of the HIT sub-cell 12, it is necessary to peel off the substrate of the GaInP/GaAs double-junction sub-cell 11 and leave the substrate of the HIT sub-cell 12. The method and process for stripping the substrate of the GaInP/GaAs double-junction sub-cell 11 are not particularly limited in this embodiment, as long as the substrate of the GaInP/GaAs double-junction sub-cell 11 can be stripped from the GaInP/GaAs/HIT cell 13. And (5) obtaining the required three-junction laminated solar cell after stripping.

And depositing an antireflection layer and an upper electrode on the surface of the obtained triple-junction laminated solar cell to finish the process preparation of the triple-junction laminated solar cell.

In this embodiment, a GaInP/GaAs double-junction sub-cell 11 is prepared by epitaxial growth, a HIT sub-cell 12 is prepared, the GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 are bonded to generate a GaInP/GaAs/HIT cell 13, and then the substrate of the GaInP/GaAs double-junction sub-cell 11 in the GaInP/GaAs/HIT cell 13 is peeled off to form a triple-junction tandem solar cell. First, the method provided in this embodiment bonds the HIT sub-cell 12 and the GaInP/GaAs double-junction sub-cell 11, so that the HIT sub-cell 12 serves as a bottom cell of a triple-junction tandem solar cell. The HIT is simple in preparation process and low in cost. Therefore, the method provided by the embodiment has the advantage of low cost. Secondly, the HIT sub-cell has high photoelectric conversion efficiency and good stability, so that the triple-junction tandem solar cell prepared by the method provided by the embodiment has high electric conversion efficiency and good stability. And thirdly, the substrate of the GaInP/GaAs double-junction sub-cell 11 in the stripped GaInP/GaAs/HIT cell 13 can be recycled, so that the preparation cost of the cell is obviously reduced.

Referring to fig. 9, S10 specifically includes the following steps:

and S110, epitaxially growing a GaAs buffer layer 112, an AlAs sacrificial layer 113, a GaInP corrosion stop layer 114, a GaInP top battery 115, a second tunneling junction 500, a GaAs middle battery 116 and a first tunneling junction 400 on the surface of a GaAs substrate 111 in sequence to form the GaInP/GaAs double-junction sub-battery 11. Wherein, an n-type doped GaAs cap layer 117 is also included between the GaInP etch stop layer 114 and the GaInP top cell 115.

The first tunneling junction 400 includes a tunneling layer 410 and a bonding layer 420. The tunneling layer 410 includes a first p-type AlGaAs layer 411 and a first n-type GaInP layer 412. The bonding layer 420 is made of GaAs material.

The GaInP/GaAs double-junction sub-cell 11 is generated by the following steps:

an n-type doped GaAs substrate 111 is selected as a substrate, the thickness of the GaAs substrate 111 can be 300um-600um, and the doping concentration of the GaAs substrate 111 can be 1 × 10¹⁷-1×10¹⁸cm^-3(preferably 1 × 10)¹⁸cm^-3)。

The n-type doped GaAs substrate 111 is placed in an MOCVD operation chamber, and a GaAs buffer layer 112, an AlAs sacrificial layer 113, a GaInP corrosion stop layer 114, an n-type doped GaAs cap layer 117, a GaInP top cell 115, a second tunneling junction 500, a GaAs middle cell 116, a tunneling layer 410 and a bonding layer 420 are epitaxially and reversely grown on the surface of the GaAs substrate 111 in sequence. The epitaxial reverse growth temperature may be set to 500 ℃ to 800 ℃. The GaAs buffer layer 112 serves as a nucleation layer for growing a GaAs-based material. The GaAs buffer layer 112 can have a thickness of 0.1 um-0.3 um. The AlAs sacrificial layer 113 is an etched layer for realizing lift-off of an epitaxial growth substrate. The thickness of the AlAs sacrificial layer 113 may be 0.1 um-0.3 um. The GaInP etch stop layer 114 is an etch control layer that acts as a lift-off epitaxial growth substrate. The GaInP etch stop layer 114 may have a thickness of 0.1 um-0.3 um. The n-type doped GaAs cap layer 117 is used for forming ohmic contact with the metal electrodeThe thickness of the n-type doped GaAs cap layer 117 may be 100nm to 500nm the doping concentration of the n-type doped GaAs cap layer 117 may be 1 × 10¹⁸-1×10¹⁹cm^-3. The bonding layer 420 may have a thickness of 50nm to 100 nm.

The GaInP top battery 115 comprises a p-type doped AlGaInP back field layer 310, a p-type doped GaInP base region 320, an n-type doped GaInP emitting region 330 and an n-type doped AlInP window layer 340 which are sequentially stacked from bottom to top, wherein the thickness of the p-type doped AlGaInP back field layer 310 can be 100nm-200nm, the thickness of the p-type doped GaInP base region 320 can be 500nm-1000nm, the thickness of the n-type doped GaInP emitting region 330 can be 50nm-100nm, the thickness of the n-type doped AlInP window layer 340 can be 30nm-100nm, the doping concentration of the p-type doped AlGaInP back field layer 310 can be 1 × 10nm¹⁷-1×10¹⁹cm^-3The doping concentration of the p-type doped GaInP base region 320 can be 1 × 10¹⁶-1×10¹⁷cm^-3The doping concentration of the n-type doped GaInP emitter region 330 may be 1 × 10¹⁷-1×10¹⁹cm^-3The n-type doped AlInP window layer 340 may have a doping concentration of 1 × 10¹⁷-1×10¹⁹cm^-3. The gap width of the GaInP top cell 115 is about 1.86 eV.

The GaAs middle cell 116 comprises p-type doped Al which are sequentially stacked from bottom to top_xGa_1-xAs back field layer 210, p-type doped GaAs base region 220, n-type doped GaAs emitter region 230 and n-type doped Al_xGa_1-xAn As window layer 240. Wherein the p-type is doped with Al_xGa_1-xThe thickness of the As back field layer 210 may be 100nm-200 nm; the thickness of the p-type doped GaAs base region 220 can be 1000nm-2000 nm; the thickness of the n-type doped GaAs emitter region 230 may be 50nm to 200 nm; the n-type doped Al_xGa_1-xThe thickness of the As window layer 240 may be 30nm to 100 nm. The p-type doped Al_xGa_1-xThe doping concentration of the As back field layer 210 may be 1 × 10¹⁷-1×10¹⁹cm^-3The doping concentration of the p-type doped GaAs base region can be 1 × 10¹⁶-1×10¹⁷cm^-3The doping concentration of the n-type doped GaAs emission region can be 1 × 10¹⁷-1×10¹⁹cm^-3(ii) a The n-type doped Al_xGa_1-xThe doping concentration of the As window layer 240 may be 1 × 10¹⁷-1×10¹⁹cm^-3. Wherein x is more than or equal to 0.3 and less than or equal to 0.5. The forbidden band width of the cell 116 in GaAs is about 1.4 eV.

In this embodiment, the GaInP/GaAs double-junction sub-cell 11 is formed by epitaxially growing a GaAs buffer layer 112, an AlAs sacrificial layer 113, a GaInP etch stop layer 114, a GaInP top cell 115, a second tunnel junction 500, a GaAs middle cell 116, and a first tunnel junction 400 on the surface of a GaAs substrate 111 in sequence, and the growth process is simple. And the generated GaInP/GaAs double-junction sub-cell 11 and HIT sub-cell 12 are bonded to form a three-junction laminated solar cell which is stable in structure and high in photoelectric conversion efficiency.

Referring to fig. 10, S30 specifically includes the following steps:

and S310, polishing the surfaces of the GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12.

The bonding layer 420 of the GaInP/GaAs double-junction sub-cell 11 and the n-type amorphous silicon emission layer 150 of the HIT sub-cell 12 are surface-treated by a Chemical Mechanical Polishing (CMP) process such that the surface roughness of the bonding layer 420 and the n-type amorphous silicon emission layer 150 is reduced to within 1 nm.

And S320, performing activation treatment on the surfaces of the polished GaInP/GaAs double-junction sub-cell 11 and the polished HIT sub-cell 12, and attaching the surfaces.

The polished surfaces of the bonding layer 420 and the n-type amorphous silicon emitter layer 150 are cleaned and subjected to surface activation treatment by plasma. And then the bonding layer 420 and the n-type amorphous silicon emitting layer 150 are attached, so that the GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 are attached together through van der waals force.

And S330, bonding the attached GaInP/GaAs double-junction sub-cell 11 and HIT sub-cell 12 at low temperature.

And placing the attached GaInP/GaAs double-junction sub-battery 11 and HIT sub-battery 12 into a bonding cavity of a bonding machine. The bonding cavity is filled with N₂. The temperature of the bonding cavity is raised to 80-120 ℃, and the bonding cavity is bondedThe GaInP/GaAs double junction subcell 11 and the HIT subcell 12 were preheated for 60-120 seconds. And then applying bonding pressure of 1 KN-5 KN to the attached GaInP/GaAs double-junction sub-battery 11 and the HIT sub-battery 12, and raising the temperature in the bonding cavity to 150-250 ℃ at a temperature rise speed of 15 ℃/min. Then, the temperature is kept constant, and bonding is performed for 1 hour to 2 hours. And finally, reducing the temperature in the bonding cavity to room temperature at a cooling speed of 3 ℃/min to realize low-temperature bonding.

In this embodiment, the surfaces of the GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 are polished, then the surfaces of the polished GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 are activated and bonded, and then the bonded GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 are bonded at a low temperature. The bonding of the GaInP/GaAs double-junction sub-cell 11 and the HIT sub-cell 12 is realized by the method provided by the embodiment, the bonding method is simple and easy to operate, the bonding result is stable, and the stability of the triple-junction tandem solar cell is improved.

Referring to fig. 11 and 12, S40 specifically includes the following steps:

s410, the AlAs sacrificial layer 113 is etched using an etchant.

And S420, stripping the GaAs substrate 111 and the GaAs buffer layer 112.

After the AlAs sacrificial layer 113 is etched, the GaAs substrate 111 and the GaAs buffer layer 112 can be peeled off from the GaInP/GaAs/HIT cell 13. The stripped GaAs substrate 111 can be reused, and the preparation cost of the three-junction laminated solar cell is reduced.

S430, the GaInP etch stop layer 114 is etched away.

With HC 1: h₂O is 1: the etching solution of 1 etches the GaInP etch stop layer 114, and the GaInP etch stop layer 114 is stripped from the GaInP/GaAs/HIT cell 13, thereby completing the substrate stripping. Finally, the peeled cell was ultrasonically cleaned with deionized water to obtain a triple-junction tandem solar cell as shown in fig. 12.

In this embodiment, the GaAs etching stopper 114 is etched and stripped by etching the AlAs sacrificial layer 113, the GaAs substrate 111, and the GaAs buffer layer 112. The method provided by the embodiment is simple to operate, and the stripped GaAs substrate 111 can be recycled, so that the preparation cost can be reduced.

The above-mentioned embodiments are merely preferred embodiments of the present invention, and the scope of the present invention is not limited thereto, so that the changes in the shape and principle of the present invention should be covered within the protection scope of the present invention.