阅读说明：本技术 基板及电泳装置 (Substrate and electrophoresis apparatus ) 是由 林宏宜 小川耀博 于 2018-12-19 设计创作，主要内容包括：提供能够提高显示性能的基板及电泳装置。具备绝缘性的基材、设在基材的一面侧的像素电极、以及设在基材与像素电极之间的共通电极。在平面视图中,共通电极的外周的边全部位于像素电极的内侧。(Provided are a substrate and an electrophoretic device capable of improving display performance. The liquid crystal display device includes an insulating substrate, a pixel electrode provided on one surface of the substrate, and a common electrode provided between the substrate and the pixel electrode. In a plan view, the sides of the outer periphery of the common electrode are all located inside the pixel electrode.)

1. A substrate, characterized in that,

the disclosed device is provided with:

an insulating base material;

a pixel electrode provided on one surface side of the substrate; and

a common electrode provided between the substrate and the pixel electrode;

in a plan view, all the outer peripheral sides of the common electrode are located inside the pixel electrode.

2. The substrate of claim 1,

a connection portion provided between the substrate and the pixel electrode;

a plurality of pixel electrodes arranged in a 1 st direction and a 2 nd direction intersecting the 1 st direction in a plan view;

a plurality of the common electrodes are arranged in the 1 st direction and the 2 nd direction;

the connection portion connects the common electrodes arranged in at least one of the 1 st direction and the 2 nd direction.

3. The substrate of claim 2,

a gate line extending in the 1 st direction between the substrate and the pixel electrode;

the connecting portion has a wiring provided in the same layer as the gate line.

4. The substrate of claim 2,

a signal line extending in a 2 nd direction between the substrate and the pixel electrode;

the connection portion has a wiring provided in the same layer as the signal line.

5. The substrate of claim 2,

the connection portion is provided on a surface of the common electrode facing the pixel electrode.

6. The substrate of claim 2,

the connecting portion is provided in the same layer as the common electrode and is made of a material having the same composition as the common electrode.

7. An electrophoresis device, characterized in that,

the disclosed device is provided with:

a substrate; and

an electrophoretic layer disposed to face the substrate;

the substrate includes:

an insulating base material;

a plurality of pixel electrodes provided on a surface of the substrate facing the electrophoretic layer and arranged in a matrix; and

a plurality of common electrodes provided between the substrate and the pixel electrodes and arranged in a matrix;

in a plan view, the plurality of pixel electrodes and the plurality of common electrodes are opposed to each other 1 to 1, and all the outer peripheral sides of the common electrodes are located inside the pixel electrodes.

8. The electrophoretic device according to claim 7,

the common electrodes adjacent to each other among the plurality of common electrodes are separated from each other.

9. The electrophoretic device according to claim 8,

a gate line extending in a 1 st direction between the substrate and the pixel electrode;

a plurality of common electrodes arranged in the 1 st direction, each of which is connected to each other by a connection portion;

the connecting part is parallel to the gate line and extends along the 1 st direction;

the connecting portion is a wiring provided in the same layer as the gate line.

10. The electrophoretic device according to claim 8,

a signal line extending in a 2 nd direction between the substrate and the pixel electrode;

a plurality of common electrodes arranged in the 2 nd direction, each of which is connected to each other by a connection portion;

the connecting portion extends in the 2 nd direction parallel to the signal line;

the connection portion is a wiring provided in the same layer as the signal line.

11. The electrophoretic device according to claim 9 or 10,

an organic film between the base material and the common electrode;

the common electrode and the connection portion are connected via a contact hole formed in the organic film;

the contact hole is opposed to the pixel electrode.

12. The electrophoretic device according to claim 11,

the common electrode includes a light-transmitting conductive film and a reflective film in contact with the light-transmitting conductive film;

in the contact hole, the connecting portion is in contact with the transparent conductive film.

Technical Field

The present invention relates to a substrate and an electrophoresis apparatus.

Background

In recent years, there has been an increasing demand for display devices for mobile electronic devices such as mobile phones and electronic paper. For example, an Electrophoretic Display (EPD) used for electronic paper has a memory property of holding a potential at the time of rewriting an image. If the EPD is rewritten 1 time per frame, the potential at the time of rewriting is held until rewriting is performed in the next frame. Thus, EPD enables low power consumption driving. Also, EPD discloses a structure in which the 1 st storage capacitor overlaps with the pixel switching element (for example, patent document 1).

Disclosure of Invention

Problems to be solved by the invention

With respect to EPDs, improvement in display performance is desired.

The present invention has been made in view of the above, and an object of the present invention is to provide a substrate and an electrophoretic device capable of improving display performance.

Means for solving the problems

A substrate according to one embodiment includes: an insulating base material; a pixel electrode provided on one surface side of the substrate; and a common electrode provided between the substrate and the pixel electrode; in a plan view, all the outer peripheral sides of the common electrode are located inside the pixel electrode.

An electrophoresis device according to one aspect includes: a substrate; and an electrophoretic layer disposed to face the substrate; the substrate includes: an insulating base material; a pixel electrode provided on a surface of the substrate facing the electrophoretic layer; and a common electrode provided between the substrate and the pixel electrode; in a plan view, all the sides of the outer periphery of the common electrode are located inside the pixel electrode.

Drawings

Fig. 1 is a block diagram showing a configuration example of a display device according to embodiment 1.

Fig. 2 is a circuit diagram showing a configuration example of 1 pixel with respect to the TFT substrate of embodiment 1.

Fig. 3 is a plan view showing an example of arrangement of a plurality of pixels with respect to the TFT substrate of embodiment 1.

Fig. 4 is a cross-sectional view showing a positional relationship between a common electrode and a pixel electrode with respect to the TFT substrate of embodiment 1.

Fig. 5 is a plan view showing a configuration example of the TFT substrate according to embodiment 1.

Fig. 6 is a sectional view showing a structural example of the coupling portion according to embodiment 1.

Fig. 7 is a sectional view showing another configuration example (1) of the coupling portion according to embodiment 1.

Fig. 8 is a sectional view showing another configuration example (2) of the coupling portion according to embodiment 1.

Fig. 9 is a plan view showing an enlarged region including a pixel transistor in the TFT substrate of embodiment 1.

FIG. 10 is a cross-sectional view of the plan view of FIG. 9 taken along line X-X'.

Fig. 11 is a sectional view for explaining a method of manufacturing a TFT substrate.

Fig. 12 is a sectional view for explaining a method of manufacturing a TFT substrate.

Fig. 13 is a sectional view for explaining a method of manufacturing the TFT substrate.

Fig. 14 is a sectional view for explaining a method of manufacturing a TFT substrate.

Fig. 15 is a sectional view showing a configuration example of a display device according to embodiment 1.

Fig. 16 is a graph showing the results of examining the relationship between the distance between the outer periphery of the pixel electrode and the outer periphery of the common electrode and the electric field intensity for 1 pixel.

Fig. 17 is a plan view showing a structural example of a TFT substrate of a comparative example.

FIG. 18 is a sectional view of the plan view of FIG. 17 cut along line XVIII-XVIII'.

Fig. 19 is a cross-sectional view showing a configuration example of a TFT substrate according to modification 1 of embodiment 1.

Fig. 20 is a cross-sectional view showing a configuration example of a TFT substrate according to modification 2 of embodiment 1.

Fig. 21 is a cross-sectional view showing a configuration example of a TFT substrate according to modification 2 of embodiment 1.

Fig. 22 is a plan view showing a configuration example of a TFT substrate according to embodiment 2.

Fig. 23 is a sectional view showing a structural example of the coupling portion according to embodiment 2.

Fig. 24 is a circuit diagram showing a configuration example of 1 pixel with respect to the TFT substrate of the modification of embodiment 2.

Fig. 25 is a plan view showing a configuration example of a TFT substrate according to a modification of embodiment 2.

Fig. 26 is a plan view showing a configuration example of a TFT substrate according to embodiment 3.

Fig. 27 is a plan view showing a configuration example of a TFT substrate according to embodiment 4.

Fig. 28 is a plan view showing a configuration example of a TFT substrate according to embodiment 5.

Fig. 29 is a plan view showing a configuration example of a TFT substrate according to a modification of embodiment 5.

Fig. 30 is a plan view showing a configuration example of a TFT substrate according to embodiment 6.

Fig. 31 is a plan view showing a configuration example of the common electrode according to embodiment 6.

Fig. 32 is a plan view showing a conductive film non-formation region of the common electrode in embodiment 6.

Fig. 33 is a plan view showing a conductive film non-formation region of the common electrode in modification 1 of embodiment 6.

Fig. 34 is a plan view showing a conductive film non-formation region of the common electrode in modification 2 of embodiment 6.

Fig. 35 is a plan view showing a conductive film non-formation region of the common electrode in modification 3 of embodiment 6.

Fig. 36 is a plan view showing a conductive film non-formation region of the common electrode in modification 4 of embodiment 6.

Fig. 37 is a plan view showing a conductive film non-formation region of the common electrode in modification 5 of embodiment 6.

Fig. 38 is a plan view showing a conductive film non-formation region of the common electrode in modification 6 of embodiment 6.

Detailed Description

The mode (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. The constituent elements described below include substantially the same elements as can be easily conceived by those skilled in the art. Further, the following constituent elements may be appropriately combined. The disclosure is merely an example, and it is needless to say that the present invention includes the embodiments which can be easily conceived by those skilled in the art without departing from the gist of the present invention. In addition, although the drawings schematically show the width, thickness, shape, and the like of each part as compared with the actual form in order to clarify the description, the drawings are merely examples and do not limit the explanation of the present invention. In the present specification and the drawings, the same elements as those described in the previous drawings are denoted by the same reference numerals, and detailed description thereof may be omitted as appropriate. In this specification, the left-right direction in fig. 3 is represented by the X direction, the up-down direction in fig. 3 is represented by the Y direction, and the direction perpendicular to the X-Y plane in fig. 3 is represented by the Z direction. The X direction and the Y direction are also referred to as horizontal directions.

(embodiment mode 1)

Fig. 1 is a block diagram showing a configuration example of a display device according to embodiment 1. Fig. 2 is a circuit diagram showing a configuration example of 1 pixel with respect to the TFT substrate of embodiment 1. The display device 200 according to embodiment 1 is mounted on an electronic apparatus not shown, for example. The display device 200 is applied with a power supply voltage from a power supply circuit of the electronic apparatus, and performs image display based on a signal output from a control circuit that is a main processor of the electronic apparatus. The display device 200 is an electrophoretic display (EPD) having, for example, an electrophoretic layer 160 (see fig. 15 described later). As shown in fig. 1, the display device 200 includes a TFT substrate 100, a gate driver 110 connected to the TFT substrate 100, and a source driver 120 connected to the TFT substrate 100. Electrophoretic displays (EPDs are also referred to as electrophoretic devices.

As shown in fig. 1, the TFT substrate 100 includes a plurality of pixels PX, a plurality of gate lines GCL (n), GCL (n +1), GCL (n +2) …, and a plurality of signal lines SGL (m), SGL (m +1), SGL (m +2) …. n and m are each an integer of 1 or more. In the following description, when it is not necessary to distinguish the plurality of gate lines GCL (n), (n +1), and GCL (n +2) … from each other, they will be referred to as gate lines GCL, respectively. When it is not necessary to describe the plurality of signal lines SGL (m), SGL (m +1), and SGL (m +2) … separately from each other, they are referred to as signal lines SGL.

The plurality of pixels PX are arranged in a two-dimensional matrix in the X direction and the Y direction intersecting the X direction, respectively. The plurality of gate lines GCL extend in the X direction and are arranged in the Y direction. The plurality of signal lines SGL extend in the Y direction and are arranged in the X direction. Thus, the plurality of signal lines SGL and the plurality of gate lines GCL are orthogonal to each other in a plan view. The plan view is a view seen from a normal line direction of one surface 1a (see fig. 10 described later) of the base 1 of the TFT substrate 100. One surface 1a of the substrate 1 is parallel to the horizontal direction. The gate lines GCL are connected to the gate driving part 110, respectively. The plurality of signal lines SGL are connected to the source driver 120, respectively.

The gate driving unit 110 generates a gate driving signal based on the signal output from the control circuit. The gate driving unit 110 supplies a gate driving signal to the gate line GCL. The source driver 120 generates a source drive signal based on the signal output from the control circuit. The source driver 120 supplies a source driving signal to the signal line SGL.

The gate driver 110 and the source driver 120 may be provided as a built-in circuit formed directly on the TFT substrate 100, or may be provided on the counter substrate 130 (see fig. 15 described later). The gate driver 110 and the source driver 120 may be mounted on an ic (integrated circuit) mounted on another circuit board (e.g., a flexible substrate) connected to the TFT substrate 100.

As shown in fig. 2, each pixel PX of the TFT substrate 100 includes a pixel transistor TR. The pixel transistor TR is, for example, a bottom gate type NMOS transistor NTR. The NMOS transistor TR has a 1 st NMOS transistor ntr1 and a 2 nd NMOS transistor ntr 2. The 1 st NMOS transistor ntr1 and the 2 nd NMOS transistor ntr2 are connected in series.

The gate of the NMOS transistor NTR includes a gate n1g (see fig. 10 described later) of the 1 st NMOS transistor NTR1 and a gate n2g (see fig. 10 described later) of the 2 nd NMOS transistor NTR 2. The gate of the NMOS transistor NTR is connected to the gate line GCL. The source of the NMOS transistor NTR is connected to the signal line SGL. The drain of the NMOS transistor NTR is connected to the pixel electrode 51 (see fig. 3 described later). A source drive signal (video signal) is supplied to the source of the NMOS transistor NTR from the signal line SGL. A gate drive signal is supplied to the gate of the NMOS transistor NTR from the gate line GCL. When the voltage of the gate drive signal supplied to the NMOS transistor NTR becomes equal to or greater than a predetermined value, the NMOS transistor NTR is turned on. Thereby, a source drive signal (video signal) is supplied from the signal line SGL to the pixel electrode 51 via the NMOS transistor NTR.

Further, each pixel PX of the TFT substrate 100 has a 1 st holding capacitance C1 and a 2 nd holding capacitance C2. The 1 st storage capacitor C1 is formed between the pixel electrode 51 and the common electrode 41 (see fig. 10 described later). The 2 nd storage capacitor C2 is formed between the counter electrode 133 (see fig. 15 described later) of the counter substrate 130 and the pixel electrode 51. A source drive signal (video signal) is supplied to the pixel electrode 51 from the signal line SGL via the pixel transistor TR. A common potential VCOM is supplied to the common electrode 41 and the counter electrode 133. The potential of the source drive signal (video signal) supplied to the pixel electrode 51 is held by the 1 st holding capacitor C1 and the 2 nd holding capacitor C2.

Next, the structure of the TFT substrate will be described. Fig. 3 is a plan view showing an example of arrangement of a plurality of pixels with respect to the TFT substrate of embodiment 1. Fig. 4 is a cross-sectional view showing a positional relationship between a common electrode and a pixel electrode with respect to the TFT substrate of embodiment 1. The cross section shown in fig. 4 is a cross section obtained by cutting the plan view shown in fig. 3 along the line IV-IV'. In fig. 4, the portions located below the planarization film 33 (i.e., on the substrate 1 side) are not shown.

As shown in fig. 3, in the TFT substrate 100, a plurality of pixel electrodes 51 are arranged in a two-dimensional matrix in the X direction and the Y direction intersecting the X direction, respectively. In this embodiment (embodiments 1 to 5), a region overlapping 1 pixel electrode 51 in a plan view is 1 pixel PX. The shape of the pixel electrode 51 in a plan view is, for example, a rectangle. The pixel electrode 51 has 4 sides 51L at the outer periphery.

Further, the shape of the common electrode 41 in a plan view is also, for example, a rectangle. The common electrode 41 has 4 sides 41L at the outer periphery. As shown in fig. 9 and 10, which will be described later, the common electrode 41 is provided with a 3 rd contact hole H3 for connecting the drain electrode 31d to the pixel electrode 51.

As shown in fig. 4, in each pixel PX, a common electrode 41 is provided on the planarization film 33. Further, a reflective film 43 is provided on the common electrode 41. Further, an insulating film 45 is provided on the planarization film 33. The common electrode 41 and the reflective film 43 are covered with an insulating film 45. Further, a pixel electrode 51 is provided on the insulating film 45. The common electrodes 41 are arranged in a two-dimensional matrix in the X direction and the Y direction intersecting the X direction. The common electrodes 41 adjacent to each other among the plurality of common electrodes 41 are separated from each other.

As shown in fig. 3 and 4, the common electrode 41 is located below the pixel electrode 51. In a plan view, all of the 4 sides 41L of the outer periphery of the common electrode 41 are located inside the pixel electrode 51. The plurality of pixel electrodes 51 and the plurality of common electrodes 51 face each other 1 to 1. That is, in 1 pixel PX, each side 41L of the common electrode 41 is located closer to the center of the pixel PX than each side 51L of the pixel electrode 51. For example, in 1 pixel PX, X1 represents the horizontal distance between the outer peripheral side 41L of the common electrode 41 and the outer peripheral side 51L of the pixel electrode 51 adjacent to the side 41L. The distance X1 is 0.1 μm to 25 μm.

Further, the reflective film 43 is located above the common electrode 41. The shape of the reflective film 43 in plan view is also, for example, rectangular. The reflective film 43 has 4 sides 43L on the outer periphery. In a plan view, all of the 4 sides 43L of the outer periphery of the reflective film 43 are located inside the common electrode 41. That is, in 1 pixel PX, each side 43L of the reflective film 43 is located closer to the center of the pixel PX than each side 41L of the common electrode 41.

Fig. 5 is a plan view showing a configuration example of the TFT substrate according to embodiment 1. Fig. 6 is a sectional view showing a structural example of the coupling portion according to embodiment 1. The cross section shown in FIG. 6 is a cross section obtained by cutting the plan view shown in FIG. 5 along line VI-VI'. As shown in fig. 5 and 6, the TFT substrate 100 includes a connection portion 50 that connects the plurality of common electrodes 41 to each other. For example, the connection portion 50 connects the common electrodes 41 adjacent in the X direction to each other. The connection portion 50 includes a plurality of lines COML extending parallel to the gate line GCL, and a 1 st relay portion rel1 connecting the lines COML to the common electrode 41 in each pixel.

As described above, the plurality of pixels PX are arranged in a two-dimensional matrix in the X direction and the Y direction, respectively. The plurality of wirings COML extend in the X direction and are arranged in the Y direction. In a plan view, the plurality of wirings COML are arranged in the Y direction so that 1 wiring COML overlaps 1 pixel PX.

In addition, in the Y direction, the wirings COML and the gate lines GCL are alternately arranged. For example, in the Y direction, the wirings COML and the gate lines GCL are arranged in the order of the wiring COML (n), the gate line GCL (n), the wiring COML (n +1), and the gate line GCL (n +1) …. Thus, the plurality of signal lines SGL are orthogonal to the wirings COML and the gate lines GCL in a plan view.

The wiring COML is provided in the same layer (layer) as the gate line GCL. The wiring COML is made of a material of the same composition as the gate line GCL. The wiring COML and the gate line GCL are formed simultaneously in the same step.

As shown in fig. 6, the wiring COML is covered with an insulating film 13. The insulating film 13 is provided with a through hole 13H. Further, an interlayer insulating film 23 is provided on the insulating film 13. The interlayer insulating film 23 has a through hole 23H. The through hole 23H and the through hole 13H are connected in the Z direction. The 1 st relay portion rel1 is provided on the interlayer insulating film 23, and fills the through hole 23H and the through hole 13H. Further, the 1 st relay portion rel1 is covered with the planarization film 33. The planarizing film 33 has a through hole 33H. The through-hole 33H is provided at a position not aligned with the through-hole 23H and the through-hole 13H in the Z direction (i.e., a position shifted in the horizontal direction with respect to the through-hole 23H and the through-hole 13H). The common electrode 41 is provided on the planarization film 33 and fills the through hole 33H. Thus, the wiring COML is electrically connected to the common electrode 41 via the 1 st relay rel 1. That is, in the contact hole 13H, the connection portion 50 is in contact with the common electrode 41 of the transparent conductive film.

In the present embodiment, the configuration of the coupling portion 50 is not limited to the configuration shown in fig. 6. Fig. 7 is a sectional view showing another configuration example (1) of the coupling portion according to embodiment 1. As shown in fig. 7, the through-hole 33H may be provided in a position aligned with the through-holes 23H and 13H in the Z direction. In such a configuration, the wiring COML is also connected to the common electrode 41 via the 1 st relay rel 1.

The coupling portion 50 may have a 2 nd relay unit rel2 in addition to the 1 st relay unit rel 1. Fig. 8 is a sectional view showing another configuration example (2) of the coupling portion according to embodiment 1. As shown in fig. 8, the connection portion 50 includes the wiring COML, the 1 st relay rel1, and the 2 nd relay rel 2. For example, the 2 nd relay portion rel2 is formed of an island-shaped semiconductor film provided between the insulating film 13 and the interlayer insulating film 23, and is interposed between the 1 st relay portion rel1 and the wiring COML. In the connection portion 50, the 1 st relay rel1 is connected to the 2 nd relay rel2 through the through hole 23H, and the 2 nd relay rel2 is connected to the wiring COML through the through hole 13H. The through-holes 13H, 23H, and 33H are provided at positions not aligned with each other in the Z direction. With such a configuration, the wiring COML is connected to the common electrode 41 via the 2 nd relay rel2 and the 1 st relay rel 1.

In the present embodiment, in fig. 8, the through-holes 13H, 23H, and 33H may be provided in a row in the Z direction. In such a configuration, the wiring COML is also connected to the common electrode 41 via the 2 nd relay rel2 and the 1 st relay rel 1.

The 1 st relay rel1 is provided in the same layer as the signal line SGL and a drain 31d (see fig. 10) described later. The 1 st relay portion rel1 is made of the same material as the signal line SGL and the drain 31 d. The 1 st relay rel1 is formed simultaneously with the signal line SGL and the drain 31d in the same step. In addition, the 2 nd relay portion re2 shown in the example of fig. 8 is formed of a material having the same composition as that of the semiconductor film 21 (see fig. 10) described later. The 2 nd intermediate portion re2 is formed simultaneously with the semiconductor film 21 in the same step.

The wiring COML is connected to, for example, a power supply circuit of an electronic device not shown. The common potential VCOM (for example, 0V) is supplied from the power supply circuit to the wiring COML. The common potential VCOM supplied to the wiring COML is supplied to the common electrode 41 via the 1 st relay portion rel 1.

Next, the structure of the pixel transistor TR (see fig. 2) and its periphery will be described. Fig. 9 is a plan view showing an enlarged region including a pixel transistor in the TFT substrate of embodiment 1. The region ar1 shown in fig. 5 is a region including a pixel transistor. In fig. 9, the pixel electrode 51, the insulating film 45, and the planarizing film 33 shown in fig. 4 are omitted in order to facilitate the visibility of the structure of each portion located below the pixel electrode 51 (i.e., on the substrate 1 side). FIG. 10 is a cross-sectional view of the plan view of FIG. 9 taken along line X-X'.

As shown in fig. 9 and 10, a gate line GCL and an insulating film 13 are provided on one surface 1a of the base material 1. The insulating film 13 covers the gate line GCL. Further, a semiconductor film 21 and an interlayer insulating film 23 are provided on the insulating film 13. The interlayer insulating film 23 covers the semiconductor film 21. The interlayer insulating film 23 is provided with a 1 st contact hole H1 and a 2 nd contact hole H2. The 1 st contact hole H1 and the 2 nd contact hole H2 are through holes having the semiconductor film 21 as a bottom surface.

As shown in fig. 9, the shape of the semiconductor film 21 in plan view is, for example, a U shape (or a J shape). That is, the semiconductor film 21 has the linear 1 st portion 211, the linear 2 nd portion 212, and the linear 3 rd portion 213. The 2 nd site 212 is connected to one end of the 1 st site 211, and the 3 rd site 213 is connected to the other end of the 1 st site 211. The angle between region 1 211 and region 2 212 is about 90. The angle between region 1 211 and region 3 213 is also about 90.

The gate line GCL intersects the U-shaped semiconductor film 21 in plan view. In the gate line GCL, a portion intersecting the semiconductor film 21 is a gate of the pixel transistor TR (see fig. 2). In the semiconductor film 21, a portion intersecting the gate line GCL serves as a channel of the pixel transistor TR.

As shown in fig. 2, the pixel transistor TR has an NMOS transistor NTR. The NMOS transistor NTR has a 1 st NMOS transistor NTR1 and a 2 nd NMOS transistor NTR 2. In the gate line GCL, a portion intersecting the 2 nd site 212 of the semiconductor film 21 is a gate of the 1 st NMOS transistor ntr 1. In the gate line GCL, a portion intersecting the 3 rd site 213 of the semiconductor film 21 is a gate of the 2 nd NMOS transistor ntr 2. The semiconductor film 21 is connected to the signal line SGL.

As shown in fig. 9 and 10, the signal line SGL and the drain 31d of the pixel transistor TR are provided on the interlayer insulating film 23, respectively. That is, the signal line SGL and the drain 31d are provided in the same layer.

In the signal line SGL, a portion where the 1 st contact hole H1 is buried and its peripheral portion are the source 31s of the pixel transistor TR. The drain electrode 31d is disposed at a position away from the signal line SGL, and fills the 2 nd contact hole H2. The shape of the drain electrode 31d in plan view is, for example, a rectangle. The signal line SGL including the source electrode 31s and the drain electrode 31d are formed of, for example, conductive films of the same composition. In the present embodiment, the source 31s may be referred to as a source electrode, and the drain 31d may be referred to as a drain electrode.

The signal line SGL overlaps a part of the gate line GCL (e.g., the gate n1g) in a plan view. Further, the 1 st end portion 311A of the drain electrode 31d overlaps with a part of the gate line GCL (e.g., the drain-side end portion of the gate electrode n2 g) in a plan view. Thus, even if a part of the incident light (for example, light obliquely incident on the one surface 1A of the substrate 1) enters the pixel transistor TR, the light is blocked by the signal line SGL and the 1 st end 311A of the drain 31 d. This can suppress light from entering the gates n1g and n2g, and hence photoelectric conversion in the pixel transistor TR is suppressed. In the TFT substrate 100, the possibility that the pixel transistor TR malfunctions due to photoelectric conversion is reduced.

Further, as shown in fig. 10, a planarization film 33 is provided on the interlayer insulating film 23. The planarization film 33 covers the signal line SGL. The upper surface 33a of the planarization film 33 is flat and parallel to the one surface 1a of the substrate 1. The planarization film 33 is provided with a 3 rd contact hole H3. As shown in fig. 10, the 3 rd contact hole H3 is a through hole having the drain electrode 31d as a bottom surface.

Further, a common electrode 41 is provided on the planarization film 33. As shown in fig. 10, the common electrode 41 has a through hole 41H. The through hole 41H surrounds the 3 rd contact hole H3. Further, a reflective film 43 is provided on the common electrode 41. The reflective film 43 is provided with 1 through hole 43H. As shown in fig. 9, the through-hole 43H surrounds the through-hole 41H in a plan view.

Further, an insulating film 45 is provided on the planarization film 33. The common electrode 41 and the reflective film 43 are covered with an insulating film 45. Insulating film 45 covers inner surfaces of 3 rd contact hole H3 and through holes 41H and 43H. The insulating film 45 is a dielectric of the 1 st storage capacitor C1 (see fig. 2), and is also a part of a dielectric of the 2 nd storage capacitor C2 (see fig. 2).

Further, a pixel electrode 51 is provided on the insulating film 45. The pixel electrode 51 covers the common electrode 41 with an insulating film 45 interposed therebetween. Further, the pixel electrode 51 fills the 3 rd contact hole H3. Thereby, the pixel electrode 51 is connected to the drain 31d of the pixel transistor TR.

Next, materials constituting each part of the TFT substrate 100 are exemplified. The substrate 1 is made of glass or a flexible resin substrate. The gate line GCL and the wiring COML (see fig. 6) are made of a material containing molybdenum. The insulating film 13 is formed of an inorganic film such as a silicon oxide film or a silicon nitride film. For example, the insulating film 13 is a film having a stacked structure in which a silicon oxide film and a silicon nitride film are stacked in this order from the substrate 1 side. The semiconductor film 21 is made of a polysilicon film. In the polysilicon film, a portion exposed from the gate line GCL contains an impurity such as phosphorus or boron, and has conductivity. The semiconductor film 21 may be amorphous silicon or an oxide semiconductor film. The interlayer insulating film 23 is formed of an inorganic film such as a silicon oxide film or a silicon nitride film. For example, the interlayer insulating film 23 is formed of a film having a stacked structure in which a silicon oxide film, a silicon nitride film, and a silicon oxide film are stacked in this order from the substrate 1 side.

The signal line SGL (including the source 31s), the drain 31d, and the 1 st relay rel1 are made of titanium and aluminum. For example, the signal line SGL, the drain electrode 31d, and the 1 st intermediate portion rel1 are formed of a film having a laminated structure in which titanium, aluminum, and titanium are laminated in this order from the substrate 1 side. The planarizing film 33 is made of an organic film such as an acrylic resin. The common electrode 41 is made of ito (indium tin oxide) as a light-transmitting conductive film. The reflective film 43 is made of molybdenum and aluminum. For example, the reflective film 43 is formed of a film having a laminated structure in which molybdenum, aluminum, and molybdenum are laminated in this order from the substrate 1 side. In addition, Ag (silver) may be used for the reflective film 43 in order to further improve reflectivity. The insulating film 45 is formed of an inorganic film such as a silicon nitride film. The pixel electrode 51 is made of ITO formed of a light-transmitting conductive material. The pixel electrode 51 and the common electrode 41 are not limited to the light-transmitting conductive film, and may be formed of a light-shielding metal material having reflectivity.

The above materials are merely examples. In this embodiment, each portion of the TFT substrate 100 may be made of a material other than the above. For example, the gate line GCL and the wiring COML may be formed of a film of aluminum, copper, silver, molybdenum, or an alloy thereof. The signal line SGL, the drain 31d, and the 1 st relay rel1 may be made of titanium aluminum, which is an alloy of titanium and aluminum.

Next, a method for manufacturing the TFT substrate 100 according to embodiment 1 will be described with reference to cross-sectional views. Fig. 11 to 14 are sectional views for explaining a method of manufacturing the TFT substrate. Fig. 11 to 14 correspond to the sectional view shown in fig. 10, showing the manufacturing process in this section.

As shown in fig. 11, first, a manufacturing apparatus (not shown) forms a conductive film (not shown) such as molybdenum on a substrate 1. The conductive film is formed by sputtering or the like. Next, the manufacturing apparatus patterns the conductive film by photolithography and dry etching to form the gate line GCL and the wiring COML (see fig. 6). For example, the manufacturing apparatus forms a resist (not shown) over the conductive film. The resist is patterned by photolithography, and is formed in a shape so as to cover the region where the gate line GCL and the wiring COML are formed and expose the region other than the region. Next, the manufacturing apparatus removes the conductive film in the region exposed from the resist by a dry etching technique. Thereby, the gate line GCL and the wiring COML are formed from the conductive film. After the gate line GCL and the wiring COML are formed, the manufacturing apparatus removes the resist.

Next, the manufacturing apparatus forms the insulating film 13 on the substrate 1. The insulating film 13 is formed by a CVD (chemical vapor Deposition) method or the like. Thereby, the gate line GCL and the wiring COML are covered with the insulating film 13.

Next, the manufacturing apparatus forms a semiconductor film on the insulating film 13. The semiconductor film is formed by a CVD method or the like. Next, the manufacturing apparatus performs patterning of the semiconductor film by photolithography and dry etching. Thus, the manufacturing apparatus forms the semiconductor film 21 having a U-shape in plan view. After the formation of the semiconductor film 21, the manufacturing apparatus removes the resist.

Next, as shown in fig. 12, the manufacturing apparatus forms an interlayer insulating film 23 on the insulating film 13. The interlayer insulating film 23 is formed by a CVD method or the like. Thereby, the semiconductor film 21 is covered with the interlayer insulating film 23.

Next, the manufacturing apparatus forms the 1 st contact hole H1, the 2 nd contact hole H2, and the through hole 23H in the interlayer insulating film 23 (see fig. 6). For example, the manufacturing apparatus patterns the interlayer insulating film 23 by photolithography and dry etching to form the 1 st contact hole H1, the 2 nd contact hole H2, the through hole 23H, and the through hole 13H (see fig. 6). The semiconductor film 21 serving as an etching stopper is present below the 1 st contact hole H1 and below the 2 nd contact hole H2, but the semiconductor film 21 is not present below the through hole 23H. Therefore, the through-hole 13H is continuously formed below the through-hole 23H. After the formation of the 1 st contact hole H1, the 2 nd contact hole H2, the through hole 23H, and the through hole 13H, the manufacturing apparatus removes the resist.

Next, the manufacturing apparatus forms the signal line SGL (including the source 31s, the drain 31d, and the 1 st intermediate portion rel1 shown in fig. 10) on the interlayer insulating film 23 (see fig. 6). For example, the manufacturing apparatus forms titanium, then aluminum, and then titanium as a metal film on the interlayer insulating film 23. The metal film is formed by sputtering or the like. Next, the manufacturing apparatus patterns the metal film by photolithography and dry etching. Thus, the manufacturing apparatus forms the signal line SGL connected to the semiconductor film 21 via the 1 st contact hole H1, the drain electrode 31d connected to the semiconductor film 21 via the 2 nd contact hole H2, and the 1 st relay portion rel1 having an island shape in a plan view. Then, the manufacturing apparatus removes the resist.

Next, as shown in fig. 13, the manufacturing apparatus forms a planarization film 33 on the interlayer insulating film 23. The planarizing film 33 is insulating, and is made of an organic material such as an acrylic resin. The planarizing film 33 is formed by slit coating (slit coating) or spin coating (spin coating). Thereby, the signal line SGL including the source 31s, the drain 31d, and the 1 st relay portion rel1 are covered with the planarization film 33. When an organic material such as an acrylic resin is used for the planarizing film 33, the planarizing film 33 can be made thick. Therefore, the parasitic capacitance between the common electrode 41 and the signal line SGL and the parasitic capacitance between the common electrode 41 and the drain 31d can be reduced.

Next, as shown in fig. 14, the manufacturing apparatus forms the common electrode 41 and the reflective film 43 on the planarization film 33. For example, the manufacturing apparatus forms a conductive film such as ITO on the planarization film 33. Next, the manufacturing apparatus sequentially forms molybdenum, aluminum, and molybdenum as a metal film on the conductive film. The conductive film and the metal film are formed by a sputtering method or the like. Next, the manufacturing apparatus patterns the metal film by photolithography and dry etching. Thus, the manufacturing apparatus forms the reflective film 43 having the through hole 43H. Next, the manufacturing apparatus patterns the conductive film by photolithography and dry etching. Thereby, the manufacturing apparatus forms the common electrode 41 having the through hole 41H. After the formation of the common electrode 41, the manufacturing apparatus removes the resist.

Next, the manufacturing apparatus forms the 3 rd contact hole H3 in the planarization film 33. For example, the manufacturing apparatus forms the 3 rd contact hole H3 by patterning the planarization film 33 by photolithography and dry etching. After the formation of the 3 rd contact hole H3, the manufacturing apparatus removes the resist.

Next, the manufacturing apparatus forms an insulating film 45 on the substrate 1 (see fig. 10). The insulating film 45 is formed by a CVD method or the like. Thereby, the common electrode 41 and the reflective film 43 are covered with the insulating film 45. The inner surface and bottom of the 3 rd contact hole H3 are also covered with the insulating film 45. Next, the manufacturing apparatus removes the portion of the insulating film 45 covering the bottom of the 3 rd contact hole H3. For example, the manufacturing apparatus removes the insulating film 45 from the bottom of the 3 rd contact hole H3 by patterning the insulating film 45 by photolithography and dry etching. Then, the manufacturing apparatus removes the resist.

Next, the manufacturing apparatus forms the pixel electrode 51 on the insulating film 45 (see fig. 10). For example, the manufacturing apparatus forms a conductive film such as ITO on the insulating film 45. The conductive film is formed by sputtering or the like. Next, the manufacturing apparatus patterns the conductive film by photolithography and dry etching. Thus, the manufacturing apparatus forms the pixel electrode 51 connected to the drain electrode 31d through the 3 rd contact hole H3. After the formation of the pixel electrode 51, the manufacturing apparatus removes the resist. Through the above steps, the TFT substrate 100 of embodiment 1 is completed.

Next, the structure of the display device 200 according to embodiment 1 will be described. Fig. 15 is a sectional view showing a configuration example of a display device according to embodiment 1. As shown in fig. 15, the display device 200 according to embodiment 1 includes the TFT substrate 100, the counter substrate 130 disposed to face the TFT substrate 100, the electrophoretic layer 160 disposed between the TFT substrate 100 and the counter substrate 130, and the sealing portion 152.

The counter substrate 130 includes a base 131 and a counter electrode 133. The substrate 131 is a light-transmitting glass substrate, a light-transmitting resin substrate, or a light-transmitting resin film. The counter electrode 133 is provided on the side of the base 131 facing the TFT substrate 100. The counter electrode 133 is made of ITO, which is a light-transmitting conductive film. The counter electrode 133 and the pixel electrode 51 face each other with the electrophoretic layer 160 interposed therebetween.

The sealing portion 152 is provided between the TFT substrate 100 and the counter substrate 130. The electrophoretic layer 160 is sealed in an internal space surrounded by the TFT substrate 100, the counter substrate 130, and the sealing portion 152. The seal 152 is provided with a connecting member 153. The counter electrode 133 is connected to the common electrode 41 of the TFT substrate 100 via a connection member 153. Thereby, the common potential VCOM is supplied to the counter electrode 133.

The electrophoretic layer 160 includes a plurality of microcapsules 163. Inside the microcapsule 163, a plurality of black fine particles 161, a plurality of white fine particles 162, and a dispersion 165 are sealed. A plurality of black fine particles 161 and a plurality of white fine particles 162 are dispersed in the dispersion liquid 165. The dispersion 165 is a light-transmitting liquid such as silicone oil. The black fine particles 161 are electrophoretic particles, and for example, negatively charged graphite is used. The white fine particles 162 are electrophoretic particles, and are formed of, for example, positively charged titanium oxide (TiO)₂). Further, the plurality of microcapsules 163 may contain therein a plurality of black fine particles 161 and a plurality of fine particles of a color other than the white fine particles 162.

By forming an electric field between the pixel electrode 51 and the counter electrode 133, the dispersion state of the black particles 161 and the white particles 162 changes. The transmission state of light transmitted through the electrophoretic layer 160 changes according to the dispersion state of the black particles 161 and the white particles 162. Thereby, an image is displayed on the display surface. For example, when a common potential VCOM (for example, 0V) is supplied to the counter electrode 133 and a negative potential is supplied to the pixel electrode 51, the negatively charged black particles 161 move toward the counter substrate 130 and the positively charged white particles 162 move toward the TFT substrate 100. Thus, when the TFT substrate 100 is viewed from the counter substrate 130 side, a region (pixel) overlapping the pixel electrode 51 in a plan view is displayed in black.

Fig. 16 is a graph showing the results of examining the relationship between the distance between the outer periphery of the pixel electrode and the outer periphery of the common electrode and the electric field intensity for 1 pixel. The horizontal axis in fig. 16 indicates the horizontal distance X1(μm) between the outer peripheral side of the common electrode and the outer peripheral side of the pixel electrode. The vertical axis in fig. 16 represents the minimum value of the electric field immediately below the counter electrode in 1 pixel. In fig. 16, when the value of the distance X1 is positive, the outer periphery of the common electrode is located inside the pixel electrode in a plan view. In the case where the value of the distance X1 is negative, the outer periphery of the common electrode is located outside the pixel electrode in plan view. In the case where the distance X1 is 0, the outer periphery of the common electrode overlaps the outer periphery of the pixel electrode in a plan view.

Fig. 17 is a plan view showing a structural example of a TFT substrate of a comparative example. FIG. 18 is a sectional view of the plan view of FIG. 17 cut along line XVIII-XVIII'. As shown in fig. 17 and 18, in the TFT substrate 300 of the comparative example, the common electrode 341 is integrated between the adjacent pixels PX. In the TFT substrate 300, 1 common electrode 341 is provided below the plurality of pixel electrodes 51 arranged in the X direction and the Y direction, respectively. The size of the common electrode 341 in a plan view is larger than that of the pixel electrode 51.

In fig. 16, point a corresponds to the TFT substrate 300 of the comparative example described above. At the point a, the common electrode is integrated between the adjacent pixels PX. Point B indicates when the outer periphery of the common electrode overlaps the outer periphery of the pixel electrode. At the point B, the outer periphery of the common electrode is coplanar with the outer periphery of the pixel electrode in the vertical direction (Z direction) perpendicularly intersecting the horizontal plane (X-Y plane). Point C indicates that the electric field intensity Y1 is equal to or higher than this. Point D indicates when the common electrode is not provided. The electric field strength at point D is Y0. In fig. 16, the electric field strength of-5% is defined as Y1 and the lead is drawn, and the electric field strength of + 5% is defined as Y2 and the lead is drawn, based on the electric field strength Y0. Y1 ═ 0.95 × Y0, and Y2 ═ 1.05 × Y0.

As can be seen from fig. 16, the value of the electric field intensity increases as the value of the distance X1 increases. It is also understood that the increase rate of the electric field intensity between the points B, C with respect to the distance X1 is larger than that between the points A, B. In particular, it is found that when the distance X1 becomes larger than 0, the rate of increase in the electric field intensity with respect to the distance X1 becomes rapidly large. It is also understood that the ratio of the increase in electric field strength to the increase in distance X1 between points C, D is more gradual than between points B, C.

As described above, the TFT substrate 100 of embodiment 1 includes the insulating substrate 1, the pixel electrode 51 provided on the side of the one surface 1a of the substrate 1, and the common electrode 41 provided between the substrate 1 and the pixel electrode 51. The sides 41L of the outer periphery of the common electrode 41 are all located inside the pixel electrode 51 in plan view. This can suppress leakage of an electric field to the outside from a gap S (see fig. 4 and 5) between the one pixel electrode 51 and the other pixel electrode 51 (between the pixel electrodes 51) adjacent to each other, and can reduce a leakage electric field from the gap S between the pixel electrodes 51. This can suppress a decrease in the electric field intensity in each pixel PX. Therefore, in the display device 200 using the TFT substrate 100, display unevenness can be reduced, and a decrease in contrast can be suppressed, so that display performance can be improved. The TFT substrate 100 and the display device 200 can be provided with improved display performance.

The TFT substrate 100 further includes a connection portion 50 provided between the substrate 1 and the pixel electrode 51. A plurality of pixel electrodes 51 are arranged in the X direction and the Y direction intersecting the X direction in a plan view. The common electrode 41 is arranged in plural in the X direction and the Y direction. The connection portion 50 connects the common electrodes 41 to each other in at least one of the X direction and the Y direction. For example, the connection portion 50 connects the plurality of common electrodes 41 arranged in the X direction to each other. Thereby, the TFT substrate 100 can supply the common potential VCOM to the plurality of common electrodes 41 arranged in the X direction via the connection portion 50. The number of wirings can be reduced compared to the case where 1 wiring is connected to 1 common electrode to supply the common potential VCOM.

The TFT substrate 100 further includes a gate line GCL extending in the X direction between the base 1 and the pixel electrode 51. The connection portion 50 includes a wiring COML provided in the same layer as the gate line GCL. Thus, the manufacturing apparatus can form the wiring COML and the gate line GCL at the same time in the same step, and thus can suppress an increase in the number of manufacturing steps. Further, since the wiring COML is provided in the same layer as the gate line GCL, an increase in the number of layers of the TFT substrate 100 can be suppressed, which can contribute to the thinning of the TFT substrate 100.

The connection portion 50 is located on a layer lower than the common electrode 41 (i.e., on the substrate 1 side). Therefore, the parasitic capacitance generated between the connection portion 50 and the pixel electrode 51 can be suppressed to be lower than in the case where the connection portion 50 is located on the same layer as the common electrode 41 or in the case where the connection portion 50 is located on the upper layer than the common electrode 41.

(modification example)

In embodiment 1 described above, the common electrode 41 is provided with the reflective film 43. However, in embodiment 1 and embodiments 2, 4, and 5 described later, the reflective film 43 is not essential. Fig. 19 is a cross-sectional view showing a configuration example of a TFT substrate according to modification 1 of embodiment 1.

Fig. 19 shows a cross section of the TFT substrate 100A according to modification 1 of embodiment 1 cut at the same position as the line IV-IV' (see fig. 3). For example, as in the TFT substrate 100A shown in fig. 19, the reflective film 43 may not be disposed on the common electrode 41. This configuration also provides the same effects as those of embodiment 1 described above.

In embodiment 1 described above, the pixel transistor TR is of a bottom gate type. However, in this embodiment, the pixel transistor TR is not limited to the bottom gate type. The pixel transistor TR may also be of a top gate type.

Fig. 20 and 21 are cross-sectional views showing a configuration example of a TFT substrate according to modification 2 of embodiment 1. Fig. 20 shows a cross section of the TFT substrate 100B according to modification 2 of embodiment 1 cut at the same position as the X-X' line (see fig. 9). Fig. 21 shows a cross section of the TFT substrate 100B according to modification 2 of embodiment 1 cut at the same position as the line IV-IV' (see fig. 3). For example, in the TFT substrate 100B shown in fig. 20, the pixel transistor is an NMOS transistor NTR having a top-gate type 1 st NMOS transistor NTR1 and a top-gate type 2 nd NMOS transistor NTR 2. In the TFT substrate 100B, a semiconductor film 21 is provided on one surface 1a of the base 1.

As shown in fig. 20 and 21, an insulating film 13 is provided on one surface 1a of the substrate 1. The insulating film 13 covers the semiconductor film 21. Further, the gate line GCL and the wiring COML are provided on the insulating film 13. The wiring COML is connected to the 1 st relay rel1 through the through hole 23H.

In embodiment 1 described above, the wiring COML and the common electrode 41 are connected via the 1 st relay rel1 (or the 1 st relay rel1 and the 2 nd relay rel 2). However, in embodiment 1, the connection between the wiring COML and the common electrode 41 is not limited thereto. The wiring COML and the common electrode 41 may be directly connected without passing through the 1 st relay rel1 and the 2 nd relay rel 2.

(embodiment mode 2)

In embodiment 1 described above, the case where the wiring COML included in the connection portion 50 is provided in the same layer as the gate line GCL is described. However, in this embodiment, the wiring COML may be provided in a layer different from the gate line GCL.

Fig. 22 is a plan view showing a configuration example of a TFT substrate according to embodiment 2. Fig. 23 is a sectional view showing a structural example of the coupling portion according to embodiment 2. The cross section shown in FIG. 23 is a cross section obtained by cutting the plan view shown in FIG. 22 along the line XXII-XXII'. As shown in fig. 22 and 23, the TFT substrate 100C of embodiment 2 has a connection portion for connecting the plurality of common electrodes 41 to each other. For example, the connection portion connects the common electrodes 41 adjacent in the Y direction to each other. The connection portions are a plurality of lines COML extending parallel to the signal line SGL.

In the TFT substrate 100C, a plurality of wirings COML are provided extending in the Y direction and arranged in the X direction. In a plan view, the plurality of wirings COML are arranged in the X direction so that 1 wiring COML overlaps 1 pixel PX. In addition, in the X direction, the wirings COML and the signal lines SGL are alternately arranged. For example, in the Y direction, the wiring COML and the signal line SGL are arranged in the order of the wiring COML (m), the signal line SGL (m), the wiring COML (m +1), and the signal line SGL (m +1) …. Thus, the plurality of gate lines GCL are orthogonal to the wirings COML and the signal lines SGL in a plan view.

The wiring COML is provided in the same layer as the signal line SGL. The wiring COML is made of the same material as the signal line SGL. The wiring COML and the signal line SGL are formed simultaneously in the same process.

As shown in fig. 23, the wiring COML is provided on the interlayer insulating film 23 and covered with a planarization film 33. The planarizing film 33 has a through hole 33H. The common electrode 41 is provided on the planarization film 33 and fills the through hole 33H. Thereby, the wiring COML is connected to the common electrode 41. The common potential VCOM (for example, 0V) is supplied to the wiring COML from a power supply circuit (not shown). The common potential VCOM supplied to the wiring COML is supplied to the common electrode 41.

In the TFT substrate 100C according to embodiment 2, the entire outer peripheral edge 41L of the common electrode 41 is located inside the pixel electrode 51. This can suppress leakage of an electric field from the gap S between the pixel electrodes 51 to the outside, and can reduce the leakage electric field from the gap S between the pixel electrodes 51. Thus, the TFT substrate 100C of embodiment 2 achieves the same effects as the TFT substrate 100 of embodiment 1.

The connection portion 50 connects the plurality of common electrodes 41 arranged in the Y direction to each other. Thereby, the TFT substrate 100C can supply the common potential VCOM to the plurality of common electrodes 41 arranged in the Y direction via the connection portion 50. The number of wirings can be reduced compared to the case where 1 wiring is connected to 1 common electrode to supply the common potential VCOM.

The TFT substrate 100C includes a signal line SGL extending in the Y direction between the base 1 and the pixel electrode 51. The connection portion 50 has a wiring COML provided in the same layer as the signal line SGL. Thus, the manufacturing apparatus can simultaneously form the wiring COML and the signal line SGL in the same step, and thus increase in the number of manufacturing steps can be suppressed. Further, since the wiring COML is provided in the same layer as the signal line SGL, an increase in the number of layers of the TFT substrate 100C can be suppressed, which can contribute to the thinning of the TFT substrate 100C.

In the TFT substrate 100C, the wiring COML is also located in a layer below the common electrode 41 (i.e., on the substrate 1 side). Therefore, the parasitic capacitance generated between the wiring COML and the pixel electrode 51 can be suppressed to be lower than in the case where the wiring COML is located on the same layer as the common electrode 41 or in the case where the wiring COML is located on the upper layer than the common electrode 41.

(modification example)

In the present embodiment, the pixel transistor TR may include a PMOS transistor instead of the NMOS transistor TR. In the present embodiment, the pixel transistor TR may include both an NMOS transistor and a PMOS transistor. Hereinafter, a case where the pixel transistor TR includes both an NMOS transistor and a PMOS transistor will be specifically described as a modification of embodiment 2.

Fig. 24 is a circuit diagram showing a configuration example of 1 pixel with respect to the TFT substrate of the modification of embodiment 2. As shown in fig. 24, the pixel transistor TR has an NMOS transistor NTR, and a PMOS transistor PTR connected in parallel with the NMOS transistor NTR. The PMOS transistor PTR has a 1 st PMOS transistor PTR1 and a 2 nd PMOS transistor PTR 2. The 1 st PMOS transistor ptr1 and the 2 nd PMOS transistor ptr2 are connected in series.

Fig. 25 is a plan view showing a configuration example of a TFT substrate according to a modification of embodiment 2. In the TFT substrate 100D according to the modification of embodiment 2, the 1 st gate lines GCL-N are arranged to extend in the X direction and to be aligned in the Y direction. A plurality of 2 nd gate lines GCL-P are also extended in the X direction and arranged in the Y direction. In the Y direction, the 1 st gate line GCL-N and the 2 nd gate line GCL-P are alternately arranged. For example, in the Y direction, the 1 st gate line GCL-N and the 2 nd gate line GCL-P are arranged in the order of the 1 st gate line GCL-N (N), the 2 nd gate line GCL-P (N), the 1 st gate line GCL-N (N +1), and the 2 nd gate line GCL-P (N +1) ….

The plurality of signal lines SGL are orthogonal to the 1 st gate line GCL-N and the 2 nd gate line GCL-P, respectively, in a plan view. The plurality of wirings COML arranged in the same layer as the signal line SGL are also orthogonal to the 1 st gate line GCL-N and the 2 nd gate line GCL-P, respectively, in a plan view.

As shown in FIG. 24, the gate of the NMOS transistor NTR is connected to the 1 st gate line GCL-N. The source of the NMOS transistor NTR is connected to the signal line SGL. The drain of the NMOS transistor NTR is connected to the pixel electrode 51. In addition, the gate of the PMOS transistor PTR is connected to the 2 nd gate line GCL-P. The source of the PMOS transistor PTR is connected to the signal line SGL. The drain of the PMOS transistor PTR is connected to the pixel electrode 51.

The 1 st gate lines GCL-N and the 2 nd gate lines GCL-P are connected to the gate driving part 110 (see fig. 1), respectively. The gate driving unit 110 generates a 1 st gate driving signal and a 2 nd gate driving signal based on the signal output from the control circuit. The gate driving part 110 supplies a 1 st gate driving signal to the 1 st gate line GCL-N and a 2 nd gate driving signal to the 2 nd gate line GCL-P.

In this way, in this embodiment, the pixel transistor TR may have a CMOS (complementary MOS) structure. Thus, as compared with the case where the pixel transistor TR is not of the CMOS structure, the voltage amplitude applied to each of the NMOS transistor NTR and the PMOS transistor PTR can be reduced, and the withstand voltage of the PMOS transistor PTR and the NMOS transistor NTR constituting the pixel transistor TR can be reduced.

(embodiment mode 3)

In embodiments 1 and 2 described above, the case where the wiring COML serving as the connection portion 50 is provided in the same layer as the gate line GCL or the signal line SGL has been described. However, in the present embodiment, the connection portion that connects the plurality of common electrodes is not limited to this. In the present embodiment, the coupling portion may be formed integrally with the reflective film 43.

Fig. 26 is a plan view showing a configuration example of a TFT substrate according to embodiment 3. In the TFT substrate 100E of embodiment 3, the connection portion 44 connecting the plurality of common electrodes 41 to each other is made of a material having the same composition as the reflective film 43, and is formed integrally with the reflective film 43. The connection portion 44 and the reflective film 43 are formed simultaneously in the same step. The reflective film 43 and the connection portion 44 are provided on a surface of the common electrode 41 facing the pixel electrode 51.

As shown in fig. 26, the common electrode 41 and the reflective film 43 are rectangular, for example, square in shape in plan view. On each side 43L of the outer periphery of the reflective film 43, 1 coupling portion 44 is connected. Thereby, the coupling portion 44 couples the reflective films 43 aligned in the X direction to each other, and couples the reflective films 43 aligned in the Y direction to each other. The connection portions 44 connect the reflection films 43 adjacent to each other in the X direction and the Y direction, respectively. The reflective film 43 is conductive and is in contact with the common electrode 41. Therefore, the connection portion 44 connects the common electrodes 41 adjacent in the X direction and the Y direction to each other via the reflection film 43 in contact with the common electrodes 41. The width (i.e., the length in the X direction or the Y direction) of the common electrode 41 is W41, the width of the reflective film 43 is W43, and the width of the connecting portion 44 is W44. The width W44 of the connection portion 44 is smaller than the width W41 of the common electrode 41 and smaller than the width W41 of the reflective film 43. Is W41> W43> W44.

According to the TFT substrate 100E of embodiment 3, the entire outer peripheral side 41L of the common electrode 41 is located inside the pixel electrode 51 in plan view. The width W44 of the connection portion 44 passing below the gap S between the pixel electrodes 51 is smaller than the width W41 of the common electrode 41 and smaller than the width W43 of the reflective film 43. This can suppress leakage of an electric field from the gap between the pixel electrodes 51 to the outside, and can reduce the leakage electric field from the gap S between the pixel electrodes 51.

In addition, since the manufacturing apparatus can form the coupling portion 50 and the reflective film 43 at the same time in the same process, the number of manufacturing processes can be reduced. Further, since the connection portion 50 is provided in the same layer as the reflective film 43, an increase in the number of layers of the TFT substrate 100E can be suppressed, which can contribute to the reduction in thickness of the TFT substrate 100E.

(embodiment mode 4)

In the present embodiment, the connection portion connecting the plurality of common electrodes may be formed integrally with the common electrode 41. Fig. 27 is a plan view showing a configuration example of a TFT substrate according to embodiment 4. In the TFT substrate 100F according to embodiment 4, the connection portion 42 connecting the plurality of common electrodes 41 to each other is made of a material having the same composition as the common electrode 41, and is formed integrally with the common electrode 41. The connection portion 42 and the common electrode 41 are formed simultaneously in the same step.

As shown in fig. 27, the shape of the common electrode 41 in a plan view is a rectangle, for example, a square. Each of the 1 coupling portions 42 is connected to each of the sides 41L of the outer periphery of the common electrode 41. Thereby, the connection portion 42 connects the common electrodes 41 adjacent to each other in the X direction and the Y direction. The width (i.e., the length in the X direction or the Y direction) of the common electrode 41 is W41, and the width of the connection portion 42 is W42. The width W42 of the connection portion 42 is smaller than the width W41 of the common electrode 41. Is W41> W42.

According to the TFT substrate 100F of embodiment 4, the entire outer peripheral side 41L of the common electrode 41 is located inside the pixel electrode 51 in plan view. The width W42 of the connection portion 42 passing through the space S between the pixel electrodes 51 is smaller than the width W41 of the common electrode 41. This can suppress leakage of an electric field from the gap between the pixel electrodes 51 to the outside, and can reduce the leakage electric field from the gap S between the pixel electrodes 51.

In addition, since the manufacturing apparatus can form the connection portion 42 and the common electrode 41 simultaneously in the same process, the number of manufacturing processes can be reduced. Further, since the connection portion 42 is provided in the same layer as the common electrode 41, an increase in the number of layers of the TFT substrate 100F can be suppressed, which can contribute to the reduction in thickness of the TFT substrate 100F.

(embodiment 5)

In embodiment 4 described above, the connection portion 42 connects the common electrodes 41 adjacent to each other in the X direction and the Y direction. However, the connection portion 42 may connect the common electrodes adjacent to each other not in both the X direction and the Y direction but in one of the X direction and the Y direction. Fig. 28 is a plan view showing a configuration example of a TFT substrate according to embodiment 5. In the TFT substrate 100G of embodiment 5, the connection portion 42 formed integrally with the common electrode 41 connects the common electrodes 41 adjacent to each other in the X direction.

According to the TFT substrate 100G of embodiment 5, the entire outer peripheral side 41L of the common electrode 41 is located inside the pixel electrode 51 in plan view. The width W42 of the connection portion 42 is smaller than the width W41 of the common electrode 41. This can suppress leakage of an electric field from the gap between the pixel electrodes 51 to the outside, and can reduce the leakage electric field from the gap S between the pixel electrodes 51.

(modification example)

Fig. 29 is a plan view showing a configuration example of a TFT substrate according to a modification of embodiment 5. In the TFT substrate 100H according to the modification of embodiment 5, the connection portion 42 formed integrally with the common electrode 41 connects the common electrodes 41 adjacent to each other in the Y direction. This configuration also provides the same effects as those of embodiment 5 described above.

In addition, in patent document 1, as shown in fig. 5, a part of the 2 nd storage capacitor 71B (corresponding to the common electrode) protrudes from the 1 st storage capacitor 51A (corresponding to the pixel electrode) in a plan view. In the 2 nd storage capacitor 71B, the width in the longitudinal direction of the paper surface of the portion extending from the 1 st storage capacitor 51A is the same as the width in the longitudinal direction of the paper surface of the portion covered by the 1 st storage capacitor 51A. Therefore, in patent document 1, it is considered that the electric field leaking from the gap between the 1 st storage capacitors 51A is larger than that in embodiment 5.

(embodiment mode 6)

If the 2 nd storage capacitor 71B (corresponding to a common electrode) described in patent document 1 is a continuous film over the entire surface, potential unevenness tends to occur in a region surrounded by corners of 4 pixel electrodes 51 adjacent in the X direction and the Y direction. In the region surrounded by the corners of the 4 pixel electrodes 51 adjacent in the X direction and the Y direction, it is estimated that the amount of electric field directed to the pixel electrodes 51 is small. Therefore, in the display device 200 of embodiment 6, the common electrode 41 is formed of a conductive film, and the common electrode 41 includes a plurality of conductive film non-formation regions 41S as holes of the conductive film in a plan view. Hereinafter, the display device 200 according to embodiment 6 will be described in detail with respect to differences from the display device 200 according to embodiment 1, and description of the same configuration will be omitted.

Fig. 30 is a plan view showing a configuration example of a TFT substrate according to embodiment 6. Fig. 31 is a plan view showing a configuration example of the common electrode according to embodiment 6. The same components as those described in the present embodiment are assigned the same reference numerals, and overlapping descriptions are omitted.