阅读说明：本技术 谐波处理电路和放大电路 (Harmonic processing circuit and amplifying circuit ) 是由 须田规仁 于 2018-03-26 设计创作，主要内容包括：一种谐波处理电路(33),其包括：第一馈电线路(31),该第一馈电线路是从信号线路分支出的,所述信号线路被配置成传输要输入到放大器(4)或从放大器(4)输出的信号；以及第一设置单元(32),该第一设置单元被连接到第一馈电线路(31)并且被配置成将信号线路中的阻抗设置为信号的谐波。所述第一设置单元(32)的至少一部分由集总电路构成。(A harmonic processing circuit (33), comprising: a first feeder line (31) branching off from a signal line configured to transmit a signal to be input to the amplifier (4) or output from the amplifier (4); and a first setting unit (32) connected to the first feeding line (31) and configured to set an impedance in the signal line as a harmonic of the signal. At least a part of the first setting unit (32) is constituted by a lumped circuit.)

1. A harmonic processing circuit, comprising:

a branch line branching from a signal line configured to transmit a signal to be input to or output from an amplifier; and

a setting unit connected to the branch line and configured to set an impedance in the signal line to a harmonic of the signal,

wherein the content of the first and second substances,

at least a part of the setting unit is constituted by a lumped circuit.

2. The harmonic processing circuit of claim 1,

the branch line is a feeder line for the amplifier.

3. The harmonic processing circuit of claim 1 or 2, wherein,

the setting unit is arranged such that the branch line is open-circuited with respect to a fundamental frequency of the signal.

4. The harmonic processing circuit according to any one of claims 1 to 3, wherein,

the amplifier is housed in a single package with another amplifier.

5. The harmonic processing circuit of any of claims 1 to 4,

the setting unit includes a plurality of capacitance elements connected in parallel, an

A capacitance of a capacitive element among the plurality of capacitive elements, which is connected in a position adjacent to a voltage source for applying a voltage to the feeder line, is a capacitance that causes a short circuit with respect to the fundamental frequency of the signal.

6. The harmonic processing circuit according to any one of claims 1 to 4, wherein the setting unit includes:

a first inductive element connected to the branch line;

a second inductive element connected between the first inductive element and the voltage source for applying a voltage to the feeder line;

a first capacitive element having one end connected to a connection point between the first inductive element and the second inductive element; and

a second capacitive element having one end connected to a connection point between the second inductive element and the voltage source,

wherein the content of the first and second substances,

the inductance of the second inductive element is a value greater than the inductance of the first inductive element, an

The capacitance of the second capacitive element is a value greater than the capacitance of the first capacitive element.

7. An amplification circuit, comprising:

an amplifier;

a signal line configured to transmit a signal to be input to or output from the amplifier; and

the harmonic processing circuit of any of claims 1 to 6.

Technical Field

The invention relates to a harmonic processing circuit and an amplifying circuit.

The present application claims priority from japanese patent application No.2017-254355, filed on 28.12.2017, the entire contents of which are incorporated herein by reference.

Background

Conventionally, in order to perform harmonic processing for improving the power efficiency of an amplifier, an open stub (open stub) that adjusts the harmonic impedance to an appropriate value is generally provided on a signal line (for example, refer to patent document 1).

List of citations

[ patent document ]

Patent document 1: japanese laid-open patent application No. 2011-Busy 66839

Disclosure of Invention

A harmonic processing circuit according to one embodiment includes: a branch line branching from a signal line configured to transmit a signal to be input to or output from an amplifier; and a setting unit connected to the branch line and configured to set an impedance in the signal line to a harmonic of the signal. At least a part of the setting unit is constituted by a lumped circuit.

Drawings

Fig. 1 is a block diagram showing a configuration of a Doherty amplification circuit according to an embodiment.

Fig. 2 is a plan view of the Doherty amplification circuit.

Fig. 3 is a block diagram showing a configuration of the first harmonic processing circuit.

Fig. 4 is a smith chart showing load impedance in response to frequency changes of a signal in an amplification circuit according to an example.

Fig. 5 is a block diagram showing the configuration of the harmonic processing circuit provided on the gate terminal side.

Detailed Description

[ problem to be solved by the present disclosure ]

The size of the above-described open stub of the circuit for performing harmonic processing is determined based on the wavelength of the signal to be processed. That is, a certain size needs to be secured for the open stub, and therefore, miniaturization thereof is difficult.

The present disclosure has been made in view of the above circumstances, and an object of the present disclosure is to provide a harmonic processing circuit and an amplifying circuit that can be miniaturized.

[ advantageous effects of the present disclosure ]

According to the present disclosure, miniaturization of a harmonic processing circuit is achieved.

First, the contents of the embodiments are listed and described.

[ brief description of the embodiments ]

(1) A harmonic processing circuit according to one embodiment includes: a branch line branching from a signal line configured to transmit a signal to be input to or output from the amplifier; and a setting unit connected to the branch line and configured to set an impedance in the signal line to a harmonic of the signal. At least a part of the setting unit is constituted by a lumped circuit.

According to the harmonic processing circuit of the above configuration, since at least a part of the setting unit for setting the harmonic impedance is constituted by the lumped circuit, the size of the setting unit can be reduced as compared with the case where the harmonic processing is performed using the open stub. Therefore, miniaturization of the entire circuit can be achieved.

(2) In the above harmonic processing circuit, the branch line is preferably a feed line for an amplifier.

In this case, by using the existing feeder line as the branch line, the setting unit can be provided without adding a new line.

Therefore, even if the harmonic processing circuit is provided to the circuit having the amplifier, since the harmonic processing circuit is provided, an increase in the circuit size is suppressed.

(3) In the above-described harmonic processing circuit, the setting unit is preferably set such that the branch line is open-circuited with respect to the fundamental frequency of the signal.

In this case, the adverse effect of the setting unit on the fundamental frequency is suppressed.

(4) In the above harmonic processing circuit, the amplifier is preferably housed together with another amplifier in a single package.

In this case, since the signal line connected to the amplifier and the signal line of another amplifier are arranged adjacent to each other, the space around the signal lines is limited. Even in this case, since the harmonic processing circuit can realize miniaturization of its entirety, an appropriate arrangement can be realized even in a case where the space around the signal line is limited.

(5) In the harmonic processing circuit described above, the setting unit includes a plurality of capacitance elements connected in parallel. The capacitance of the capacitive element connected in a position adjacent to the voltage source for applying the voltage to the feeder line among the plurality of capacitive elements is a capacitance that causes a short circuit with respect to the fundamental frequency of the signal.

In this case, the high-frequency signal is prevented from leaking to the voltage source side of the feeder line.

(6) In the above harmonic processing circuit, preferably, the setting unit includes: a first inductance element connected to the branch line; a second inductive element connected between the first inductive element and a voltage source for applying a voltage to the feeder line; a first capacitive element having one end connected to a connection point between the first inductive element and the second inductive element; and a second capacitive element having one end connected to a connection point between the second inductive element and the voltage source. Preferably, the inductance of the second inductive element is a value greater than the inductance of the first inductive element, and the capacitance of the second capacitive element is a value greater than the capacitance of the first capacitive element.

In this case, the values of the respective elements may be appropriately set.

(7) An amplifying circuit according to another embodiment includes: an amplifier; and a signal line configured to transmit a signal to be input to or output from the amplifier; the harmonic processing circuit according to any one of the above (1) to (6).

[ details of the embodiment ]

Hereinafter, preferred embodiments will be described with reference to the accompanying drawings.

It should be noted that at least some portions of the embodiments described below may be combined as desired.

[ configuration of Doherty amplifying Circuit ]

Fig. 1 is a block diagram showing a configuration of a Doherty amplification circuit according to an embodiment.

The Doherty amplification circuit 1 is mounted on a wireless communication apparatus such as a base station apparatus in a mobile communication system, and amplifies a transmission signal (RF signal) having a radio frequency.

The Doherty amplification circuit 1 amplifies an RF signal (input signal) supplied to the input terminal 2 and outputs the resultant signal from the output terminal 3.

As shown in fig. 1, the Doherty amplification circuit 1 includes: a carrier amplifier 4; a peak amplifier 5 connected in parallel to the carrier amplifier 4; a dispenser 6; a combiner 7 that combines outputs from the carrier amplifier 4 and the peak amplifier 5; a carrier side input matching circuit 8; a peak side input matching circuit 9; a carrier side output matching circuit 10; and a peak side output matching circuit 11.

The distributor 6 is connected to a stage subsequent to the input terminal 2, and distributes the RF signal supplied from the input terminal 2 to the carrier amplifier 4 and the peak amplifier 5.

The output from the distributor 6 is supplied to the carrier amplifier 4 via the carrier side input matching circuit 8, and is supplied to the peak amplifier 5 via the peak side input matching circuit 9.

The carrier side input matching circuit 8 performs impedance matching with respect to the fundamental frequency between the distributor 6 side and the carrier amplifier 4 side. The peak side input matching circuit 9 performs impedance matching with respect to the fundamental frequency between the distributor 6 side and the peak amplifier 5 side.

The carrier amplifier 4 is an amplifier for continuously amplifying an input signal supplied thereto. On the other hand, the peak amplifier 5 is an amplifier for amplifying the input signal when the power of the input signal is equal to or higher than a predetermined value. Each of the carrier amplifier 4 and the peak amplifier 5 is, for example, a High Electron Mobility Transistor (HEMT) using gallium nitride (GaN).

The carrier amplifier 4 and the peak amplifier 5 are mounted on an integrated circuit and housed in a package 20.

The output from the carrier amplifier 4 is supplied to the combiner 7 via the carrier side output matching circuit 10.

The output from the peak amplifier 5 is supplied to the combiner 7 via the peak side output matching circuit 11.

The carrier side output matching circuit 10 performs impedance matching with respect to the fundamental frequency between the carrier amplifier 4 side and the combiner 7 side. The peak side output matching circuit 11 performs impedance matching with respect to the fundamental frequency between the peak amplifier 5 side and the combiner 7 side.

The combiner 7 combines the output from the carrier amplifier 4 and the output from the peak amplifier 5. The combiner 7 supplies the combined output as an output signal to the output terminal 3.

The output terminal 3 outputs the output signal supplied from the combiner 7.

Fig. 2 is a plan view of the Doherty amplification circuit 1.

As shown in fig. 2, a package 20 accommodating the amplifiers 4 and 5, the input and output terminals 2 and 3, the divider 6, the combiner 7, and the matching circuits 8, 9, 10, and 11 is mounted on a circuit board 25.

The first drain power supply 30, the second drain power supply 40, the first gate power supply 60, and the second gate power supply 70 arranged outside the circuit board 25 are connected to the Doherty amplification circuit 1.

The first drain power supply 30 is a power supply for supplying a drain voltage to be applied to the carrier amplifier 4, and is connected to a drain terminal of the carrier amplifier 4 via a first feeding line 31.

The second drain power source 40 is a power source for supplying a drain voltage to be applied to the peak amplifier 5, and is connected to the drain terminal of the peak amplifier 5 via a second feeding line 41.

The first gate power supply 60 is a power supply for supplying a gate voltage to be applied to the carrier amplifier 4, and is connected to the gate terminal of the carrier amplifier 4 via a third feeding line 61.

The second gate power supply 70 is a power supply for supplying a gate voltage to be applied to the peak amplifier 5, and is connected to the gate terminal of the peak amplifier 5 via a fourth feeding line 71.

The first setting unit 32 is connected to the first feeder line 31. The first setting unit 32 performs harmonic processing on the output from the carrier amplifier 4 to supply it to the carrier side output matching circuit 10.

The second setting unit 42 is connected to the second feeding line 41. The second setting unit 42 performs harmonic processing on the output from the peak amplifier 5 to supply it to the peak side output matching circuit 11.

The first setting unit 32 and the second setting unit 42 perform processing (harmonic processing) for adjusting the harmonic impedance of the signal in the carrier side output matching circuit 10 and the peak side output matching circuit 11 to an appropriate value, respectively.

The first feeding line 31 and the first setting unit 32 connected to the first feeding line 31 form a first harmonic processing circuit 33.

The second feeding line 41 and the second setting unit 42 connected to the second feeding line 41 form a second harmonic processing circuit 43.

Fig. 3 is a block diagram showing the configuration of the first harmonic processing circuit 33. The second harmonic processing circuit 43 has the same configuration as the first harmonic processing circuit 33. Therefore, only the first harmonic processing circuit 33 will be described hereinafter.

As shown in fig. 3, the first harmonic processing circuit 33 is configured to include a first inductive element 34, a second inductive element 35, a first capacitive element 36, and a second capacitive element 37.

These elements 34, 35, 36, and 37 are lumped elements, and the first harmonic processing circuit 33 is configured as a lumped circuit.

The first inductive element 34 and the second inductive element 35 are connected to the first feeding line 31.

One end of the first capacitive element 36 is connected to a connection point 38 between the first inductive element 34 and the second inductive element 35, and the other end thereof is grounded.

One end of the second capacitive element 37 is connected to a connection point 39 between the second inductive element 35 and the first drain power supply 30, and the other end thereof is grounded. Therefore, the first capacitive element 36 and the second capacitive element 37 are connected in parallel.

Therefore, the first harmonic processing circuit 33 is configured to include a first LC circuit 51 composed of the first inductance element 34 and the first capacitance element 36, and a second LC circuit 52 composed of the second inductance element 35 and the second capacitance element 37. That is, the first harmonic processing circuit 33 is configured by connecting two stages of LC circuits.

According to the first harmonic processing circuit 33 of the present embodiment, since at least a part of the first setting unit 32 (second setting unit 42) for setting the harmonic impedance is constituted by a lumped circuit, for example, the size of the first setting unit 32 (second setting unit 42) can be reduced as compared with the case where the harmonic processing is performed using the open stub in the aforementioned conventional art, thereby achieving miniaturization of the entire circuit.

In the present embodiment, the first setting unit 32 (second setting unit 42) is provided on the first feeder line 31 (second feeder line 41) with the first feeder line 31 (second feeder line 41) as a branch line that is branched from the carrier side output matching circuit 10 (peak side output matching circuit 11) as a signal line.

In this case, since the existing first feeder line 31 (second feeder line 41) is used as the branch line, the first setting unit 32 (second setting unit 42) can be set without adding a new line.

Therefore, even when the Doherty amplifying circuit 1 including the amplifiers 4 and 5 is provided with a harmonic processing circuit, an increase in size of the Doherty amplifying circuit 1 is suppressed due to the harmonic processing circuit.

In the present embodiment, the first setting unit 32 (second setting unit 42) is set such that the first feeder line 31 (second feeder line 41) is open-circuited with respect to the fundamental frequency of the signal in the carrier-side output matching circuit 10 (peak-side output matching circuit 11).

In this case, the adverse effect of the first setting unit 32 (second setting unit 42) on the fundamental frequency is suppressed.

In the present embodiment, the first setting unit 32 includes a plurality of (two) capacitance elements 36 and 37 connected in parallel. Among these capacitance elements 36 and 37, the second capacitance element 37 connected in a position adjacent to the first drain power supply 30 is set as a capacitance that causes a short circuit with respect to the fundamental frequency of the signal in the carrier side output matching circuit 10.

Therefore, the high-frequency signal is prevented from leaking to the voltage source side of the feeder line.

In the present embodiment, the inductance of the second inductance element 35 is set to a value larger than the inductance of the first inductance element 34, and the capacitance of the second capacitance element 37 is set to a value larger than the capacitance of the first inductance element 36.

By the setting satisfying the above-described relationship, the values of the respective elements can be appropriately set while satisfying the capacitance of the second capacitive element 37 and other conditions.

There are cases where the capacitance of the first capacitive element 36 is set to a very small value. Therefore, the first capacitive element 36 need not be connected between the first inductive element 34 and the second inductive element 35.

In the present embodiment, since both the carrier amplifier 4 and the peak amplifier 5 are accommodated in the single package 20, the carrier side output matching circuit 10 and the peak side output matching circuit 11 are arranged adjacent to each other (fig. 2), thereby limiting the space around the matching circuits 10 and 11. Even in this case, since the first harmonic processing circuit 33 of the present embodiment can realize miniaturization of its entirety, even when the space around the matching circuits 10 and 11 is limited, an appropriate arrangement can be realized.

[ examples ]

Hereinafter, an example of the harmonic processing circuit will be described.

As an example, assume an amplifying circuit including an amplifier that amplifies an RF signal having a frequency of 2.6GHz, and a harmonic processing circuit provided to a feed line of this amplifier. The load impedance of the amplifying circuit is obtained.

The harmonic processing circuit according to this example has the same configuration as the first harmonic processing circuit 33 shown in fig. 3. That is, the harmonic processing circuit includes the first inductance element 34, the second inductance element 35, the first capacitance element 36, and the second capacitance element 37, and thus connects the two-stage LC circuit.

This harmonic processing circuit is arranged to perform harmonic processing on the duplex wave having the frequency of 2.6 GHz. More specifically, the values of the respective elements are set so that the phase of duplex wave (frequency: 5.2GHz) is about 85 degrees. Note that the second capacitive element is provided as a capacitance that causes a short circuit with respect to the fundamental frequency.

Examples of the setting values of the respective elements in this example are as follows.

First inductance element: 2.2nH

A second inductance element: 3.3nH

A first capacitive element: 0.5pF

A second capacitive element: 10pF

In this case, the load impedance of the amplifier is obtained by performing simulation using a computer.

Fig. 4 is a smith chart showing load impedance in response to frequency change in a signal in an amplification circuit according to an example.

In fig. 4, the mark m1 indicates the load impedance at a frequency of 2.6 GHz. The marker m3 indicates the load impedance at a frequency of 5.2 GHz.

The load impedance of marker m1 is of the order of 0.978 and the phase is 2.433 and is substantially open.

The magnitude of the load impedance of marker m3 is 0.943 and the phase is 84.285, allowing harmonic processing to be performed almost as expected.

[ others ]

It is noted that the embodiments disclosed herein are merely exemplary in all respects, and should not be considered as limiting.

For example, although the Doherty amplification circuit 1 has been described in the above embodiment, the embodiment is also applicable to an amplification circuit using a package accommodating a single amplifier.

In the above-described embodiment, the first setting unit 32 is configured by connecting two stages of LC circuits. However, more stages, such as three-stage or four-stage LC circuits, may be connected. For example, two stages of LC circuits are connected to enable harmonic processing up to the second harmonic, and three stages of LC circuits are connected to enable harmonic processing up to the third harmonic. Therefore, the number of LC circuits to be connected is set according to the order of harmonics to be processed.

In the above embodiment, the first setting unit 32 includes the elements 34, 35, 36, and 37 respectively constituted by lumped elements. However, for example, the first inductive element 34 and the second inductive element may be used in combination with a transmission line, or may be replaced by a transmission line. In this case, each of the first inductance element 34 and the second inductance element 35 is constituted by a distributed element, and each of the first capacitance element 36 and the second capacitance element 37 is constituted by a lumped element. Therefore, in this case, at least a part of the first setting unit 32 is constituted by a lumped circuit.

In the above-described embodiment, the first harmonic processing circuit 33 and the second harmonic processing circuit 43 are provided to the first feeder line 31 connected to the drain terminal of the carrier amplifier 4 and the second feeder line 41 connected to the drain terminal of the peak amplifier 5, respectively. However, as shown in fig. 5, a setting unit 62 may be provided to the third feeding line 61 for supplying the gate voltage from the first gate power supply 60, thereby providing the harmonic processing circuit 63. The setting unit 62 has the same configuration as the first setting unit 32 of the above-described embodiment, and is configured by connecting two stages of LC circuits 64 and 65.

The same applies to the second gate power supply 70 and the harmonic processing circuit may be provided to the fourth feed line 71.

In this case, when the setting unit 62 that sets the impedance on the signal source side of the carrier amplifier 4 and the peak amplifier 5 is configured by the lumped circuit, the size of the setting unit 62 can be reduced, so that the miniaturization of the entire harmonic processing circuit 63 can be achieved. Further, miniaturization of the entire Doherty amplification circuit 1 can be achieved.

The scope of the present invention is defined by the scope of the claims, rather than the above meaning, and is intended to include the meaning equivalent to the scope of the claims and all modifications within the scope.

List of reference signs

1 Doherty amplifying circuit

2 input terminal

3 output terminal

4-carrier amplifier

5 peak amplifier

6 distributor

7 combiner

8 carrier side input matching circuit

9 peak side input matching circuit

10 carrier side output matching circuit

11 peak side output matching circuit

20 packaging

25 circuit board

30 first drain Power supply

31 first feeder line

32 first setting unit

33 first harmonic processing circuit

34 first inductance element

35 second inductive element

36 first capacitance element

37 second capacitive element

38 connection point

39 point of connection

40 second drain Power supply

41 second feeder line

42 second setting unit

43 second harmonic processing circuit

51 first LC circuit

52 second LC circuit

60 first grid power supply

61 third feeder line

62 setting unit

63 harmonic processing circuit

64. 65 LC circuit

70 second grid power supply

71 fourth feeding line