Semiconductor substrate and display device

文档序号：1377975 发布日期：2020-08-14 浏览：16次中文

阅读说明：本技术 半导体基板及显示装置 (Semiconductor substrate and display device ) 是由池田匡孝林宏宜田中仁于 2020-02-05 设计创作，主要内容包括：提供能利用多个电流路进行驱动的半导体基板和显示装置。半导体基板具备第一基材、栅极线(G)、源极线(S)、绝缘膜、第一像素电极(PE1)、以及在源极线(S)与第一像素电极(PE1)之间并联连接的第一晶体管(Tr1)和第二晶体管(Tr2)。第一晶体管(Tr1)的第一半导体层(SC1)和第二晶体管(Tr2)的第二半导体层(SC2)分别具有第一区域(R1)、第二区域(R2)以及沟道区域(RC)。第一半导体层(SC1)和第二半导体层(SC2)与第一表面接触,所述第一表面是上述绝缘膜的源极线(S)侧的面。第一半导体层(SC1)和第二半导体层(SC2)各自的沟道区域(RC)的整体与栅极线(G)重叠。(Provided are a semiconductor substrate and a display device which can be driven by a plurality of current paths. The semiconductor substrate includes a first base material, a gate line (G), a source line (S), an insulating film, a first pixel electrode (PE1), and a first transistor (Tr1) and a second transistor (Tr2) connected in parallel between the source line (S) and the first pixel electrode (PE 1). The first semiconductor layer (SC1) of the first transistor (Tr1) and the second semiconductor layer (SC2) of the second transistor (Tr2) have a first region (R1), a second region (R2), and a channel Region (RC), respectively. The first semiconductor layer (SC1) and the second semiconductor layer (SC2) are in contact with a first surface which is the source line (S) -side surface of the insulating film. The entirety of the channel Region (RC) of each of the first semiconductor layer (SC1) and the second semiconductor layer (SC2) overlaps the gate line (G).)

1. A semiconductor substrate is provided with:

a first substrate;

a gate line over the first substrate;

a source line over the first substrate;

an insulating film located above the gate line and below the source line;

a first pixel electrode over the first substrate, the gate line, and the source line; and

a first transistor and a second transistor over the first substrate and electrically connected in parallel between the source line and the first pixel electrode,

a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor each have a first region electrically connected to the source line, a second region electrically connected to the first pixel electrode, and a channel region between the first region and the second region,

the first semiconductor layer and the second semiconductor layer are in contact with a first surface which is a surface of the insulating film on the source line side,

the entirety of the channel region of each of the first semiconductor layer and the second semiconductor layer overlaps the gate line.

2. The semiconductor substrate according to claim 1,

the first semiconductor layer and the second semiconductor layer each have a long axis in a direction in which the gate line extends,

the entirety of the first semiconductor layer and the second semiconductor layer overlaps the gate line.

3. The semiconductor substrate according to claim 2,

the width of the gate line is greater than the sum of the length of the minor axis of the first semiconductor layer and the length of the minor axis of the second semiconductor layer.

4. The semiconductor substrate according to claim 3,

the first semiconductor layer and the second semiconductor layer are arranged in a width direction of the gate line.

5. The semiconductor substrate according to claim 1, further comprising:

a second pixel electrode located between the first substrate and the first pixel electrode and electrically connected to the first pixel electrode; and

a capacitance electrode between the first pixel electrode and the second pixel electrode and electrostatically capacitively coupled with the first pixel electrode and the second pixel electrode, respectively,

wherein, when viewed from above, the whole of the capacitor electrode is positioned inside the first pixel electrode and inside the second pixel electrode.

6. The semiconductor substrate according to claim 5, further comprising:

other capacitance electrodes located at positions sandwiching the gate line together with the capacitance electrodes; and

a connection wiring connecting the capacitance electrode and the other capacitance electrode,

wherein the source line crosses the gate line,

the connection wiring intersects the gate line and does not intersect the source line.

7. The semiconductor substrate according to claim 6,

the gate line and the second pixel electrode are formed of the same material and are located at the same layer,

the source line, the capacitor electrode, the other capacitor electrode, and the connection wiring are formed of the same material and located in the same layer,

the capacitor electrode, the other capacitor electrode, and the connection wiring are integrally formed.

8. The semiconductor substrate according to claim 5, further comprising:

another capacitance electrode located at a position sandwiching the source line together with the capacitance electrode; and

a connection wiring connecting the capacitance electrode and the other capacitance electrode,

wherein the source line crosses the gate line,

the connection wiring intersects the source line and does not intersect the gate line.

9. The semiconductor substrate according to claim 1, further comprising a second pixel electrode and a capacitor electrode, the second pixel electrode being located between the first base material and the first pixel electrode,

wherein the source line crosses the gate line and is located on a boundary line of the first domain and the second domain,

the second region and the channel region of the first semiconductor layer are located in the first domain,

the second region and the channel region of the second semiconductor layer are located in the second domain,

the second pixel electrode has:

a first segment located in the first domain and electrically connected to the first pixel electrode; and

a second segment located in the second domain and electrically connected to the first pixel electrode,

the capacitance electrode has:

a first capacitance electrode between the first pixel electrode and the first segment in the first domain and electrostatically capacitively coupled with the first pixel electrode and the first segment, respectively;

a second capacitance electrode between the first pixel electrode and the second section in the second domain and electrostatically capacitively coupled with the first pixel electrode and the second section, respectively; and

and a crossing electrode crossing the source line and electrically connecting the first capacitor electrode and the second capacitor electrode.

10. The semiconductor substrate according to claim 9, further comprising:

other capacitance electrodes adjacent to the first capacitance electrode;

a third capacitance electrode located adjacent to the second capacitance electrode and sandwiching the capacitance electrode together with the other capacitance electrodes;

a connection wiring for connecting the first capacitor electrode and the other capacitor electrode; and

a second connection wiring connecting the second capacitor electrode and the third capacitor electrode,

wherein the connection wiring and the other connection wiring do not intersect with the gate line and do not intersect with the source line, respectively.

11. The semiconductor substrate according to claim 1,

when the channel length and the channel width in the channel region of each of the first semiconductor layer and the second semiconductor layer are set to L and W,

W/L≤0.75。

12. the semiconductor substrate according to claim 11,

the first semiconductor layer and the second semiconductor layer are each formed using an oxide semiconductor.

13. The semiconductor substrate according to claim 1, further comprising an auxiliary gate electrode electrically connected to the gate line and sandwiching the first semiconductor layer and the second semiconductor layer together with the gate line,

wherein the auxiliary gate electrode overlaps with at least the entire channel region of both the first semiconductor layer and the second semiconductor layer in a plan view.

14. A display device is provided with:

a counter substrate including a second base material facing the first pixel electrode, and a counter electrode located between the second base material and the first pixel electrode and facing the first pixel electrode; and

a display function layer located between the first pixel electrode and the counter electrode, to which a voltage applied between the first pixel electrode and the counter electrode is applied,

the first semiconductor layer and the second semiconductor layer are in contact with a first surface which is a surface of the insulating film on the source line side,

the entirety of the channel region of each of the first semiconductor layer and the second semiconductor layer overlaps the gate line.

15. The display device according to claim 14,

the display function layer is an electrophoretic layer.

Technical Field

Embodiments of the invention relate to a semiconductor substrate and a display device.

Background

As a display device, for example, an electrophoretic display device is known. In an electrophoretic display device, a thin film transistor is used as a switching element. By increasing the channel width of the thin film transistor, the amount of current flowing through the thin film transistor can be increased.

Disclosure of Invention

The present embodiment provides a semiconductor substrate and a display device which can be driven by a plurality of current paths.

A semiconductor substrate according to one embodiment includes:

a first substrate; a gate line over the first substrate; a source line over the first substrate; an insulating film located above the gate line and below the source line; a first pixel electrode over the first substrate, the gate line, and the source line; and a first transistor and a second transistor which are located above the first substrate and electrically connected in parallel between the source line and the first pixel electrode, wherein a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor each have a first region electrically connected to the source line, a second region electrically connected to the first pixel electrode, and a channel region between the first region and the second region, the first semiconductor layer and the second semiconductor layer are in contact with a first surface, the first surface is a surface of the insulating film on the source line side, and the entire channel region of each of the first semiconductor layer and the second semiconductor layer overlaps with the gate line.

In addition, a display device according to an embodiment includes:

a semiconductor substrate, comprising: a first substrate; a gate line over the first substrate; a source line over the first substrate; an insulating film located above the gate line and below the source line; a first pixel electrode over the first substrate, the gate line, and the source line; and a first transistor and a second transistor over the first substrate and electrically connected in parallel between the source line and the first pixel electrode; a counter substrate including a second base material facing the first pixel electrode, and a counter electrode located between the second base material and the first pixel electrode and facing the first pixel electrode; and a display functional layer which is located between the first pixel electrode and the counter electrode, and to which a voltage applied between the first pixel electrode and the counter electrode is applied, wherein each of a first semiconductor layer of the first transistor and a second semiconductor layer of the second transistor has a first region electrically connected to the source line, a second region electrically connected to the first pixel electrode, and a channel region between the first region and the second region, the first semiconductor layer and the second semiconductor layer are in contact with a first surface, the first surface is a surface of the insulating film on the source line side, and the entire channel region of each of the first semiconductor layer and the second semiconductor layer overlaps with the gate line.

Drawings

Fig. 1 is a plan view showing the structure of a display device of the first embodiment.

Fig. 2 is a circuit diagram showing the above display device.

Fig. 3 is an equivalent circuit diagram showing the pixel shown in fig. 2.

Fig. 4 is a sectional view showing a display panel of the display device.

Fig. 5 is an enlarged plan view showing a part of the first substrate of the display device.

Fig. 6 is a plan view showing a part of the first substrate of fig. 5 in a further enlarged manner, and shows a gate line, a first semiconductor layer, a second semiconductor layer, a source line, a first connection electrode, a second connection electrode, and an auxiliary gate electrode.

Fig. 7 is a sectional view showing the first substrate as viewed along a line VII-VII of fig. 5.

Fig. 8 is a cross-sectional view showing the first substrate as viewed along line VIII-VIII of fig. 5.

Fig. 9 is a graph showing the results of determination and the values of W/L in the case where the channel widths and channel lengths of the respective semiconductor layers shown in fig. 6 are changed.

Fig. 10 is an enlarged plan view showing a part of the first substrate of the display device of the second embodiment.

Fig. 11 is a sectional view showing the first substrate as viewed along a line XI-XI of fig. 10.

Fig. 12 is an enlarged plan view showing a part of the first substrate of the display device of the third embodiment.

Fig. 13 is a cross-sectional view showing the first substrate as viewed along line XIII-XIII of fig. 12.

Fig. 14 is a cross-sectional view showing the first substrate as viewed along line XIV-XIV of fig. 12.

Fig. 15 is a cross-sectional view showing the first substrate as viewed along line XV-XV of fig. 12.

Fig. 16 is a sectional view showing the first base plate as viewed along line XVI-XVI of fig. 12.

Fig. 17 is an enlarged plan view showing a part of the first substrate of the display device of the fourth embodiment.

Fig. 18 is a sectional view showing the first substrate as viewed along line XVIII-XVIII of fig. 17.

Fig. 19 is an enlarged plan view showing a part of the first substrate of the display device of the fifth embodiment.

Fig. 20 is a sectional view showing the first substrate as described above, viewed along the line XX-XX of fig. 19.

Fig. 21 is a sectional view showing the first substrate as viewed along the line XXI-XXI of fig. 19.

Fig. 22 is an enlarged plan view showing a part of the first substrate of the display device of the sixth embodiment.

Fig. 23 is a sectional view showing the first substrate described above viewed along the line XXIII-XXIII of fig. 22.

Fig. 24 is an enlarged plan view showing a part of the first substrate of the display device of the seventh embodiment.

Fig. 25 is an enlarged plan view showing a part of the first substrate of the display device of the eighth embodiment.

Fig. 26 is an enlarged plan view showing a part of the first substrate of the display device of the ninth embodiment.

Fig. 27 is an enlarged plan view showing a part of a first substrate of a display device of the tenth embodiment.

Fig. 28 is an enlarged plan view showing a part of the first substrate of the display device of the eleventh embodiment.

Fig. 29 is an enlarged plan view showing a part of a first substrate of a display device of the twelfth embodiment.

Detailed Description

Embodiments of the present invention will be described below with reference to the drawings. It should be noted that the disclosure is merely an example, and appropriate modifications within the spirit of the invention, which can be easily conceived by those skilled in the art, are of course included within the scope of the invention. In addition, for the sake of clarity of explanation, the width, thickness, shape, and the like of each part are schematically shown in the drawings in comparison with the actual technical solution, but the present invention is only an example and is not limited to the explanation. In the present specification and the drawings, the same elements as those described above in the existing drawings are denoted by the same reference numerals, and detailed description thereof will be omitted as appropriate.

(first embodiment)

First, the display device DSP of the first embodiment is described in detail. Fig. 1 is a plan view showing the structure of a display device DSP according to the first embodiment.

As shown in fig. 1, in the present embodiment, the first direction X and the second direction Y are orthogonal to each other. The direction referred to herein is a direction indicated by an arrow in the drawing, and a direction reversed by 180 degrees with respect to the arrow is an opposite direction. The first direction X and the second direction Y may intersect at an angle other than 90 °. The third direction Z is orthogonal to the first direction X and the second direction Y, respectively. The third direction Z corresponds to the thickness direction of the display device DSP.

The display device DSP includes an active matrix display panel PNL, a wiring board CB, an IC chip I1, and the like. The display panel PNL includes a first substrate SUB1 and a second substrate SUB2 disposed to face the first substrate SUB 1. In this embodiment, the first substrate SUB1 is formed in a rectangular shape, and the second substrate SUB2 is formed in a rectangular shape having a smaller outer shape than the first substrate SUB 1.

In the following description, a direction from the first substrate SUB1 toward the second substrate SUB2 is referred to as an upper direction (or simply as an upper direction), and a direction from the second substrate SUB2 toward the first substrate SUB1 is referred to as a lower direction (or simply as a lower direction). In the case of the "second member above the first member" and the "second member below the first member", the second member may be in contact with the first member or may be located at a position separated from the first member. In the latter case, a third member may be interposed between the first member and the second member. The observation position of the observation display device DSP is located on the tip side of an arrow indicating the third direction Z, and observation from the observation position to an X-Y plane defined by the first direction X and the second direction Y is referred to as a plan view.

The display panel PNL includes a display area DA for displaying an image and a non-display area NDA other than the display area DA. In this embodiment, the non-display area NDA is formed in a frame shape.

Here, a band-shaped region extending in the second direction Y as a region on the left side of the display region DA in the non-display region NDA is referred to as a first region a1, a band-shaped region extending in the second direction Y as a region on the right side of the display region DA is referred to as a second region a2, a band-shaped region extending in the first direction X as a region on the lower side of the display region DA is referred to as a third region A3, and a band-shaped region extending in the first direction X as a region on the upper side of the display region DA is referred to as a fourth region a 4.

The display panel PNL includes gate drivers GD1 and GD2 and a source driver SD. The gate drivers GD1, GD2 are configured to drive gate lines described later, the gate driver GD1 is disposed in the first region a1, and the gate driver GD2 is disposed in the second region a 2. The source driver SD is configured to drive source lines described later, and is disposed in the third region a 3. The pad group is an outer wire bonding (bonding) pad group, and is disposed in the third region a 3. The pads included in the pad group are electrically connected to the gate drivers GD1 and GD2, the source driver SD, and the like.

The wiring substrate CB is physically connected to the third region A3 of the first substrate SUB1, and is electrically connected to the plurality of pads of the pad group PG. The IC chip I1 is mounted on the wiring board CB. However, unlike the present embodiment, the IC chip I1 may be mounted on a region of the third region A3 of the first substrate SUB1 that does not face the second substrate SUB 2. The IC chip I1 can apply signals to the gate drivers GD1, GD2, the source driver SD, and the like via the wiring board CB and the like.

Fig. 2 is a circuit diagram showing the display device DSP. Fig. 3 is an equivalent circuit diagram illustrating the pixel PX shown in fig. 2. In fig. 2, not all the pixels PX and all the wirings are illustrated.

As shown in fig. 2 and 3, the display panel PNL includes a first substrate 1, a plurality of pixels PX arranged in a matrix above the first substrate 1 in a display area DA, a plurality of gate lines G, a plurality of source lines S, and a plurality of capacitor lines CW.

The gate line G is connected to a gate driver GD, extends in the first direction X, and is electrically connected to a plurality of pixels PX arranged in the first direction X. The source line S is connected to the source driver SD, extends in the second direction Y, and is electrically connected to the plurality of pixels PX arranged in the second direction Y. The capacitance wiring CW extends in the first direction X or the second direction Y. In the present embodiment, the capacitance wiring CW extends in the second direction Y and is electrically connected to the plurality of pixels PX arranged in the second direction Y. A plurality of capacitance wirings CW are bundled in the non-display area NDA and connected to the IC chip I1.

The gate driver GD is configured to apply a control signal SG to the gate line G and drive the gate line G. The source driver SD is configured to apply a video signal (e.g., video signal) Vsig to the source lines S and drive the source lines S. The IC chip I1 applies a constant voltage Vpc to the capacitance wiring CW, and the capacitance wiring CW is fixed at a constant potential. Further, the IC chip I1 applies a common voltage Vcom to the counter electrode CE, and the counter electrode CE is fixed at a constant potential (common potential). In the present embodiment, the counter electrode CE is common to all the pixels PX, and thus may be referred to as a common electrode. In the present embodiment, the capacitance line CW is set to the same potential as the counter electrode CE, but may be set to a potential different from the counter electrode CE. The gate driver GD, the source driver SD, and the IC chip I1 constitute a driving section for driving the plurality of pixels PX.

Each pixel PX includes a first transistor Tr1, a second transistor Tr2, a first capacitor C1, and a second capacitor C2. The first transistor Tr1 and the second transistor Tr2 are formed of Thin Film Transistors (TFTs) of the same conductivity type, for example, a P-channel type. The semiconductor layers of the first transistor Tr1 and the second transistor Tr2 are formed of an oxide semiconductor. The semiconductor layer may be made of a semiconductor other than an oxide semiconductor such as polycrystalline silicon such as low-temperature polycrystalline silicon or amorphous silicon. Further, each of the first transistor Tr1 and the second transistor Tr2 may also be configured by a TFT of an N-channel type. The following description will be given using a transistor Tr using an oxide semiconductor.

The first transistor Tr1 and the second transistor Tr2 have a first terminal t1, a second terminal t2, and a control terminal t3, respectively. In this embodiment, the control terminal t3 functions as a gate electrode, one of the first terminal t1 and the second terminal t2 functions as a source electrode, and the other of the first terminal t1 and the second terminal t2 functions as a drain electrode. The first transistor Tr1 and the second transistor Tr2 are electrically connected in parallel between the source line S and the pixel electrode PE.

In each of the first transistor Tr1 and the second transistor Tr2, the first terminal t1 is connected to the source line S, the second terminal t2 is connected to the pixel electrode PE, and the control terminal t3 is connected to the gate line G. Thereby, the first transistor Tr1 and the second transistor Tr2 are each switched to an on state or an off state in accordance with the control signal SG applied to the gate line G. The image signal Vsig is applied to the pixel electrode PE via the source line S and the transistors Tr1, Tr2 in an on state.

The first capacitance C1 and the second capacitance C2 are capacitors. The first capacitor C1 is connected between the pixel electrode PE and the capacitor wire CW. The second capacitor C2 is connected between the pixel electrode PE and the opposite electrode CE.

Fig. 4 is a sectional view illustrating the display panel PNL. Here, a pixel PX is focused.

As shown in fig. 4, the first substrate SUB1 includes a first base 1, a base layer 10 provided on the first base 1, and a pixel electrode PE provided on the base layer 10. The second substrate SUB2 includes a second base material 2 facing the pixel electrode PE, and a counter electrode CE located between the second base material 2 and the pixel electrode PE and facing the pixel electrode PE. The counter electrode CE is formed of a transparent conductive material such as Indium Tin Oxide (ITO) or Indium Zinc Oxide (IZO).

In this embodiment, the first substrate SUB1 is a semiconductor substrate, and the second substrate SUB2 is a counter substrate. The first substrate and the second substrate 2 are formed of an insulating material such as resin or glass. In the present embodiment, the second substrate 2 is positioned on the screen side (observation side) and has light transmittance. The first base material may be opaque or transparent because it is located on the opposite side of the screen.

The display functional layer DL of the display panel PNL is located between the pixel electrode PE and the counter electrode CE. A voltage applied between the pixel electrode PE and the counter electrode CE is applied to the display functional layer DL. In this embodiment, the display device DSP is an electrophoretic display device, and the display function layer DL is an electrophoretic layer. The display function layer DL is formed of a plurality of microcapsules 30 arranged substantially without gaps in the X-Y plane.

The adhesive layer AL of the display panel PNL is located between the pixel electrode PE and the display functional layer DL.

The microcapsules 30 are, for example, spherical bodies having a particle diameter of about 20 to 70 μm. In the illustrated example, although many microcapsules 30 are arranged between one pixel electrode PE and the counter electrode CE in a proportional relationship, about 1 to 10 microcapsules 30 are arranged in a rectangular or polygonal pixel PX having one side with a length of about one hundred to several hundred μm.

The microcapsule 30 includes a dispersant 31, a plurality of black particles 32, and a plurality of white particles 33. The black particles 32 and the white particles 33 are sometimes referred to as electrophoretic particles. The outer shell (wall film) 34 of the microcapsule 30 is formed using a transparent resin such as an acrylic resin, for example. The dispersant 31 is a liquid for dispersing the black particles 32 and the white particles 33 in the microcapsule 30. The black particles 32 are particles (polymer or colloid) made of a black pigment such as aniline black, for example, and are positively charged. The white particles 33 are particles (polymer or colloid) made of a white pigment such as titanium dioxide, for example, and are negatively charged. Various additives can be added to these pigments as required. In addition, for example, pigments such as red, green, blue, yellow, cyan, magenta, and the like may be used instead of the black particles 32 and the white particles 33.

In the display functional layer DL having the above-described structure, when the pixel PX is caused to display black, the pixel electrode PE is held at a relatively higher potential than the counter electrode CE. That is, when the potential of the counter electrode CE is set to the reference potential, the pixel electrode PE is kept at the positive polarity. Thereby, the positively charged black particles 32 are drawn to the opposite electrode CE, while the negatively charged white particles 33 are drawn to the pixel electrode PE. As a result, when the pixel PX is viewed from the counter electrode CE side, black is recognized. On the other hand, when the pixel PX is to display white, the pixel electrode PE is kept negative when the potential of the counter electrode CE is set to the reference potential. Thereby, the negatively charged white particles 33 are drawn toward the counter electrode CE, while the positively charged black particles 32 are drawn toward the pixel electrode PE. As a result, when the pixel PX is observed, white is recognized.

In this embodiment, the pixel electrode PE is in contact with the adhesive layer AL. An insulating protective layer may be interposed between the pixel electrode PE and the adhesive layer AL, and the pixel electrode PE may be protected by the protective layer.

Fig. 5 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP.

As shown in fig. 5, the gate line G extends in the first direction X. The source line S extends in the second direction Y and crosses the gate line G. The pixel electrode PE has a first pixel electrode PE1 and a second pixel electrode PE2 electrically connected to each other. The gate line G and the source line S intersect the first pixel electrode PE 1. The second pixel electrode PE2 is located at a position spaced apart from the gate line G in the second direction Y.

The first semiconductor layer SC1 of the first transistor Tr1 and the second semiconductor layer SC2 of the second transistor Tr2 respectively have a first region R1 electrically connected to the source line S, a second region R2 electrically connected to the pixel electrode PE, and a channel region RC between the first region R1 and the second region R2. The entirety of the channel region RC of each of the first semiconductor layer SC1 and the second semiconductor layer SC2 overlaps the same gate line G. In this embodiment mode, the entirety of the first semiconductor layer SC1 and the entirety of the second semiconductor layer SC2 overlap the same gate line G.

The first connection electrode EL1 overlaps the gate line G at a position spaced apart from the source line S in the first direction X.

The second connection electrode EL2 extends in the second direction Y. One end portion of the second connection electrode EL2 is positioned between the source line S and the first connection electrode EL1 in the region overlapping the gate line G, and overlaps the second region R2 of each semiconductor layer SC. The other end portion of the second connection electrode EL2 overlaps the second pixel electrode PE 2.

The capacitor electrode OE is located at a position spaced apart from the semiconductor layer SC, the source line S, the first connection electrode EL1, and the second connection electrode EL2, and overlaps with the first pixel electrode PE1 and the second pixel electrode PE2, respectively. In this embodiment, the entire capacitor electrode OE is located inside the first pixel electrode PE1 and inside the second pixel electrode PE2 in a plan view.

The connection wiring NW extends in the second direction Y, intersects the gate line G, and does not intersect the source line S. The connection wiring NW connects two capacitance electrodes OE adjacent in the second direction Y with the gate line G therebetween. In this embodiment, the plurality of connection wirings NW and the plurality of capacitor electrodes OE arranged in the second direction Y are integrally formed, and the capacitor wiring CW is formed.

The auxiliary gate electrode AE overlaps with each of the semiconductor layers SC and the first connection electrode EL 1. The auxiliary gate electrode AE may overlap at least the entire channel region RC of both the first semiconductor layer SC1 and the second semiconductor layer SC2 in plan view. In this embodiment mode, the auxiliary gate electrode AE overlaps with the entirety of the first semiconductor layer SC1 and the entirety of the second semiconductor layer SC 2.

The third connection electrode EL3 is located at a position spaced apart from the auxiliary gate electrode AE and overlaps the second connection electrode EL2 and the first pixel electrode PE 1.

The gate line G and the second pixel electrode PE2 are formed of the same material. The source line S, the first connection electrode EL1, the second connection electrode EL2, the capacitor electrode OE, and the connection wiring NW are formed of the same material. The auxiliary gate electrode AE and the third connection electrode EL3 are formed of the same material. The gate line G, the second pixel electrode PE2, the source line S, the first connection electrode EL1, the second connection electrode EL2, the capacitor electrode OE, the connection wiring NW, the auxiliary gate electrode AE, and the third connection electrode EL3 are formed using a metal material such as Al (aluminum), Ti (titanium), Ag (silver), Mo (molybdenum), W (tungsten), Cu (copper), or Cr (chromium), or an alloy obtained by combining these metal materials, and may have a single-layer structure or a multi-layer structure.

Fig. 6 is a plan view showing a part of the first substrate SUB1 of fig. 5 in a further enlarged manner, and is a diagram showing the gate line G, the first semiconductor layer SC1, the second semiconductor layer SC2, the source line S, the first connection electrode EL1, the second connection electrode EL2, and the auxiliary gate electrode AE.

As shown in fig. 6, the first semiconductor layer SC1 and the second semiconductor layer SC2 have a major axis AX1 in the first direction X in which the gate line G extends and a minor axis AX2 in the second direction Y. In this embodiment mode, the first semiconductor layer SC1 and the second semiconductor layer SC2 are arranged in the width direction (second direction Y) of the gate line G. The width WI of the gate line G is greater than the sum of the length of the minor axis AX2 of the first semiconductor layer SC1 and the length of the minor axis AX2 of the second semiconductor layer SC 2.

For example, the minor axis AX2 (channel width W) of each of the first semiconductor layer SC1 and the second semiconductor layer SC2 is 1.5 μm, the width WI of the gate line G is 11 μm, and the width WI of the gate line G is set to be substantially greater than 2 times the sum of the length of the minor axis AX2 of the first semiconductor layer SC1 and the length of the minor axis of the second semiconductor layer SC 2. By making the width WI of the gate line G larger than the sum of the length of the minor axis AX2 of the first semiconductor layer SC1 and the length of the minor axis AX2 of the second semiconductor layer SC2, even when positional deviation in manufacturing occurs, the entirety of the first semiconductor layer SC1 and the second semiconductor layer SC2 can be converged to the width WI of the gate line G.

In the structure shown in fig. 6, the second connection electrode EL2 has an extension end EX that extends in the second direction Y on the opposite side of the second semiconductor layer SC2 across the first semiconductor layer SC 1. For example, when the extending end EX of the second connection electrode EL2 is located inward of the first semiconductor layer SC1 due to manufacturing positional deviation, it is expected that the characteristics originally required for the first transistor Tr1 cannot be achieved or that a difference occurs in the characteristics of the first transistor Tr1 and the second transistor Tr 2. Since the extension end portion EX of the second connection electrode EL2 has a structure extending beyond the first semiconductor layer SC1, it is possible to prevent a change in characteristics of the transistor due to a positional shift.

The channel length and the channel width in the channel region RC of each of the first semiconductor layer SC1 and the second semiconductor layer SC2 are set to L and W, respectively. In the present embodiment, W/L is preferably 0.75 or less. The relationship between the channel length (L) and the channel width (W) will be described later.

Next, a cross-sectional structure of the display panel PNL is described. Fig. 7 is a sectional view showing the first substrate SUB1 viewed along the line VII-VII of fig. 5. Fig. 8 is a sectional view showing the first substrate SUB1 viewed along the line VIII-VIII of fig. 5.

As shown in fig. 7, an insulating layer 11 is formed over the first substrate 1. A gate line G is formed over the insulating layer 11. An insulating layer 12 is formed over the insulating layer 11 and the gate line G.

The semiconductor layer SC such as the first semiconductor layer SC1 is provided on the insulating layer 12. The insulating layer 12 has a first surface 12S which is a surface on the source line S side. The semiconductor layer SC such as the first semiconductor layer SC1 is in contact with the first surface 12 s. The source line S, the first connection electrode EL1, the second connection electrode EL2, and the connection wiring NW are provided over the insulating layer 12 in which the semiconductor layer SC is formed. The source line S is located above the first region R1 of the semiconductor layer SC such as the first semiconductor layer SC1, is in contact with the first region R1, and is electrically connected to the first region R1. The second connection electrode EL2 is located above the second region R2 of the semiconductor layer SC such as the first semiconductor layer SC1, is in contact with the second region R2, and is electrically connected to the second region R2. The first connection electrode EL1 is electrically connected to the gate line G. Here, the first connection electrode EL1 is in contact with the gate line G through a contact hole CH1 formed in the insulating layer 12.

An insulating layer 13 is formed over the insulating layer 12 in which the insulating layer 12, the semiconductor layer SC, the source line S, the first connection electrode EL1, the second connection electrode EL2, and the connection wiring NW are formed. The auxiliary gate electrode AE is provided over the insulating layer 13 and is in contact with the first connection electrode EL1 through a contact hole CH2 formed in the insulating layer 13. The auxiliary gate electrode AE is electrically connected to the gate line G via the first connection electrode EL 1.

The auxiliary gate electrode AE faces at least the channel region RC of the semiconductor layer SC. The auxiliary gate electrode AE sandwiches the first semiconductor layer SC1 and the second semiconductor layer SC2 together with the gate line G. For example, in the first transistor Tr1, the gate line G and the auxiliary gate electrode AE function as gate electrodes, respectively. The first transistor Tr1 is a thin film transistor of a double gate configuration. A part of the gate line G, the first semiconductor layer SC1, the auxiliary gate electrode AE, and the like constitute the first transistor Tr 1. The second transistor Tr2 has the same cross-sectional structure as the first transistor Tr 1. The gate line G, the source line S, and the auxiliary gate electrode AE are located above the first substrate 1. The first transistor Tr1 and the second transistor Tr2 are also located above the first substrate 1.

An insulating layer 14 is formed over the insulating layer 13 and the auxiliary gate electrode AE. The insulating layer 11, the insulating layer 12, and the insulating layer 13 each correspond to an inorganic insulating layer formed using an inorganic insulating material such as silicon oxide (SiO), silicon nitride (SiN), or silicon oxynitride (SiON). The insulating layer 11, the insulating layer 12, and the insulating layer 13 may have a single-layer structure or a stacked structure. The insulating layer 14 corresponds to an organic insulating layer formed using an organic insulating material such as an acrylic resin. The base layer 10 is formed above the first substrate 1 from the insulating film 11 to the insulating layer 14.

The first pixel electrode PE1 is located above the first substrate 1, the gate line G and the source line S. In this embodiment mode, the first pixel electrode PE1 is disposed on the insulating layer 14. The first pixel electrode PE1 is formed of a laminate of a light reflecting layer FL and a transparent conductive layer TL. The light reflecting layer FL is disposed on the insulating layer 14. The light reflecting layer FL is formed of a metal material such as Al, Ti, Ag, Mo, W, Cu, or Cr, an alloy obtained by combining these metal materials, or the like, and may have a single-layer structure or a multilayer structure. The light reflecting layer FL of the present embodiment is a light reflecting conductive layer.

The transparent conductive layer TL is disposed on the insulating layer 14 and the light reflection layer FL, and is in contact with the light reflection layer FL. In this embodiment, the size of the transparent conductive layer TL is larger than that of the light reflection layer FL, and the transparent conductive layer TL completely covers the upper surface and the side surface of the light reflection layer FL. The transparent conductive layer TL is in contact with the insulating layer 14 outside the light reflecting layer FL. However, the dimensions of the light reflecting layer FL and the transparent conductive layer TL are not limited to those of the present embodiment, and various modifications are possible. For example, the size of the transparent conductive layer TL may be the same as that of the light reflection layer FL, and the transparent conductive layer TL and the light reflection layer FL may be formed to completely overlap each other. In the present embodiment, the second capacitance C2 corresponds to a capacitance formed between the first pixel electrode PE1 and the counter electrode CE.

As shown in fig. 8, the second pixel electrode PE2 is located between the first substrate 1 and the first pixel electrode PE 1. In this embodiment mode, the second pixel electrode PE2 is provided on the insulating layer 11 and covered with the insulating layer 12. The second connection electrode EL2 is provided over the insulating layer 12 and covered with the insulating layer 13. The second connection electrode EL2 is in contact with the second pixel electrode PE2 through a contact hole CH3 formed in the insulating layer 12.

The capacitance electrode OE is located between the first pixel electrode PE1 and the second pixel electrode PE 2. In this embodiment mode, the capacitor electrode OE is provided on the insulating layer 12 and covered with the insulating layer 13. The capacitance electrode OE is electrostatically capacitively coupled to the first and second pixel electrodes PE1 and PE2, respectively. The sum of the capacitance formed between the first pixel electrode PE1 and the capacitor electrode OE and the capacitance formed between the second pixel electrode PE2 and the capacitor electrode OE corresponds to the first capacitance C1.

The third connection electrode EL3 is provided over the insulating layer 13 and covered with the insulating layer 14. The third connection electrode EL3 is in contact with the second connection electrode EL2 through a contact hole CH4 formed in the insulating layer 13.

The light reflection layer FL has an opening surrounding the contact hole CH5, which is formed in the insulating layer 14, CH 5. The transparent conductive layer TL is in contact with the third connection electrode EL3 through the opening of the light reflective layer FL and the contact hole CH 5. According to the above, the second pixel electrode PE2 is electrically connected to the first pixel electrode PE1 via the second connection electrode EL2 and the third connection electrode EL 3.

As shown in fig. 5, 7 and 8, the gate line G and the second pixel electrode PE2 are formed of the same material and are located at the same layer. The source line S, the plurality of capacitor electrodes OE, the plurality of connection wirings NW, the first connection electrode EL1, and the second connection electrode EL2 are formed of the same material and are located in the same layer. The auxiliary gate electrode AE and the third connection electrode EL3 are formed of the same material and are located in the same layer.

Next, the relationship between the channel length (L) and the channel width (W) of each semiconductor layer SC will be described. Fig. 9 is a graph showing the results of determination and the values of W/L when the channel width (W) and the channel length (L) of each semiconductor layer SC shown in fig. 6 are changed. In the figure, the values of W/L are enclosed by brackets.

As shown in fig. 9, the determination is performed on each transistor Tr under the same conditions, and the result is described as a or B. In the determination, for example, the same current is caused to flow through the various transistors Tr to perform the determination. If the transistor Tr is not broken and the transistor Tr functions as a switch, it is determined as a. On the other hand, if the transistor Tr breaks and the transistor Tr does not function as a switch, the determination is made as B. It is expected that an excessive current flows in the transistor Tr, and the transistor Tr is broken due to heat generation deterioration.

For example, patent documents 3 and 4 described in the above prior art documents describe: in an electrophoresis device, a voltage for moving particles in a microcapsule needs to be a high voltage of 30V or more. Under the conditions shown in fig. 9, a high-voltage current of, for example, 30V or more is caused to flow through the gate and the source of one transistor Tr using an oxide semiconductor, and evaluation is performed.

If the value of W/L is 0.75 or less, all the results are judged as A. Therefore, the value of W/L is preferably set to 0.75 or less.

According to the display device DSP of the first embodiment configured as described above, the first substrate SUB1 includes the first base 1, the gate line G, the source line S, the first pixel electrode PE1, and the first transistor Tr1 and the second transistor Tr2 connected in parallel between the source line S and the first pixel electrode PE 1. Therefore, compared to the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel electrode PE can be driven with substantially 2 times the current while maintaining the allowable current flowing through one transistor Tr.

The semiconductor layers SC of the first transistor Tr1 and the second transistor Tr2 have a first region R1, a second region R2, and a channel region RC, respectively. The first region R1 is electrically connected to the source line S. The second region R2 is electrically connected to the first pixel electrode PE 1. The channel region RC is located between the first region R1 and the second region R2. Each semiconductor layer SC has a long axis AX1 in the direction in which the gate line G extends, and overlaps the gate line G as a whole. Therefore, for example, when it is necessary to increase the width of the gate line G in order to apply the control signal SG of a high voltage to the gate line G, the entire semiconductor layer SC can be overlapped with the gate line G.

In this way, a semiconductor substrate and a display device which can be driven by a plurality of current paths can be obtained. In the first embodiment, the first substrate SUB1 and the display device DSP capable of driving the pixel electrode PE by the first semiconductor layer SC1 and the second semiconductor layer SC2 can be obtained.

(second embodiment)

Next, a display device DSP of the second embodiment is explained. Fig. 10 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the second embodiment.

As shown in fig. 10, the display device DSP according to the second embodiment is different from the first embodiment in that the capacitor line CW extends in the first direction X. In this embodiment, the plurality of connection wirings NW and the plurality of capacitor electrodes OE arranged in the first direction X are electrically connected to form a capacitor wiring CW. The connection wiring NW does not intersect with the gate line G, but intersects with the source line S.

Each connection wiring NW is composed of a connection electrode NW1, a connection electrode NW2, and a cross electrode NW 3. The connection electrode NW1 is electrically connected to one of the capacitor electrodes OE and is located at a position spaced apart from the source line S. The connection electrode NW2 is electrically connected to the other capacitor electrode OE, and is located at a position spaced apart from the source line S. In this embodiment, the connection electrode NW1 is formed integrally with one of the capacitor electrodes OE, and the connection electrode NW2 is formed integrally with the other capacitor electrode OE.

Crossing electrode NW3 crosses source line S and overlaps connection electrode NW1 and connection electrode NW2, respectively. Regarding the width of the crossing electrode NW3 (the length in the second direction Y), the region crossing the source line S is smaller than the region overlapping the connection electrode NW1 and the connection electrode NW 2. Therefore, the load on the source line S can be reduced as compared with the case where the width of the intersecting electrode NW3 is not narrowed in the region intersecting the source line S.

Fig. 11 is a sectional view showing the first substrate SUB1 viewed along a line XI-XI of fig. 10.

As shown in fig. 11, crossing electrode NW3 is disposed on insulating layer 11. The crossover electrode NW3 and the second pixel electrode PE2 are formed of the same material in the same layer. A connection electrode NW1 and a connection electrode NW2 are disposed over the insulating layer 12. The connection electrode NW1 and the connection electrode NW2 are formed of the same material in the same layer as the capacitor electrode OE and the source line S. Connection electrode NW1 is in contact with crossover electrode NW3 through contact hole CH6 formed in insulating layer 12. Connection electrode NW2 is in contact with crossover electrode NW3 through contact hole CH7 formed in insulating layer 12.

The display device DSP according to the second embodiment configured as described above can also obtain the same effects as those of the first embodiment. The capacitance wiring CW does not cross the gate line G. Therefore, the load on the gate line G can be reduced compared to the case where the capacitive wiring CW crosses the gate line G. This can further improve the driving capability of the gate line G.

(third embodiment)

Next, a display device DSP of the third embodiment is explained. Fig. 12 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the third embodiment.

As shown in fig. 12, the display device DSP according to the third embodiment differs from the first embodiment in that the source line S extends vertically through the center of the pixel PX, the capacitor line CW extends in the first direction X, the first semiconductor layer SC1 and the second semiconductor layer SC2 are arranged and integrally formed in the first direction X, and each of the second pixel electrode PE2 and the capacitor electrode OE is divided in the first direction X. For example, the connection wiring NW and the capacitor electrode OE are formed of the same material and are located at the same layer as the capacitor electrode OE. A region overlapping the first pixel electrode PE1 is classified into a first domain DOa and a second domain DOb adjacent in the first direction X.

The second pixel electrode PE2 has a first segment SEa and a second segment SEb. The first segment SEa is located in the first domain DOa at a position spaced apart from the gate line G. The second segment SEa is located at the second domain DOb, spaced apart from each of the gate line G and the first segment SEa.

The first semiconductor layer SC1 and the second semiconductor layer SC2 are arranged in the first direction X. The second region R2 and the channel region RC of the first semiconductor layer SC1 are located in the first domain DOa. The second region R2 and the channel region RC of the second semiconductor layer SC2 are located in the second domain DOb. The first region R1 of the first semiconductor layer SC1 and the first region R1 of the second semiconductor layer SC2 are integrally formed, and overlap the source line S. In this embodiment mode, the entirety of the first semiconductor layer SC1 and the second semiconductor layer SC2 which are integrally formed overlaps the same gate line G.

The source line S intersects the gate line G and is located on a boundary line BL between the first domain DOa and the second domain DOb.

The first connection electrode EL1 is located in the first domain DOa or the second domain DOb, overlaps the gate line G, and is located at a position spaced apart from the source line S in the first direction X. In the present embodiment, the first connection electrode EL1 is located in the second region DOb.

The second connection electrode EL2a is located in the first region DOa, extends in the second direction Y, and is spaced apart from the source line S. One end portion of the second connection electrode EL2a overlaps with the second region R2 of the first semiconductor layer SC1 in a region overlapping with the gate line G. The other end portion of the second connection electrode EL2a overlaps the first segment SEa and is electrically connected to the first segment SEa.

The second connection electrode EL2b is located in the second region DOb, extends in the second direction Y, and is spaced apart from the source line S. One end portion of the second connection electrode EL2b is located between the source line S and the first connection electrode EL1 in a region overlapping the gate line G, and overlaps the second region R2 of the second semiconductor layer SC 2. The other end portion of the second connection electrode EL2b overlaps the second segment SEb and is electrically connected to the second segment SEb.

The capacitor electrode OE has a first capacitor electrode OEa, a second capacitor electrode OEb and a cross electrode OEc. The crossing electrode OEc crosses the source line S at a position spaced apart from each of the first and second segments SEa and SEb.

The first capacitor electrode OEa is positioned in the first region DOa, overlaps each of the first segment SEa, the crossing electrode OEc, and the first pixel electrode PE1, and is spaced apart from each of the second connection electrode EL2a and the source line S.

The second capacitor electrode OEb is positioned in the second region DOb, overlaps each of the second segment SEb, the crossing electrode OEc, and the first pixel electrode PE1, and is spaced apart from each of the first connection electrode EL1, the second connection electrode EL2b, and the source line S.

In the explanation of fig. 12, the capacitance electrode OE of the central pixel PX among the three pixels PX arranged in the first direction X is simply referred to as the capacitance electrode OE, the capacitance electrode OE of the left pixel PX is referred to as the other capacitance electrode OE, and the capacitance electrode OE of the right pixel PX is referred to as the third capacitance electrode OE. The other capacitive electrode OE is adjacent to the first capacitive electrode OEa of the capacitive electrode OE. The third capacitance electrode OE is adjacent to the second capacitance electrode OEb, and is located at a position where the capacitance electrode OE is sandwiched together with the other capacitance electrodes OE.

In this embodiment, a plurality of connection wirings NW and a plurality of capacitor electrodes OE arranged in the first direction X are connected to form a capacitor wiring CW.

The third connection electrode EL3 is located at a position spaced apart from the auxiliary gate electrode AE and overlaps the second connection electrode EL2a, the second connection electrode EL2b, and the first pixel electrode PE 1.

When the boundary line BL is defined as a symmetry axis, the set of the first segment SEa, the second connection electrode EL2a and the first capacitor electrode OEa is disposed substantially line-symmetrically to the set of the second segment SEa, the second connection electrode EL2b and the second capacitor electrode OEb.

Next, a cross-sectional structure of the display panel PNL is described. Fig. 13 is a sectional view showing the first substrate SUB1 viewed along a line XIII-XIII in fig. 12. Fig. 14 is a sectional view showing the first substrate SUB1 viewed along the line XIV-XIV of fig. 12. Fig. 15 is a cross-sectional view showing the first substrate SUB1 viewed along the line XV-XV of fig. 12.

As shown in fig. 13, the first semiconductor layer SC1 and the second semiconductor layer SC2 are provided over the insulating layer 12 and are integrally formed. The source line S is located above the first region R1 common to the first semiconductor layer SC1 and the second semiconductor layer SC2, is in contact with the first region R1, and is electrically connected to the first region R1. The second connection electrode EL2a is located above the second region R2 of the first semiconductor layer SC1, is in contact with the second region R2, and is electrically connected to the second region R2. The second connection electrode EL2b is located over the second region R2 of the second semiconductor layer SC2, is in contact with the second region R2, and is electrically connected to the second region R2. The insulating layer 13 covers the insulating layer 12, the source line S, the first connection electrode EL1, the second connection electrode EL2a, and the second connection electrode EL2 b.

As shown in fig. 14, the first segment SEa and the second segment SEa are disposed on the insulating layer 11 and covered by the insulating layer 12. The source line S, the second connection electrode EL2a, and the second connection electrode EL2b are provided over the insulating layer 12 and covered with the insulating layer 13.

Here, as shown in fig. 16, the second connection electrode EL2a faces the first segment SEa and contacts the first segment SEa through the contact hole CH3a formed in the insulating layer 12. The second connection electrode EL2b faces the second segment SEb, and contacts the second segment SEb through a contact hole CH3b formed in the insulating layer 12.

As shown in fig. 14, the third connection electrode EL3 is provided over the insulating layer 13 and covered with the insulating layer 14. The third connection electrode EL3 is in contact with the second connection electrode EL2a through the contact hole CH4a formed in the insulating layer 13, and is in contact with the second connection electrode EL2b through the contact hole CH4b formed in the insulating layer 13. The first pixel electrode PE1 is in contact with the third connection electrode EL3 through the contact hole CH 5. According to the above, the first segment SEa is electrically connected to the first pixel electrode PE1 via the second connection electrode EL2a and the third connection electrode EL 3. The second segment SEb is electrically connected to the first pixel electrode PE1 via the second connection electrode EL2b and the third connection electrode EL 3.

As shown in fig. 15, the first segment SEa, the second segment SEa, and the crossing electrode OEc are disposed on the insulating layer 11 and covered by the insulating layer 12. On the insulating layer 12, a first capacitance electrode OEa and a second capacitance electrode OEb are provided in addition to the source line S. The first capacitor electrode OEa is opposite to the first segment SEa and the crossing electrode OEc, and contacts the crossing electrode OEc through a contact hole CH8 formed in the insulating layer 12. The second capacitor electrode OEb is opposite to the second segment SEb and the crossing electrode OEc, and contacts the crossing electrode OEc through a contact hole CH9 formed in the insulating layer 12. According to the above, the crossing electrode OEc electrically connects the first and second capacitance electrodes OEa and OEb.

The source line S, the first capacitor electrode OEa, and the second capacitor electrode OEb are covered with the insulating layer 13. An insulating layer 14 and a first pixel electrode PE1 are sequentially disposed on the insulating layer 13. In the first domain DOa, the first capacitor electrode OEa is located between the first segment SEa and the first pixel electrode PE 1. In the second domain DOb, the second capacitor electrode OEb is located between the second segment SEb and the first pixel electrode PE 1.

The first capacitor electrode OEa is electrostatically and capacitively coupled to the first segment SEa and the first pixel electrode PE1, respectively. The second capacitive electrode OEb is electrostatically capacitively coupled to the second segment SEb and the first pixel electrode PE1, respectively. The sum of the capacitance formed between the first pixel electrode PE1 and the first capacitor electrode OEa, the capacitance formed between the first segment SEa and the first capacitor electrode OEa, the capacitance formed between the first pixel electrode PE1 and the second capacitor electrode OEb, and the capacitance formed between the first segment SEa and the second capacitor electrode OEb is equivalent to the first capacitance C1.

As shown in fig. 12 to 16, the gate line G, the first segment SEa, the second segment SEa, and the cross electrode OEc are formed of the same material and located at the same layer. The source line S, the first capacitor electrode OEa, the second capacitor electrode OEb, the connection wiring NW, the first connection electrode EL1, the second connection electrode EL2a, and the second connection electrode EL2b are formed of the same material and located in the same layer. The auxiliary gate electrode AE and the third connection electrode EL3 are formed of the same material and are located in the same layer.

The display device DSP according to the third embodiment configured as described above can also obtain the same effects as those of the second embodiment. The capacitor electrode OE is divided into a first capacitor electrode OEa and a second capacitor electrode OEb, and the second pixel electrode PE2 is divided into a first segment SEa and a second segment SEa. Since the area of the electrodes of each capacitor constituting the first capacitor C1 can be reduced as compared with the second embodiment, it is possible to prevent the capacitor breakdown due to ESD (electrostatic discharge) from occurring.

(fourth embodiment)

Next, a display device DSP of the fourth embodiment is explained. Fig. 17 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the fourth embodiment.

As shown in fig. 17, the configuration of the connection wiring NW is different from that of the first embodiment. In the present embodiment, each connection wiring NW is configured by a connection electrode NW5, a connection electrode NW6, and a cross electrode NW 7. The connection electrode NW5 is electrically connected to one of the capacitor electrodes OE and is located at a position spaced apart from the gate line G. The connection electrode NW6 is electrically connected to the other capacitance electrode OE, and is located at a position spaced apart from the gate line G. In this embodiment, the connection electrode NW5 is formed integrally with one of the capacitor electrodes OE, and the connection electrode NW6 is formed integrally with the other capacitor electrode OE. The crossing electrode NW7 crosses the gate line G and overlaps the connection electrode NW5 and the connection electrode NW6, respectively.

Fig. 18 is a sectional view showing the first base plate SUB1 viewed along the line XVIII-XVIII of fig. 17.

As shown in fig. 18, the crossing electrode NW7 is located at a layer different from the layer where each of the gate line G and the source line S is located. Crossing electrode NW7 is disposed on insulating layer 13. The crossover electrode NW7 is formed of the same material and in the same layer as the auxiliary gate electrode AE and the third connection electrode EL 3. A connection electrode NW5 and a connection electrode NW6 are disposed over the insulating layer 12. The connection electrode NW5 and the connection electrode NW6 are formed of the same material in the same layer as the capacitor electrode OE and the source line S. The crossover electrode NW7 is in contact with the connection electrode NW5 through a contact hole CH10 formed in the insulating layer 13, and is in contact with the connection electrode NW6 through a contact hole CH11 formed in the insulating layer 13.

Crossing electrode NW7 is disposed on insulating layer 13 instead of insulating layer 12. The load on the gate line G can be reduced as compared with the case where the crossover electrode NW7 is provided on the insulating layer 12.

The display device DSP according to the fourth embodiment configured as described above can also obtain the same effects as those of the first embodiment. In the manufacturing process of the first substrate SUB1, after the capacitor electrode OE, the connection electrode NW5, and the connection electrode NW6 are formed, the plurality of capacitor electrodes OE arranged in the second direction Y are electrically insulated from each other until the cross electrode NW7 is formed. Since the crossover electrode NW7 can be formed without electrically connecting the plurality of capacitor electrodes OE arranged in the second direction Y and the capacitor wiring CW can be completed, the capacitor breakdown due to ESD can be made less likely to occur.

(fifth embodiment)

Next, a display device DSP according to a fifth embodiment will be described. Fig. 19 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the fifth embodiment.

As shown in fig. 19, the display device DSP according to the fifth embodiment is different from the third embodiment in that the cross electrode OEd is provided instead of the cross electrode OEc and the configuration of the connection wiring NW is different from that of the third embodiment.

In the explanation of fig. 19, the capacitance electrode OE of the central pixel PX among the three pixels PX arranged in the first direction X is simply referred to as the capacitance electrode OE, the capacitance electrode OE of the left pixel PX is referred to as the other capacitance electrode OE, and the capacitance electrode OE of the right pixel PX is referred to as the third capacitance electrode OE. The other capacitive electrode OE is adjacent to the first capacitive electrode OEa of the capacitive electrode OE. The third capacitive electrode OE is adjacent to the second capacitive electrode OEb of the capacitive electrode OE, and is located at a position where the capacitive electrode OE is sandwiched together with the other capacitive electrodes OE.

The connection wiring NWa and the other connection wiring NWb extend in the first direction X, and do not intersect the gate line G and the source line S. The connection wiring NWa connects the first capacitance electrode OEa of the capacitance electrode OE to the other capacitance electrode OE. The connection wiring NWb connects the second capacitance electrode OEb of the capacitance electrode OE and the third capacitance electrode OE. The connection wiring NWa overlaps the first capacitance electrode OEa and the second capacitance electrode OEb of the other capacitance electrode OE, respectively. The connection wiring NWb overlaps the second capacitive electrode OEb and the first capacitive electrode OEa of the third capacitive electrode OE, respectively.

In this embodiment, a plurality of connection wirings NW and a plurality of capacitor electrodes OE arranged in the first direction X are connected to form a capacitor wiring CW.

Fig. 20 shows a cross-sectional view of the first substrate SUB1, as viewed along the line XX-XX of fig. 19.

As shown in fig. 20, interdigitated electrodes OEd are disposed on insulating layer 13 and covered by insulating layer 14. The cross electrode OEd contacts the first capacitor electrode OEa through a contact hole CH8 formed in the insulating layer 13, and contacts the second capacitor electrode OEb through a contact hole CH9 formed in the insulating layer 13. According to the above, the crossing electrode OEc electrically connects the first and second capacitance electrodes OEa and OEb.

Fig. 21 is a sectional view showing the first substrate SUB1 viewed along the line XXI-XXI of fig. 19. As shown in fig. 21, the connection wiring nwa (nw) is provided over the insulating layer 13 and covered with the insulating layer 14. The connection wiring NWa is in contact with the first capacitor electrode OEa of the capacitor electrode OE through the contact hole CH6 formed in the insulating layer 13, and is in contact with the second capacitor electrode OEb of the other capacitor electrode OE through the contact hole CH7 formed in the insulating layer 13. In this case, the connection wire NWa electrically connects the first and second capacitor electrodes OEa and OEb.

According to the above, the cross electrode OEd and the connecting wiring NW are located at a layer different from the layer where each of the gate line G and the source line S is located. The crossover electrode OEd and the connection wiring NW are formed of the same material and in the same layer as the auxiliary gate electrode AE and the third connection electrode EL 3.

In this embodiment, the plurality of connection wirings NW, the plurality of first capacitor electrodes OEa, the plurality of second capacitor electrodes OEb, and the plurality of crossing electrodes OEd arranged in the first direction X are connected to form a capacitor wiring CW.

The display device DSP according to the fifth embodiment configured as described above can also obtain the same effects as those of the third embodiment. In the manufacturing process of the first substrate SUB1, after the first and second capacitor electrodes OEa and OEb are formed, the plurality of first and second capacitor electrodes OEa and OEb arranged in the first direction X are electrically insulated from each other until the cross electrode OEd and the connection wiring NW are formed. Since the crossover electrode OEd and the connection wiring NW can be formed without electrically connecting the plurality of first capacitor electrodes OEa and the plurality of second capacitor electrodes OEb arranged in the first direction X, and the capacitor wiring CW can be completed, the capacitor breakdown due to ESD can be less likely to occur.

(sixth embodiment)

Next, a display device DSP according to a sixth embodiment will be described. Fig. 22 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the sixth embodiment.

As shown in fig. 22, the configuration of the connection wiring NW of the display device DSP according to the sixth embodiment is different from that of the fifth embodiment.

Each connection wiring NW is composed of a connection electrode NW1, a connection electrode NW2, and a cross electrode NW 3. The connection electrode NW1 extends in the first direction X, is electrically connected to the first capacitor electrode OEa of the capacitor electrode OE, and extends across the edge of the first segment SEa. The connection electrode NW2 extends in the first direction X, is electrically connected to the second capacitor electrode OEb of the other capacitor electrode OE, and extends across the edge of the second segment SEb. The connection electrode NW1 and the connection electrode NW2 each have a portion that does not overlap with the second pixel electrode PE2, and are located at positions spaced apart from each other. In this embodiment, the connection electrode NW1 is formed integrally with the first capacitor electrode OEa of the capacitor electrode OE, and the connection electrode NW2 is formed integrally with the second capacitor electrode OEb of the other capacitor electrode OE.

Fig. 23 is a sectional view showing the first substrate SUB1 viewed along the line XXIII-XXIII of fig. 22.

As shown in fig. 23, the crossover electrode NW3 is disposed on the insulating layer 11. The crossing electrode NW3 is formed of the same material as the first segment SEa, the second segment SEa, and the gate line G.

A connection electrode NW1 and a connection electrode NW2 are disposed over the insulating layer 12. The connection electrode NW1 and the connection electrode NW2 are formed of the same material in the same layer as the capacitor electrode OE and the source line S. Connection electrode NW1 is in contact with crossover electrode NW3 through contact hole CH6 formed in insulating layer 12. Connection electrode NW2 is in contact with crossover electrode NW3 through contact hole CH7 formed in insulating layer 12.

The same effects as those of the fifth embodiment can be obtained also in the display device DSP of the sixth embodiment configured as described above.

(seventh embodiment)

Next, a display device DSP of the seventh embodiment is explained. Fig. 24 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the seventh embodiment.

As shown in fig. 24, the display device DSP according to the seventh embodiment differs from the third embodiment in that it includes a cross electrode OEd instead of the cross electrode OEc.

The capacitance electrode OE has a first capacitance electrode OEa, a second capacitance electrode OEb and an intersecting electrode OEd. Crossing electrode OEd crosses source line S at a position spaced apart from each of first segment SEa and second segment SEa. The cross electrode OEd overlaps the first and second capacitance electrodes OEa and OEb, respectively. The capacitor electrode OE has the same structure as the capacitor electrode OE of the fifth embodiment (fig. 20). For example, interdigitated electrodes OEd are disposed on insulating layer 13 and covered by insulating layer 14. The intersecting electrode OEd is formed of the same material as the auxiliary gate electrode AE and the third connecting electrode EL3 in the same layer.

The same effects as those of the fifth embodiment can be obtained also in the display device DSP of the seventh embodiment configured as described above.

(eighth embodiment)

Next, a display device DSP according to an eighth embodiment will be described. Fig. 25 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the eighth embodiment.

As shown in fig. 25, the configuration of the connection wiring NW of the display device DSP according to the eighth embodiment is different from that of the third embodiment.

In the explanation of fig. 25, the capacitance electrode OE of the center pixel PX is referred to as a capacitance electrode OE, the capacitance electrode OE of the left pixel PX is referred to as another capacitance electrode OE, and the capacitance electrode OE of the right pixel PX is referred to as a third capacitance electrode OE. The other capacitive electrode OE is adjacent to the first capacitive electrode OEa of the capacitive electrode OE. The third capacitive electrode OE is adjacent to the second capacitive electrode OEb of the capacitive electrode OE, and is located at a position where the capacitive electrode OE is sandwiched together with the other capacitive electrodes OE.

In this embodiment, a plurality of connection wirings NW and a plurality of capacitor electrodes OE arranged in the first direction X are connected to form a capacitor wiring CW. The configuration of the connection wiring NW and the connection relationship between the connection wiring NW and the capacitor electrode OE are the same as those in the fifth embodiment (fig. 21). For example, the connection wiring NW is provided over the insulating layer 13 and covered with the insulating layer 14. The connection wiring NW is formed of the same material as the auxiliary gate electrode AE and the third connection electrode EL3 in the same layer.

The same effects as those of the fifth embodiment can be obtained also in the display device DSP of the eighth embodiment configured as described above.

(ninth embodiment)

Next, a display device DSP according to a ninth embodiment will be described. Fig. 26 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the ninth embodiment.

As shown in fig. 26, the configuration of the connection wiring NW of the display device DSP according to the ninth embodiment is different from that of the third embodiment.

The crossover electrode NW3 is located at a position spaced apart from the second pixel electrode PE2, and overlaps the connection electrode NW1 and the connection electrode NW2, respectively. In this embodiment, a plurality of connection wirings NW and a plurality of capacitor electrodes OE arranged in the first direction X are connected to form a capacitor wiring CW. The configuration of the connection wiring NW is the same as that of the sixth embodiment (fig. 23). For example, the connection wire NW is disposed on the insulating layer 11, and is formed of the same material and in the same layer as the first segment SEa, the second segment SEa, the gate line G, and the like.

The same effects as those of the fifth embodiment can be obtained also in the display device DSP of the ninth embodiment configured as described above.

(tenth embodiment)

Next, a display device DSP according to a tenth embodiment will be described. Fig. 27 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the tenth embodiment. The display device DSP according to the tenth embodiment is configured substantially in the same manner as the display device DSP according to the fourth embodiment (fig. 17). Hereinafter, a configuration different from that of the display device DSP according to the fourth embodiment will be described.

As shown in fig. 27, in the display device DSP according to the tenth embodiment, three transistors Tr are connected in parallel between the source line S and the pixel electrode PE.

The pixel PX is further provided with a third transistor Tr 3. The first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 of the third transistor Tr3 extend in the first direction X, and are arranged at intervals in the second direction Y. The entire channel regions RC of the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 overlap the same gate line G. In the tenth embodiment, the entirety of the first semiconductor layer SC1, the entirety of the second semiconductor layer SC2, and the entirety of the third semiconductor layer SC3 overlap the same gate line G.

Since the three semiconductor layers SC are overlapped with the same gate line G, the gate line G is partially formed to be wide. In other words, the gate line G has a protrusion PR partially protruding in the second direction Y and opposite to the second and third semiconductor layers SC2 and SC 3. The protruding portion PR is located at a position spaced apart from the second pixel electrode PE 2.

The auxiliary gate electrode AE may overlap at least the entire channel region RC of the first semiconductor layer SC1, the second semiconductor layer SC2, and the third semiconductor layer SC3 in plan view. In the tenth embodiment, the auxiliary gate electrode AE overlaps with the entirety of the first semiconductor layer SC1, the entirety of the second semiconductor layer SC2, and the entirety of the third semiconductor layer SC 3.

With the addition of the third semiconductor layer SC3, the shape of the second pixel electrode PE2, the shape of the second connection electrode EL2, the position of the third connection electrode EL3, and the like are appropriately adjusted.

The display device DSP according to the tenth embodiment configured as described above can also obtain the same effects as those of the fourth embodiment. In comparison with the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel electrode PE can be driven with a current substantially 3 times while maintaining an allowable current flowing through one transistor Tr.

(eleventh embodiment)

Next, a display device DSP according to an eleventh embodiment will be described. Fig. 28 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the eleventh embodiment. The display device DSP according to the eleventh embodiment is configured substantially in the same manner as the display device DSP according to the first embodiment (fig. 5). Hereinafter, a configuration different from that of the display device DSP according to the first embodiment will be described.

As shown in fig. 28, in the display device DSP according to the eleventh embodiment, 4 transistors Tr are connected in parallel between the source line S and the pixel electrode PE.

The pixel PX is further provided with a third transistor Tr3 and a fourth transistor Tr 4. The first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3 of the third transistor Tr3, and the fourth semiconductor layer SC4 of the fourth transistor Tr4 extend in the first direction X, and are arranged at intervals in the second direction Y. The entire channel regions RC of the first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3, and the fourth semiconductor layer SC4 overlap the same gate line G. In the eleventh embodiment, the entirety of the first semiconductor layer SC1, the entirety of the second semiconductor layer SC2, the entirety of the third semiconductor layer SC3, and the entirety of the fourth semiconductor layer SC4 overlap the same gate line G.

Since the four semiconductor layers SC are overlapped with the same gate line G, the gate line G is partially formed to be wide. In other words, the gate line G has a protrusion PR partially protruding in the second direction Y and opposite to the second, third, and fourth semiconductor layers SC2, SC3, and SC 4. The protruding portion PR is located at a position spaced apart from the second pixel electrode PE 2.

The auxiliary gate electrode AE may overlap at least the entire channel region RC of the first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3, and the fourth semiconductor layer SC4 in plan view. In the eleventh embodiment, the auxiliary gate electrode AE overlaps with the entirety of the first semiconductor layer SC1, the entirety of the second semiconductor layer SC2, the entirety of the third semiconductor layer SC3, and the entirety of the fourth semiconductor layer SC 4.

With the addition of the third semiconductor layer SC3 and the fourth semiconductor layer SC4, the shape of the second pixel electrode PE2, the shape of the second connection electrode EL2, the position of the third connection electrode EL3, and the like are appropriately adjusted.

The same effects as those of the first embodiment can be obtained also in the display device DSP of the eleventh embodiment configured as described above. In addition, compared to the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel electrode PE can be driven with substantially 4 times the current while maintaining the allowable current flowing through one transistor Tr.

(twelfth embodiment)

Next, a display device DSP according to a twelfth embodiment will be described. Fig. 29 is an enlarged plan view showing a part of the first substrate SUB1 of the display device DSP according to the twelfth embodiment. The display device DSP according to the twelfth embodiment is configured substantially in the same manner as the display device DSP according to the eleventh embodiment (fig. 28). Hereinafter, a configuration different from that of the display device DSP according to the eleventh embodiment will be described.

As shown in fig. 29, in the display device DSP according to the twelfth embodiment, five transistors Tr are connected in parallel between the source line S and the pixel electrode PE.

The pixel PX is further provided with a fifth transistor Tr 5. The first semiconductor layer SC1, the second semiconductor layer SC2, the third semiconductor layer SC3, the fourth semiconductor layer SC4, and the fifth semiconductor layer SC5 of the fifth transistor Tr5 extend in the first direction X, and are arranged at intervals in the second direction Y. The entire channel region RC of each semiconductor layer SC, such as the entire channel region RC of the fifth semiconductor layer SC5, overlaps the same gate line G. In the twelfth embodiment, the entirety of the first semiconductor layer SC1, the entirety of the second semiconductor layer SC2, the entirety of the third semiconductor layer SC3, the entirety of the fourth semiconductor layer SC4, and the entirety of the fifth semiconductor layer SC5 overlap the same gate line G.

The protruding portion PR is also opposite to the fifth semiconductor layer SC 5.

The auxiliary gate electrode AE also overlaps at least the entire channel region RC of the fifth semiconductor layer SC5 in plan view. In the twelfth embodiment, the auxiliary gate electrode AE overlaps with the entirety of the first semiconductor layer SC1, the entirety of the second semiconductor layer SC2, the entirety of the third semiconductor layer SC3, the entirety of the fourth semiconductor layer SC4, and the entirety of the fifth semiconductor layer SC 5.

The shape of the protruding portion PR and the like are appropriately adjusted in accordance with addition of the fifth semiconductor layer SC5 and the like.

The display device DSP according to the twelfth embodiment configured as described above can also obtain the same effects as those of the eleventh embodiment. In addition, compared to the case where one transistor is connected between the source line S and the first pixel electrode PE1, the pixel electrode PE can be driven with a current substantially 5 times the allowable current flowing through one transistor Tr.

Although the embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments can be implemented in other various forms, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the scope equivalent thereto. A plurality of embodiments can be combined as necessary.

For example, in the above-described embodiment, an example is shown in which two, three, four, or five transistors Tr are connected in parallel between the source line S and the pixel electrode PE. However, two or more transistors Tr may be connected in parallel between the source line S and the pixel electrode PE. Therefore, six or more transistors Tr may be connected in parallel between the source line S and the pixel electrode PE.

The transistor Tr may be formed without the auxiliary gate electrode AE.

The semiconductor layer SC may be positioned between the first substrate 1 and the gate line G. When a conductive light-shielding layer is present between the first base material 1 and the semiconductor layer SC, the light-shielding layer may be electrically connected to the gate line G and may function as an auxiliary gate electrode.

The semiconductor substrate of the above embodiment can be applied to various semiconductor substrates, and is not limited to the first substrate SUB 1.

The display device DSP according to the above embodiment can be applied to various display devices, and is not limited to the electrophoretic display device. The display device DSP may be, for example, a liquid crystal display device. In this case, the display functional layer DL is a liquid crystal layer. The liquid crystal layer may be, for example, a Polymer Dispersed Liquid Crystal (PDLC).

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