阅读说明：本技术 一种多电平逆变器拓扑结构 (Multi-level inverter topological structure ) 是由 阿拉丁·穆斯塔法·穆罕默德·哈森 李小腾 戴立宇 陈文洁 杨旭 周永兴 于 2020-05-15 设计创作，主要内容包括：本发明公开了一种多电平逆变器拓扑结构,采用两个直流电源和十个单向功率开关可以产生十三电平的输出电压波形,采用较少的开关数量,产生十三电平输出波形,而且各开关之间无干扰,连接电路简单,不需要增加输出电平需要隔离的直流电源和大容量电容器组,谐波失真率低,并且该逆变器电路在没有任何辅助充电电路的情况下为电容器提供自充电功能,可实现电荷平衡控制拓扑,本发明控制开关个数少,结构简单,成本低；且输出电平控制开关数量少,可实现多种电平输出控制,效率高且易控制。(The invention discloses a multi-level inverter topological structure, which adopts two direct current power supplies and ten unidirectional power switches to generate thirteen-level output voltage waveforms, adopts less switches to generate thirteen-level output waveforms, has no interference among the switches, has simple connecting circuits, does not need to increase the direct current power supplies and large-capacity capacitor banks of which the output levels need to be isolated, has low harmonic distortion rate, provides self-charging function for a capacitor under the condition of no auxiliary charging circuit and can realize charge balance control topology; and the output level control switches are few, can realize multiple level output control, and are efficient and easy to control.)

1. A multi-level inverter topology structure is characterized by comprising a first switch T₁A second switch T₂And a third switch T₃And a fourth switch T₄The fifth switch T₅And a sixth switch T₆Seventh switch T₇The eighth switch T₈The ninth switch T₉The tenth switch T₁₀A first capacitor C₁A second capacitor C₂A first dc power supply Vdc1 and a second dc power supply Vdc 2;

positive pole of first DC power supply Vdc1, seventh switch T₇One end of, a ninth switch T₉And a tenth switch T₁₀Is connected with one end of the connecting rod; negative pole of first direct current power supply Vdc1, sixth switch T₆One end of, a fourth switch T₄And an eighth switch T₈Is connected with one end of the connecting rod;

fourth switch T₄Another terminal of (1), a second capacitor C₂Positive pole and third switch T₃Is connected with one end of the connecting rod; second capacitor C₂Negative electrode of (1), fifth switch T₅One end of, a second switch T₂And a first switch T₁Is connected with one end of the connecting rod; a second switch T₂And the other terminal of the first capacitor C₁The positive electrode of (1) is connected;

ninth switch T₉The other end of (1), an eighth switch T₈The other end of the second direct current power supply is connected with the negative electrode of a second direct current power supply Vdc 2;

positive pole of second DC power supply Vdc2, third switch T₃The other end of (1) aTen-switch T₁₀Another terminal of (1), a first capacitor C₁Negative pole and first switch T₁The other end of the output terminal B is connected with the other end of the output terminal B; fifth switch T₅Another end of (1), a sixth switch T₆And the other end of the seventh switch T₇The other end of the input terminal is connected with the output terminal A.

2. Multilevel inverter topology according to claim 1, characterized in that the first switch T is₁A second switch T₂And a third switch T₃And a fourth switch T₄The fifth switch T₅And a sixth switch T₆Seventh switch T₇The eighth switch T₈The ninth switch T₉And a tenth switch T₁₀All are power switch tubes.

3. Multilevel inverter topology according to claim 1, characterized in that the first capacitor C₁And a second capacitor C₂Are all active capacitors.

4. The multilevel inverter topology of claim 1, wherein a plurality of multilevel inverter topologies are connected in series in sequence to form a multi-cascade circuit structure.

5. The multilevel inverter topology of claim 4, wherein the plurality of multilevel inverter topologies are symmetrically cascaded such that the number of levels in the output voltage waveform is N_levels12 × m +1, m is 1, 2, 3 … …, where m is the number of multilevel inverter topologies connected in series.

6. The multilevel inverter topology of claim 4, wherein a plurality of multilevel inverter topology asymmetric units are connected, and the number of output voltage waveform levels is N_levels2(7 × 12 × m) +1, where m is 1, 2, 3 … …, where m is the number of additional multilevel inverter topologies in series with the master cells.

Technical Field

The invention belongs to the field of power electronic research, and particularly discloses a multi-level inverter topology structure.

Background

In recent years, renewable energy has become a topic of interest due to global warming and the reduction of fossil fuels. These renewable energy systems require inverters, and multilevel inverters are favored because of their low cost, high efficiency, and good output waveform quality. These multilevel inverters may be used to inject energy conversion systems, such as fuel cells, wind turbines, etc., into the grid. Because the output voltage of the renewable energy system is low, it needs to be fed into the grid. In the multi-level inverter, the output voltage is the same as the step waveform, and the total harmonic distortion is small.

In general, conventional topologies of multilevel inverters can be divided into Diode Clamp (DCMLI), Flying Capacitor (FCMLI), and cascaded H-bridges, which are generally divided into two basic types, input dc power supply symmetry and asymmetry. However, increasing the output level in these topologies requires isolated dc power supplies and large capacitance capacitor banks. Furthermore, a charge balance control topology is required due to the voltage discharge of the capacitor. The structure is complicated, and the stability is poor.

Disclosure of Invention

The present invention is directed to a multi-level inverter topology to overcome the disadvantages of the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

a multi-level inverter topology includes a first switch T₁A second switch T₂And a third switch T₃And a fourth switch T₄The fifth switch T₅And a sixth switch T₆Seventh switch T₇The eighth switch T₈The ninth switch T₉The tenth switch T₁₀A first capacitor C₁A second capacitor C₂A first dc power supply Vdc1 and a second dc power supply Vdc 2;

positive pole of first DC power supply Vdc1, seventh switch T₇One end of, a ninth switch T₉And a tenth switch T₁₀Is connected with one end of the connecting rod; negative pole of first direct current power supply Vdc1, sixth switch T₆One end of, a fourth switch T₄And an eighth switch T₈Is connected with one end of the connecting rod;

fourth switch T₄Another terminal of (1), a second capacitor C₂Positive pole and third switch T₃Is connected with one end of the connecting rod; second capacitor C₂Negative electrode of (1), fifth switch T₅One end of, a second switch T₂And a first switch T₁Is connected with one end of the connecting rod; a second switch T₂And the other terminal of the first capacitor C₁The positive electrode of (1) is connected;

ninth switch T₉The other end of (1), an eighth switch T₈The other end of the second direct current power supply is connected with the negative electrode of a second direct current power supply Vdc 2;

positive pole of second DC power supply Vdc2, third switch T₃The other end of (1), a tenth switch T₁₀Another terminal of (1), a first capacitor C₁Negative pole and first switch T₁The other end of the output terminal B is connected with the other end of the output terminal B; fifth switch T₅Another end of (1), a sixth switch T₆And the other end of the seventh switch T₇The other end of the input terminal is connected with the output terminal A.

Further, a first switch T₁A second switch T₂And a third switch T₃And a fourth switch T₄The fifth switch T₅And a sixth switch T₆Seventh switch T₇The eighth switch T₈The ninth switch T₉And a tenth switch T₁₀All are power switch tubes.

Further, a first capacitor C₁And a second capacitor C₂Are all active capacitors.

Furthermore, a plurality of multi-level inverter topological structures are sequentially connected in series to form a multi-cascade circuit structure.

Furthermore, a plurality of multi-level inverters are symmetrically cascaded in a topological structure, so that the level number in the output voltage waveform is N_levels12 × m +1, m is 1, 2, 3 … …, where m is the number of multilevel inverter topologies connected in series.

Furthermore, a plurality of multi-level inverter topology asymmetric units are connected, and the number of output voltage waveform levels is N_levels2(7 × 12 × m) +1, where m is 1, 2, 3 … …, where m is the number of additional multilevel inverter topologies in series with the master cells.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention discloses a multi-level inverter topological structure, which adopts two direct current power supplies and ten unidirectional power switches to generate thirteen-level output voltage waveforms, adopts less switches to generate thirteen-level output waveforms, has no interference among the switches, has simple connecting circuits, does not need to increase a direct current power supply and a large-capacity capacitor bank which need to be isolated for outputting the levels, has low harmonic distortion rate, provides self-charging function for a capacitor under the condition of no auxiliary charging circuit, and can realize charge balance control topology; and the output level control switches are few, can realize multiple level output control, and are efficient and easy to control.

Furthermore, the power switch tube is adopted, so that the control of each switch is facilitated, and the level output control of the multi-level inverter topology structure is improved.

Drawings

Fig. 1 shows a thirteen-level inverter topology according to an embodiment of the present invention.

Fig. 2 is a structural schematic diagram of different operating modes of a thirteen-level boost inverting unit topology in the embodiment of the present invention.

FIG. 3 shows a capacitor charging circuit according to an embodiment of the present invention, and FIG. 3(a) shows a first capacitor C according to an embodiment of the present invention₁A charging circuit path; FIG. 3(b) shows the present inventionSecond capacitance C in the example₂And charging circuit path.

Fig. 4 is a cascade structure diagram of a multi-level inverter topology according to an embodiment of the present invention.

Fig. 5 is a thirteen-level output waveform of a thirteen-level inverter topology according to an embodiment of the present invention.

FIG. 6 is a graph of capacitor voltages of a thirteen-level inverter topology according to an embodiment of the present invention, and FIG. 6(a) is a graph of a first capacitor C of a thirteen-level inverter topology according to an embodiment of the present invention₁A voltage diagram; FIG. 6(b) is a schematic diagram of a thirteenth level inverter topology structure second capacitor C according to an embodiment of the present invention₂Voltage diagram.

Fig. 7 is a schematic diagram of output voltage and load current of a thirteen-level inverter topology according to an embodiment of the present invention.

Fig. 8 shows the output voltage of the cascaded unit of the thirteen-level inverter topology according to the embodiment of the present invention.

Fig. 9 shows the output voltage of the cascaded system based on the thirteen-level inverter topology according to the embodiment of the present invention.

Fig. 10 shows the output voltage and current of a cascaded system based on a thirteen-level inverter topology according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the accompanying drawings:

as shown in FIG. 1, the present invention relates to a multi-level inverter topology, which comprises a first switch T₁A second switch T₂And a third switch T₃And a fourth switch T₄The fifth switch T₅And a sixth switch T₆Seventh switch T₇The eighth switch T₈The ninth switch T₉The tenth switch T₁₀A first capacitor C₁A second capacitor C₂A first dc power supply Vdc1 and a second dc power supply Vdc 2;

positive pole of first DC power supply Vdc1, seventh switch T₇One end of, a ninth switch T₉And a tenth switch T₁₀Is connected with one end of the connecting rod; negative pole of first direct current power supply Vdc1, sixth switch T₆One end of (1) aFour-switch T₄And an eighth switch T₈Is connected with one end of the connecting rod;

fourth switch T₄Another terminal of (1), a second capacitor C₂Positive pole and third switch T₃Is connected with one end of the connecting rod; second capacitor C₂Negative electrode of (1), fifth switch T₅One end of, a second switch T₂And a first switch T₁Is connected with one end of the connecting rod; a second switch T₂And the other terminal of the first capacitor C₁The positive electrode of (1) is connected;

ninth switch T₉The other end of (1), an eighth switch T₈The other end of the second direct current power supply is connected with the negative electrode of a second direct current power supply Vdc 2;

positive pole of second DC power supply Vdc2, third switch T₃The other end of (1), a tenth switch T₁₀Another terminal of (1), a first capacitor C₁Negative pole and first switch T₁The other end of the output terminal B is connected with the other end of the output terminal B; fifth switch T₅Another end of (1), a sixth switch T₆And the other end of the seventh switch T₇The other end of the input terminal is connected with the output terminal A.

First switch T₁A second switch T₂And a third switch T₃And a fourth switch T₄The fifth switch T₅And a sixth switch T₆Seventh switch T₇The eighth switch T₈The ninth switch T₉And a tenth switch T₁₀All power switch tubes are favorable for controlling each switch, and the level output control of the multi-level inverter topological structure is improved; a first capacitor C₁And a second capacitor C₂All the capacitors are active capacitors, and the output of the multi-level inverter topology structure can be realized.