阅读说明：本技术 一种多电平逆变拓扑电路 (Multi-level inverter topology circuit ) 是由 阿拉丁·穆斯塔法·穆罕默德·哈森 李小腾 王睿 陈文洁 杨旭 杨洋 周永兴 于 2020-05-15 设计创作，主要内容包括：本发明公开了一种多电平逆变拓扑电路,采用H桥拓扑电路与K型逆变器拓扑电路连接,形成模块化多电平逆变拓扑电路,采用H桥拓扑电路为辅,K型逆变器拓扑电路为主连接而成,以H桥拓扑电路与K型逆变器拓扑电路分别为子模块连接,简化了电路的连接结构,同时能够通过H桥拓扑电路与K型逆变器拓扑电路开关配合,实现多电平输出,无需额外的升压电路,输出电压可达3倍率,并且有可进行级联以对输出电压和功率进行扩展,K型逆变器拓扑电路中只使用了2个电源及3个开关电容,并为电容器分别提供了互不干扰的充电环路,同时减少了产生15级输出电压所需的活跃开关数量,降低开关损耗。(The invention discloses a multi-level inverter topological circuit, which is formed by connecting an H-bridge topological circuit with a K-type inverter topological circuit to form a modular multi-level inverter topological circuit, wherein the H-bridge topological circuit is adopted as an auxiliary circuit, the K-type inverter topological circuit is mainly connected, the H-bridge topological circuit and the K-type inverter topological circuit are respectively connected as sub-modules, the connection structure of the circuit is simplified, meanwhile, multi-level output can be realized through the matching of the H-bridge topological circuit and a K-type inverter topological circuit switch, no additional booster circuit is needed, the output voltage can reach 3 multiplying power, cascade connection can be carried out to expand the output voltage and power, only 2 power sources and 3 switch capacitors are used in the K-type inverter topological circuit, non-interfering charge loops are respectively provided for the capacitors, and the number of active switches required for generating 15-level output voltage is reduced, the switching loss is reduced.)

1. A multi-level inverter topology circuit is characterized by comprising a K-type inverter topology circuit and an H-bridge topology circuit;

the K-type inverter topology circuit comprises a fifth switch unit T₅And a sixth switching unit T₆Seventh switching unit T₇The eighth switching unit T₈And a ninth switching unit T₉The tenth switching unit T₁₀Eleventh switching unit T₁₁And a twelfth switching unit T₁₂And a thirteenth switching unit T₁₃And a fourteenth switching unit T₁₄A first capacitor C₁A second capacitor C₂A third capacitor C₃And a first direct current power supply V_dc；

First DC power supply V_dcPositive electrode, fourteenth switching unit T₁₄One end, tenth switching unit T₁₀One terminal and an eleventh switching unit T₁₁One end is connected;

first DC power supply V_dcNegative electrode, thirteenth switching unit T₁₃One end, seventh switch unit T₇One end, eighth switch unit T₈One terminal and a ninth switching unit T₉One end is connected;

seventh switching unit T₇Another end of (1), a sixth switching unit T₆One terminal and a third capacitor C₃Connecting the positive electrode;

third capacitor C₃Negative electrode, twelfth switching element T₁₂One terminal and a second capacitor C₂Connecting the positive electrode; second capacitor C₂Negative pole and fifth switch unit T₅One end is connected;

tenth switching unit T₁₀The other end of the ninth switch unit T₉The other end and a first capacitor C₁Connecting the negative electrodes;

eleventh switching unit T₁₁The other end of the first capacitor C₁Positive and eighth switch unit T₈The other end, a sixth switching unit T₆The other end and a fifth switching unit T₅The other end is connected to form the output end of the K-type inverter topology circuit; twelfth switching unit T₁₂The other end, a thirteenth switching unit T₁₃The other end and a fourteenth switching unit T₁₄The other end is connected;

the H-bridge topology circuit comprises a first switch unit T₁A second switch unit T₂A third switch unit T₃A fourth switching unit T₄And a second DC power supply V_dc；

Third switch unit T₃One end, a first switch unit T₁One end and an eleventh switch unit T₁₁The other end is connected;

second DC power supply V_dcPositive electrode of (1), first switch unit T₁The other end and a second switch unit T₂One end is connected; second DC power supply V_dcNegative electrode, third switching unit T₃The other end and a fourth switching unit T₄One end is connected;

fourteenth switching unitT₁₄The other end is connected with an output end A and a second switch unit T₂The other end and a fourth switching unit T₄The other end is connected with the output end B.

2. The multi-level inverter topology circuit according to claim 1, wherein a plurality of H-bridge topology circuits are cascaded and then connected to a K-type inverter topology circuit.

3. The multi-level inverter topology circuit according to claim 2, wherein a plurality of H-bridge topology circuits are cascaded: third switching unit T of one of the H-bridge topology circuits₃Fourth switching unit T with one end connected with another H-bridge topological circuit₄The other end is connected; wherein the third switching unit T of one H-bridge topology circuit at one end of the H-bridge topology circuit cascade circuit₃One end and an eleventh switch unit T₁₁The other end is connected; the fourth switching unit T of the H-bridge topology circuit at the other end of the H-bridge topology circuit cascade circuit₄The other end is connected with the output end B.

4. The multilevel inverter topology circuit according to claim 1, wherein a plurality of K-type inverter topology circuits are cascaded and then connected to an H-bridge topology circuit.

5. The multi-level inverter topology circuit according to claim 4, wherein a plurality of K-type inverter topology circuits are cascaded: fourteenth switching unit T of one of the K-type inverter topology circuits₁₄The other end of the eleventh switching unit T is connected with another K-type inverter topology circuit₁₁The other end; the fourteenth switching unit T of one K-type inverter topology circuit at one end in the K-type inverter topology circuit cascade circuit₁₄The other end of the eleventh switch unit T is connected with the output end A, and the eleventh switch unit T of the K-type inverter topology circuit at the other end in the K-type inverter topology circuit cascade circuit₁₁The other end is connected with a third switch unit T₃And the other end.

Technical Field

The invention belongs to the technical field of power electronics, and particularly relates to a multi-level inverter topology circuit.

Background

Recently, multilevel inverters (MLI) have attracted considerable attention in the DC-AC converter family, especially in applications in the industrial field in the high power range. MLI can significantly reduce Total Harmonic Distortion (THD) of the output voltage while also limiting electromagnetic interference (EMI), and in addition, the use of multiple output levels can also reduce voltage stress on the switches and switching losses, thus it is of great help to improve system efficiency. Multilevel power conversion is rapidly developing and widely used in the field of power engineering for applications such as medium voltage ac drives, flexible ac transmission system (FACTS) devices, and High Voltage Direct Current (HVDC) transmission systems. Based on the existing research, the more inverter output voltage levels means that the output is closer to a smooth sinusoidal waveform, the harmonic content is less, and the generation of multiple levels currently generally needs more direct-current voltage source coordination, which complicates the module topology and even introduces an unstable factor.

Disclosure of Invention

The invention aims to provide a multi-level inverter topology circuit to overcome the defects of the prior art.

In order to achieve the purpose, the invention adopts the following technical scheme:

a multi-level inverter topology circuit, a K-type inverter topology circuit and an H-bridge topology circuit;

k-type inverter topology circuit packageA fifth switch unit T₅And a sixth switching unit T₆Seventh switching unit T₇The eighth switching unit T₈And a ninth switching unit T₉The tenth switching unit T₁₀Eleventh switching unit T₁₁And a twelfth switching unit T₁₂And a thirteenth switching unit T₁₃And a fourteenth switching unit T₁₄A first capacitor C₁A second capacitor C₂A third capacitor C₃And a first direct current power supply V_dc；

First DC power supply V_dcPositive electrode, fourteenth switching unit T₁₄One end, tenth switching unit T₁₀One terminal and an eleventh switching unit T₁₁One end is connected;

first DC power supply V_dcNegative electrode, thirteenth switching unit T₁₃One end, seventh switch unit T₇One end, eighth switch unit T₈One terminal and a ninth switching unit T₉One end is connected;

seventh switching unit T₇Another end of (1), a sixth switching unit T₆One terminal and a third capacitor C₃Connecting the positive electrode;

third capacitor C₃Negative electrode, twelfth switching element T₁₂One terminal and a second capacitor C₂Connecting the positive electrode; second capacitor C₂Negative pole and fifth switch unit T₅One end is connected;

tenth switching unit T₁₀The other end of the ninth switch unit T₉The other end and a first capacitor C₁Connecting the negative electrodes;

eleventh switching unit T₁₁The other end of the first capacitor C₁Positive and eighth switch unit T₈The other end, a sixth switching unit T₆The other end and a fifth switching unit T₅The other end is connected to form the output end of the K-type inverter topology circuit; twelfth switching unit T₁₂The other end, a thirteenth switching unit T₁₃The other end and a fourteenth switching unit T₁₄The other end is connected;

the H-bridge topology circuit comprises a first switch unit T₁The second switch sheetYuan T₂A third switch unit T₃A fourth switching unit T₄And a second DC power supply V_dc；

Third switch unit T₃One end, a first switch unit T₁One end and an eleventh switch unit T₁₁The other end is connected;

second DC power supply V_dcPositive electrode of (1), first switch unit T₁The other end and a second switch unit T₂One end is connected; second DC power supply V_dcNegative electrode, third switching unit T₃The other end and a fourth switching unit T₄One end is connected;

fourteenth switching unit T₁₄The other end is connected with an output end A and a second switch unit T₂The other end and a fourth switching unit T₄The other end is connected with the output end B.

Furthermore, a plurality of H-bridge topology circuits are connected with a K-type inverter topology circuit after being cascaded.

Further, a plurality of H-bridge topology circuits are cascaded: third switching unit T of one of the H-bridge topology circuits₃Fourth switching unit T with one end connected with another H-bridge topological circuit₄The other end is connected; wherein the third switching unit T of one H-bridge topology circuit at one end of the H-bridge topology circuit cascade circuit₃One end and an eleventh switch unit T₁₁The other end is connected; the fourth switching unit T of the H-bridge topology circuit at the other end of the H-bridge topology circuit cascade circuit₄The other end is connected with the output end B.

Furthermore, a plurality of K-type inverter topology circuits are connected with an H-bridge topology circuit after being cascaded.

Further, a plurality of K-type inverter topology circuits are cascaded: fourteenth switching unit T of one of the K-type inverter topology circuits₁₄The other end of the eleventh switching unit T is connected with another K-type inverter topology circuit₁₁The other end; the fourteenth switching unit T of one K-type inverter topology circuit at one end in the K-type inverter topology circuit cascade circuit₁₄The other end of the K-type inverter topology circuit cascade circuit is connected with an output end A, and a K-type inverter at the other end of the K-type inverter topology circuit cascade circuitEleventh switching unit T of the inverter topology circuit₁₁The other end is connected with a third switch unit T₃And the other end.

Compared with the prior art, the invention has the following beneficial technical effects:

the invention relates to a multi-level inverter topological circuit, which is formed by connecting an H-bridge topological circuit with a K-type inverter topological circuit to form a modular multi-level inverter topological circuit, wherein the H-bridge topological circuit is used as an auxiliary circuit, the K-type inverter topological circuit is used as a main circuit, the H-bridge topological circuit and the K-type inverter topological circuit are respectively connected as sub-modules, the connection structure of the circuit is simplified, meanwhile, multi-level output can be realized through the matching of the H-bridge topological circuit and a K-type inverter topological circuit switch, no additional booster circuit is needed, the output voltage can reach 3 multiplying powers, and the multi-level inverter topological circuit can be cascaded to expand the output voltage and power, only 2 power sources and 3 switch capacitors are used in the K-type inverter topological circuit, non-interfering charging loops are respectively provided for the capacitors, and the number of active switches required for generating 15-level output voltage is reduced, the switching loss is reduced.

Drawings

FIG. 1 is a schematic circuit topology according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of different switch states of an inverter topology, and FIG. 2(i) is a circuit diagram of a circuit forming 0.5V_dcAn output path; FIG. 2(ii) shows the formation of-0.5V_dcAn output path; FIG. 2(iii) shows the formation of 1V_dcAn output path; FIG. 2(iv) is a diagram of formation of-V_dcAn output path; FIG. 2(V) is a graph showing 1.5V_dcAn output path; FIG. 2(vi) shows the formation of-1.5V_dcAn output path; FIG. 2(vii) is a schematic view showing 2V formation_dcAn output path; FIG. 2(viii) is a diagram showing the formation of-2V_dcAn output path; FIG. 2(ix) shows 2.5V formation_dcAn output path; FIG. 2(x) is a graph showing formation of-2.5V_dcAn output path; FIG. 2(xi) is a diagram of forming 3V_dcAn output path; FIG. 2(xii) is a diagram of formation of-3V_dcAn output path; FIG. 2(xiii) is for forming 3.5V_dcAn output path; FIG. 2(xiv) is a diagram forming-3.5V_dcAnd (4) an output channel.

Fig. 3 is a circuit diagram of a cascade circuit in an embodiment of the present invention, fig. 3(a) is a circuit diagram of a cascade circuit in an H-bridge topology, and fig. 3(b) is a circuit diagram of a cascade circuit in a K-type inverter topology.

Fig. 4 shows the 15-level output voltage and load current in the simulation environment of the embodiment of the present invention.

Fig. 5 shows output voltages of H-bridge and K-type inverter sub-modules in a simulation environment according to an embodiment of the present invention.

FIG. 6 shows the voltage variation of the capacitor according to the embodiment of the present invention.

Fig. 7 is a graph of harmonic components of a single stage output voltage in an embodiment of the invention.

Fig. 8 shows the output voltage and the load current of the cascade system in an embodiment of the invention.

Fig. 9 shows the output voltages of different sub-modules in the cascade system according to an embodiment of the present invention.

FIG. 10 shows harmonic components of the output voltage of the cascade system in accordance with an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the accompanying drawings:

as shown in fig. 1, a multi-level inverter topology circuit includes 2 power supplies and 14 power switches and 3 symmetrical chargeable capacitors; the 2 power supplies comprise a first DC power supply V_dcAnd a second DC power supply V_dc(ii) a The 14 power switches include a first switching unit T₁A second switch unit T₂A third switch unit T₃A fourth switching unit T₄A fifth switching unit T₅And a sixth switching unit T₆Seventh switching unit T₇The eighth switching unit T₈And a ninth switching unit T₉The tenth switching unit T₁₀Eleventh switching unit T₁₁And a twelfth switching unit T₁₂And a thirteenth switching unit T₁₃And a fourteenth switching unit T₁₄(ii) a The 3 symmetrical chargeable capacitors comprise a first capacitor C₁A second capacitor C₂And a third capacitance C₃；

First DC power supply V_dcPositive electrode, fourteenth switching unit T₁₄One end, tenth switching unit T₁₀One end and eleventh switch unitT₁₁One end is connected;

first DC power supply V_dcNegative electrode, thirteenth switching unit T₁₃One end, seventh switch unit T₇One end, eighth switch unit T₈One terminal and a ninth switching unit T₉One end is connected;

seventh switching unit T₇Another end of (1), a sixth switching unit T₆One terminal and a third capacitor C₃Connecting the positive electrode;

third capacitor C₃Negative electrode, twelfth switching element T₁₂One terminal and a second capacitor C₂Connecting the positive electrode; second capacitor C₂Negative pole and fifth switch unit T₅One end is connected;

tenth switching unit T₁₀The other end of the ninth switch unit T₉The other end and a first capacitor C₁Connecting the negative electrodes;

eleventh switching unit T₁₁The other end of the first capacitor C₁Positive and eighth switch unit T₈The other end, a sixth switching unit T₆The other end, a fifth switch unit T₅The other end, a third switching unit T₃One terminal and a first switching unit T₁One end is connected;

second DC power supply V_dcPositive electrode of (1), first switch unit T₁The other end and a second switch unit T₂One end is connected; second DC power supply V_dcNegative electrode, third switching unit T₃The other end and a fourth switching unit T₄One end is connected;

twelfth switching unit T₁₂The other end, a thirteenth switching unit T₁₃The other end and a fourteenth switching unit T₁₄The other end is connected with the output end A; second switch unit T₂The other end and a fourth switching unit T₄The other end is connected with the output end B.