阅读说明：本技术 半导体装置 (Semiconductor device with a plurality of semiconductor chips ) 是由 和泉正人 于 2019-01-07 设计创作，主要内容包括：实施方式的半导体装置具备第1导电型的第1半导体层、第2导电型的第2半导体层和第2导电型的第3半导体层。第2半导体层及第3半导体层设置在第1半导体层上。第2半导体层具有将其一部分有选择地除去的凹槽部和将其包围的外缘部。第3半导体层在沿着第2半导体层的凹槽部与第1半导体层之间的第1边界的第1方向上与第2半导体层隔开配置。与第1边界交叉的第2方向上的第1边界附近的第2导电型杂质分布、和外缘部与第1半导体层之间的第2边界附近处的第2方向上的第2导电型杂质分布大致相同,第2边界附近处的第2方向上的第2导电型杂质分布和第1半导体层与第3半导体层之间的第3边界附近处的第2方向的第2导电型杂质分布大致相同。(The semiconductor device of the embodiment includes a 1 st semiconductor layer of a 1 st conductivity type, a 2 nd semiconductor layer of a 2 nd conductivity type, and a 3 rd semiconductor layer of a 2 nd conductivity type. The 2 nd semiconductor layer and the 3 rd semiconductor layer are provided on the 1 st semiconductor layer. The 2 nd semiconductor layer has a recessed portion where a part thereof is selectively removed and an outer edge portion surrounding the recessed portion. The 3 rd semiconductor layer is spaced apart from the 2 nd semiconductor layer in a 1 st direction along a 1 st boundary between the groove portion of the 2 nd semiconductor layer and the 1 st semiconductor layer. The impurity distribution of the 2 nd conductivity type in the vicinity of the 1 st boundary in the 2 nd direction intersecting the 1 st boundary is substantially the same as the impurity distribution of the 2 nd conductivity type in the 2 nd direction in the vicinity of the 2 nd boundary between the outer edge portion and the 1 st semiconductor layer, and the impurity distribution of the 2 nd conductivity type in the 2 nd direction in the vicinity of the 2 nd boundary is substantially the same as the impurity distribution of the 2 nd conductivity type in the 2 nd direction in the vicinity of the 3 rd boundary between the 1 st semiconductor layer and the 3 rd semiconductor layer.)

1. A semiconductor device is characterized in that a semiconductor element,

the disclosed device is provided with:

a 1 st semiconductor layer of a 1 st conductivity type;

a 2 nd semiconductor layer of a 2 nd conductivity type provided on the 1 st semiconductor layer, the 2 nd semiconductor layer having a groove portion provided inside the 2 nd semiconductor layer and an outer edge portion surrounding the groove portion; and

a 3 rd semiconductor layer of a 2 nd conductivity type provided on the 1 st semiconductor layer and disposed apart from the 2 nd semiconductor layer in a 1 st direction, the 1 st direction being a direction along a 1 st boundary between the 1 st semiconductor layer and the groove portion of the 2 nd semiconductor layer;

the 2 nd semiconductor layer has a 1 st distribution of the 2 nd conductive type impurity in the vicinity of the 1 st boundary and a 2 nd distribution of the 2 nd conductive type impurity in the vicinity of the 2 nd boundary between the outer edge portion of the 2 nd semiconductor layer and the 1 st semiconductor layer, the 1 st and 2 nd distributions being defined in a 2 nd direction intersecting the 1 st boundary, the 1 st distribution being substantially the same as the 2 nd distribution;

the 3 rd semiconductor layer has a 3 rd distribution of the impurity of the 2 nd conductivity type in the vicinity of a 3 rd boundary between the 1 st semiconductor layer and the 3 rd semiconductor layer, and the 3 rd distribution is defined in the 2 nd direction and is substantially the same as the 2 nd distribution.

2. The semiconductor device according to claim 1,

further provided with:

a 1 st electrode electrically connected to the recessed portion of the 2 nd semiconductor layer; and

and a contact layer disposed between the recess portion and the 1 st electrode, and including a 2 nd conductive type impurity at a higher concentration than the 2 nd conductive type impurity in the recess portion.

3. The semiconductor device according to claim 2,

a plurality of contact layers are arranged along the boundary between the groove part and the 1 st electrode;

the plurality of contact layers are arranged to be spaced apart from each other.

4. The semiconductor device according to claim 1,

the 2 nd semiconductor layer has a plurality of the groove portions.

5. The semiconductor device according to claim 4,

the semiconductor device further includes a 1 st electrode, the 1 st electrode being provided so as to cover a surface of the 2 nd semiconductor layer other than the outer edge portion, and being electrically connected to the plurality of groove portions.

6. The semiconductor device according to claim 1,

the 2 nd semiconductor layer has an island-shaped convex portion surrounded by the recessed portion.

7. The semiconductor device according to claim 6,

the island-shaped convex portion has an upper surface positioned at the same level as the upper surface of the outer edge portion.

8. The semiconductor device according to claim 6,

the semiconductor device further includes a 1 st electrode which covers the recessed portion and the island-shaped convex portion and is electrically connected to the recessed portion and the island-shaped convex portion.

9. The semiconductor device according to claim 8,

a contact layer provided between the recess portion and the electrode, the contact layer containing a 2 nd conductive type impurity at a higher concentration than the 2 nd conductive type impurity in the recess portion;

the contact layer is not provided between the island-shaped projections and the electrode.

10. The semiconductor device according to claim 2,

further provided with:

a 2 nd electrode electrically connected to the 1 st semiconductor layer;

a 3 rd electrode electrically connected to the 3 rd semiconductor layer;

a part of the 1 st semiconductor layer and the 2 nd semiconductor layer are located between the 1 st electrode and the 2 nd electrode;

the other part of the 1 st semiconductor layer and the 3 rd semiconductor layer are located between the 3 rd electrode and the 2 nd electrode.

11. The semiconductor device according to claim 10,

a 4 th semiconductor layer of the 1 st conductivity type, the 4 th semiconductor layer being provided between the 1 st semiconductor layer and the 2 nd electrode, the 4 th semiconductor layer containing a 1 st conductivity type impurity at a higher concentration than the 1 st conductivity type impurity of the 1 st semiconductor layer;

the 2 nd electrode is electrically connected to the 4 th semiconductor layer;

the 1 st semiconductor layer is electrically connected to the 2 nd electrode via the 4 th semiconductor layer.

12. A semiconductor device is characterized in that a semiconductor element,

the disclosed device is provided with:

a 1 st semiconductor layer of a 1 st conductivity type; and

a 2 nd semiconductor layer of a 2 nd conductivity type provided on the 1 st semiconductor layer, the 2 nd semiconductor layer having a groove portion provided inside the 2 nd semiconductor layer and an outer edge portion surrounding the groove portion;

the recessed portion includes a 1 st portion and a 2 nd portion, the 1 st portion and the 2 nd portion being in contact with the 1 st semiconductor layer;

the 2 nd portion contains a 2 nd conductive type impurity at a lower concentration than the 2 nd conductive type impurity of the 1 st portion;

the 1 st portion and the 2 nd portion are arranged along a 1 st direction, the 1 st direction being a direction along a 1 st boundary between the 1 st semiconductor layer and the 1 st portion;

the 2 nd semiconductor layer has a 1 st distribution of the 2 nd conductive type impurity in the vicinity of the 1 st boundary and a 2 nd distribution of the 2 nd conductive type impurity in the vicinity of the 2 nd boundary between the outer edge portion of the 2 nd semiconductor layer and the 1 st semiconductor layer, the 1 st distribution and the 2 nd distribution being defined in a 2 nd direction intersecting the 1 st boundary, the 1 st distribution being substantially the same as the 2 nd distribution.

13. The semiconductor device according to claim 12,

a 3 rd semiconductor layer of a 2 nd conductivity type, the 3 rd semiconductor layer being provided on the 1 st semiconductor layer and being disposed apart from the 2 nd semiconductor layer in the 1 st direction;

the 3 rd semiconductor layer has a 3 rd distribution of the 2 nd conductive type impurity in the vicinity of a 3 rd boundary between the 1 st semiconductor layer and the 3 rd semiconductor layer, and the 3 rd distribution is defined in the 2 nd direction and is substantially the same as the 2 nd distribution of the 2 nd conductive type impurity.

14. The semiconductor device according to claim 12,

further provided with:

a 1 st electrode electrically connected to the recess portion; and

and a contact layer disposed between the 1 st portion of the recess portion and the 1 st electrode, and including a 2 nd conductive type impurity at a higher concentration than the 2 nd conductive type impurity in the 1 st portion of the recess portion.

15. A semiconductor device is characterized in that a semiconductor element,

the disclosed device is provided with:

a 1 st semiconductor layer of a 1 st conductivity type; and

a 2 nd semiconductor layer of a 2 nd conductivity type provided on the 1 st semiconductor layer, the 2 nd semiconductor layer having a 1 st region, a 2 nd region adjacent to the 1 st region, and an outer edge portion surrounding the 1 st region and the 2 nd region;

the 1 st region and the 2 nd region are arranged in a 1 st direction, the 1 st direction being a direction along a boundary between the 1 st semiconductor layer and the 1 st region;

the 1 st region includes a groove portion from which a part is selectively removed;

the 2 nd region includes a 2 nd conductive type impurity at a lower concentration than the 2 nd conductive type impurity at the outer edge portion.

16. The semiconductor device according to claim 15,

the 2 nd semiconductor layer has a 1 st distribution of the 2 nd conductive type impurity in the vicinity of a 1 st boundary between the 1 st semiconductor layer and the 1 st region, and a 2 nd distribution of the 2 nd conductive type impurity in the vicinity of a 2 nd boundary between the outer edge portion and the 1 st semiconductor layer, the 1 st distribution and the 2 nd distribution being defined in a 2 nd direction intersecting the 1 st boundary, the 1 st distribution being substantially the same as the 2 nd distribution.

17. The semiconductor device according to claim 16,

further provided with:

a 1 st electrode electrically connected to the 1 st region and the 2 nd region; and

and a contact layer provided between the 1 st electrode and the 1 st region, the contact layer containing a 2 nd conductive type impurity at a higher concentration than the 2 nd conductive type impurity in the 1 st region.

18. The semiconductor device according to claim 16,

a 3 rd semiconductor layer of a 2 nd conductivity type, the 3 rd semiconductor layer being provided on the 1 st semiconductor layer and being disposed apart from the 2 nd semiconductor layer in the 1 st direction;

the 3 rd semiconductor layer has a 3 rd distribution of the impurity of the 2 nd conductivity type in the vicinity of a 3 rd boundary between the 1 st semiconductor layer and the 3 rd semiconductor layer, and the 3 rd distribution is defined in the 2 nd direction and is substantially the same as the 2 nd distribution.

Technical Field

The present invention relates to a semiconductor device.

Background

A semiconductor device used for power control includes, for example, a P-type semiconductor layer, an N-type semiconductor layer, and a low concentration layer having a low impurity concentration, i.e., an Intrinsic layer (I-layer) or a drift layer, disposed therebetween. In the semiconductor device having such a structure, for example, if the amount of holes injected into the low concentration layer from the P-type semiconductor layer increases, the on-resistance decreases, but the switching speed from the on state to the off state decreases. Therefore, in order to reduce the on-resistance and increase the switching speed, it is important to appropriately control the amount of holes injected into the low-concentration layer.

Disclosure of Invention

The invention provides a semiconductor device capable of improving breakdown tolerance by controlling carrier injection into a low concentration layer.

A semiconductor device according to the present invention includes a 1 st semiconductor layer of a 1 st conductivity type, a 2 nd semiconductor layer of a 2 nd conductivity type, and a 3 rd semiconductor layer of a 2 nd conductivity type. The 2 nd semiconductor layer and the 3 rd semiconductor layer are provided on the 1 st semiconductor layer. The 2 nd semiconductor layer has a recessed portion in which a part of the semiconductor layer is selectively removed and an outer edge portion surrounding the recessed portion. The 3 rd semiconductor layer is spaced apart from the 2 nd semiconductor layer in a 1 st direction, and the 1 st direction is a direction along a 1 st boundary between the groove portion of the 2 nd semiconductor layer and the 1 st semiconductor layer. A 2 nd conductivity type impurity distribution in the vicinity of the 1 st boundary in a 2 nd direction intersecting the 1 st boundary is substantially the same as a 2 nd conductivity type impurity distribution in the 2 nd direction in the vicinity of a 2 nd boundary between the outer edge portion and the 1 st semiconductor layer, and the 2 nd conductivity type impurity distribution in the 2 nd direction in the vicinity of the 2 nd boundary is substantially the same as a 2 nd conductivity type impurity distribution in the 2 nd direction in the vicinity of a 3 rd boundary between the 1 st semiconductor layer and the 3 rd semiconductor layer.

Drawings

Fig. 1 is a schematic cross-sectional view showing a semiconductor device according to embodiment 1.

Fig. 2 is a schematic plan view showing a semiconductor device according to embodiment 1.

Fig. 3 (a) and 3 (b) are schematic diagrams showing impurity distributions of the semiconductor device according to embodiment 1.

Fig. 4 is a schematic cross-sectional view showing a semiconductor device according to modification 1 of embodiment 1.

Fig. 5 is a schematic cross-sectional view showing a semiconductor device according to modification 2 of embodiment 1.

Fig. 6 is a schematic cross-sectional view showing a semiconductor device according to modification 3 of embodiment 1.

Fig. 7 (a) and 7 (b) are schematic plan views showing a semiconductor device according to a 3 rd modification of embodiment 1.

Fig. 8 is a schematic cross-sectional view showing a semiconductor device according to a 4 th modification of embodiment 1.

Fig. 9 is a schematic cross-sectional view showing a semiconductor device according to embodiment 2.

Fig. 10 is a schematic plan view showing a semiconductor device according to embodiment 2.

Fig. 11 is a schematic cross-sectional view showing a semiconductor device according to modification 1 of embodiment 2.

Fig. 12 is a schematic cross-sectional view showing a semiconductor device according to modification 2 of embodiment 2.

Fig. 13 is a schematic plan view showing a semiconductor device according to modification 2 of embodiment 2.

Fig. 14 is a schematic cross-sectional view showing a semiconductor device according to modification 3 of embodiment 2.

Detailed Description

Hereinafter, embodiments will be described with reference to the drawings. The same reference numerals are given to the same portions in the drawings, and detailed description thereof will be omitted as appropriate, and different portions will be described. The drawings are schematic or conceptual, and the relationship between the thickness and the width of each portion, the ratio of the sizes of the portions, and the like are not necessarily the same as those in reality. Even when the same portions are shown, the sizes and ratios thereof are shown differently from each other in the drawing.

Further, the arrangement and structure of each part will be described using the X, Y, and Z axes shown in the drawings. The X, Y and Z axes are orthogonal to each other and respectively represent the X, Y and Z directions. In some cases, the Z direction is described as being upward and the opposite direction is described as being downward.

(embodiment 1)

Fig. 1 is a schematic cross-sectional view showing a semiconductor device 1 according to embodiment 1.

Fig. 2 is a schematic plan view showing a semiconductor device 1 according to embodiment 1. Fig. 1 is a schematic view showing a cross section along the line a-a shown in fig. 2.

The semiconductor device 1 is, for example, an FRD (Fast Recovery Diode).

As shown in fig. 1, the semiconductor device 1 includes an N-type cathode layer 10, an I layer 20, and a P-type anode layer 30. The I layer 20 is disposed between the N-type cathode layer 10 and the P-type anode layer 30. The I layer 20 is, for example, an N-type semiconductor layer containing N-type impurities at a lower concentration than the N-type cathode layer 10.

The N-type cathode layer 10 is, for example, an N-type silicon substrate. Further, the I layer 20 is, for example, an N-type silicon layer epitaxially grown on an N-type silicon substrate. The P-type anode layer 30 is, for example, a P-type diffusion layer selectively formed in an N-type silicon layer.

The P-type anode layer 30 includes a groove portion 31 and an outer edge portion 33. The groove 31 is a portion having a thickness in the Z direction smaller than the outer edge 33 of the P-type anode layer 30 (the same applies hereinafter). The groove portion 31 is formed by selectively removing a portion of the P-type anode layer 30. The thickness of the groove portion 31 in the Z direction is thinner than the thickness of the outer edge portion 33 in the Z direction. As shown in fig. 2, outer edge portion 33 is disposed so as to surround groove portion 31, for example.

The semiconductor device 1 further includes a guard ring layer 40. The guard ring layer 40 is, for example, a P-type semiconductor layer, and is formed simultaneously with the P-type anode layer 30. Further, the guard ring layer 40 is provided so as to be spaced apart from the P-type anode layer 30 in a direction (for example, X direction, Y direction) along the boundary of the I layer 20 and the groove portion 31. As shown in fig. 2, the guard ring layer 40 is provided so as to surround the P-type anode layer 30.

The semiconductor device 1 further includes a cathode electrode 50, an anode electrode 60, and a guard ring electrode 70. The cathode electrode 50 is provided on the back surface side of the N-type cathode layer 10, and is connected to the N-type cathode layer 10. The anode electrode 60 is disposed on the groove 31, for example, and connected to the P-type anode layer 30. The guard ring electrode 70 is connected to the guard ring layer 40.

The semiconductor device 1 further includes an insulating film 45 and a passivation film 75.

The insulating film 45 is provided so as to cover the outer edge 33 of the P-type anode layer 30, the inner edge of the grommet layer 40, and the I layer 20 exposed between the P-type anode layer 30 and the grommet layer 40. The insulating film 45 is, for example, a silicon oxide film. The passivation film 75 is provided so as to cover a part of the anode electrode 60, the insulating film 45, and the guard ring electrode 70. The passivation film 75 is, for example, an insulating resin film.

Fig. 3 (a) and 3 (b) are schematic diagrams showing impurity distributions of the semiconductor device 1 according to embodiment 1. Fig. 3 (a) is a schematic diagram showing impurity distributions in the outer edge portion 33 of the P-type anode layer 30 and the guard ring layer 40. Fig. 3 (b) is a schematic diagram showing the impurity distribution in the groove portion 31 of the P-type anode layer 30.

"NI" and "PI" shown in fig. 3 (a) and 3 (b) respectively indicate concentration distributions of the N-type impurity and the P-type impurity. Further, "LB" represents a boundary between the I layer 20 and the P-type anode layer 30, or a boundary between the I layer 20 and the grommet layer 40.

The P-type anode layer 30 and the guard ring layer 40 are formed simultaneously. The P-type anode layer 30 and the guard ring layer 40 are formed by, for example, selectively ion-implanting P-type impurities into a silicon layer and then diffusing the P-type impurities by heat treatment. Thus, the P-type anode layer 30 and the guard ring layer 40 are formed so that the P-type impurity distribution in the depth direction (-Z direction) is substantially the same.

The peak concentration Pmax of the P-type impurity shown in fig. 3 (a) is, for example, 1 × 10¹⁸cm^－3The above. In addition, the concentration of the N-type impurity in the I layer 20 is, for example, 1 × 10¹⁷cm^－3The following.

As shown in fig. 3 (b), the groove portion 31 is formed by selectively removing (recessing) a part of the P-type anode layer 30. In the groove portion 31, a high concentration region of the P-type impurity in the P-type anode layer 30 is removed, but the distribution of the P-type impurity in the vicinity of the boundary between the I layer 20 and the P-type anode layer 30 is maintained.

That is, the P-type impurity distribution near the boundary between the I layer 20 and the P-type anode layer 30 in the groove portion 31 and the P-type impurity distribution near the boundary between the I layer 20 and the P-type anode layer 30 in the outer edge portion 33 are substantially the same. Further, the P-type impurity distribution near the boundary between the I layer 20 and the P-type anode layer 30 in the groove portion 31 is also substantially the same as the P-type impurity distribution near the boundary between the I layer 20 and the guard ring layer 40.

Further, the amount of P-type impurities in the groove portion 31 depends on the depth in the-Z direction from the level of the upper surface of the outer edge portion 33 to the upper surface of the groove portion 31 (hereinafter referred to as a groove amount LA). For example, if the groove amount LA is increased, the amount of P-type impurities decreases, and if the groove amount LA is decreased, the amount of P-type impurities increases. That is, the amount of holes injected from the P-type anode layer 30 to the I layer 20 when the semiconductor device 1 is biased in the forward direction can be controlled by the recess amount LA.

In this embodiment, by controlling the recess amount LA, the hole injection amount from the P-type anode layer 30 to the I layer 20 can be appropriately set, and the on-resistance and the switching speed can be optimized according to the application of the semiconductor device 1.

Further, in the semiconductor device 1, the damage tolerance of the outer peripheral portion, i.e., the so-called terminal portion, of the P-type anode layer 30 can be improved. For example, the terminal portion preferably maintains a tolerance amount capable of blocking a current 2 to 3 times the rated current. The failure mode at such a current level includes a mode in which the material is melted by joule heat and a mode in which the material is broken by electric field concentration. In contrast, by making the depth and cross section of the P-type diffusion layer constituting the outer edge portion 33 of the P-type anode layer 30 and the guard ring layer 40 uniform, the amount of damage resistance at the end portion can be improved.

In the present embodiment, by forming the P-type anode layer 30 and the guard ring layer 40 at the same time, it is possible to obtain substantially the same P-type impurity distribution in the outer edge portion 33 and the guard ring layer 40. Further, the cross section of the P-type diffusion layer is kept thicker in the-Z direction in the outer edge portion 33 and the guard ring layer 40 than in the groove portion 31. This can improve the damage tolerance in the end region of the semiconductor device 1. That is, in the semiconductor device 1, the on-resistance and the switching speed can be optimized while securing the breakdown resistance amount.

Fig. 4 is a schematic cross-sectional view showing a semiconductor device 2 according to modification 1 of embodiment 1. The semiconductor device 2 has a planar arrangement of a P-type anode layer 30 and a guard ring layer 40 as shown in fig. 2. Fig. 4 is a schematic view showing a cross section along the line a-a shown in fig. 2.

As shown in fig. 4, the semiconductor device 2 further includes a P-type contact layer 35. The P-type contact layer 35 is disposed between the groove portion 31 of the P-type anode layer 30 and the anode electrode 60. P-type contact layer 35 contains P-type impurities at a higher concentration than the peak concentration of P-type impurities in groove portion 31 (see fig. 3 (b)). This enables, for example, ohmic contact to be formed between the P-type contact layer 35 and the anode electrode 60.

The P-type contact layer 35 is formed by ion-implanting P-type impurities into the surface layer of the groove portion 31, for example. At this time, the implantation energy is set to be low to obtain the distribution of the P-type impurity having a high peak concentration at a low doping amount. Further, the P-type impurity is activated by a short-time heat treatment. This can suppress the diffusion of P-type impurities, and can make P-type contact layer 35 shallow. The P-type contact layer 35 is formed, for example, to have a thickness in the Z direction smaller than that of the groove portion 31.

Such P-type contact layer 35 is formed to contain P-type impurities at a high concentration without greatly increasing the amount of P-type impurities between I layer 20 and anode electrode 60. In this example, the hole injection amount from the P-type anode layer 30 to the I-layer 20 can also be made appropriate by controlling the recess amount LA.

Fig. 5 is a schematic cross-sectional view showing a semiconductor device 3 according to modification 2 of embodiment 1. The semiconductor device 3 has a planar arrangement of a P-type anode layer 30 and a guard ring layer 40 as shown in fig. 2. Fig. 5 is a schematic view showing a cross section along the line a-a shown in fig. 2.

As shown in fig. 5, the semiconductor device 3 includes a P-type contact layer 37. The P-type contact layer 37 is disposed between the groove portion 31 of the P-type anode layer 30 and the anode electrode 60. The P-type contact layer 37 is formed to include a plurality of regions spaced apart from each other. P-type contact layer 37 is formed, for example, by the same method as P-type contact layer 35 (see fig. 4), and contains P-type impurities at a higher concentration than the peak concentration of P-type impurities in groove portion 31 (see fig. 3 b). The P-type contact layer 37 is formed, for example, to have a thickness in the Z direction smaller than that of the groove portion 31.

In the semiconductor device 3, the P-type contact layer 37 is formed to include a plurality of regions spaced apart from each other, whereby an increase in the amount of P-type impurities between the I layer 20 and the anode electrode 60 can be suppressed as compared with the semiconductor device 2. In this example, an ohmic contact can be formed between the P-type contact layer 37 and the anode electrode 60. Further, by controlling the recess amount LA, the hole injection amount from the P-type anode layer 30 to the I-layer 20 can be optimized.

Fig. 6, fig. 7 (a) and fig. 7 (b) are schematic views showing a semiconductor device 4 according to a 3 rd modification of embodiment 1. Fig. 6 is a schematic view showing a cross section along the line B-B shown in fig. 7 (a) or the line C-C shown in fig. 7 (B). Fig. 7 (a) and 7 (b) are schematic plan views showing the arrangement of the P-type anode layer 30 and the guard ring layer 40 of the semiconductor device 4.

As shown in fig. 6, P-type anode layer 30 of semiconductor device 4 includes groove portions 31, protruding portions 32, and outer edge portions 33. The groove portion 31 is formed by selectively removing a portion of the P-type anode layer 30. The convex portions 32 remain between the regions where the P-type anode layer 30 is selectively removed.

As shown in fig. 7 (a), a plurality of groove portions 31 are formed in the P-type anode layer 30. Convex portions 32 remain between adjacent groove portions 31. Outer edge 33 is provided so as to surround recessed portion 31 and projecting portion 32.

As shown in fig. 7 (b), semiconductor device 4 may have a structure in which a plurality of protruding portions 32 remain in an island shape inside groove portions 31 formed in P-type anode layer 30.

As shown in fig. 6, anode electrode 60 of semiconductor device 4 is provided so as to cover recessed portion 31 and protruding portion 32. Anode electrode 60 is in contact with recessed portion 31 and protruding portion 32. The convex portion 32 has a distribution of P-type impurities as shown in fig. 3 (a), for example. Therefore, in the semiconductor device 4, ohmic contact can be obtained between the anode electrode 60 and the upper surface of the convex portion 32.

In this example, the amount of holes injected from P-type anode layer 30 into I layer 20 can be optimized by controlling the area ratio of recessed portions 31 to protruding portions 32 in addition to recessed amount LA (see fig. 3 (b)) corresponding to recessed portions 31.

Fig. 8 is a schematic cross-sectional view showing a semiconductor device 5 according to a 4 th modification of embodiment 1. The semiconductor device 5 has a planar arrangement of the P-type anode layer 30 and the guard ring layer 40 shown in fig. 7 (a) or 7 (b). Fig. 8 is a schematic view showing a cross section along the line B-B shown in fig. 7 (a) or the line C-C shown in fig. 7 (B).

As shown in fig. 8, the semiconductor device 5 further includes a P-type contact layer 39. The P-type contact layer 39 is disposed between the groove portion 31 of the P-type anode layer 30 and the anode electrode 60. P-type contact layer 39 contains P-type impurities at a higher concentration than the peak concentration of P-type impurities in groove portion 31 (see fig. 3 (b)). This enables ohmic contact to be formed between P-type contact layer 39 and anode electrode 60, in addition to the upper surface of projection 32. Further, P-type contact layer 39 is formed to have a thickness in the Z direction thinner than that of recessed portion 31 so that the amount of P-type impurities between I layer 20 and anode electrode 60 is not greatly increased.

(embodiment 2)

Fig. 9 and 10 are schematic views showing a semiconductor device 6 according to embodiment 2.

Fig. 9 is a schematic view showing a cross section along the line D-D shown in fig. 10. Fig. 10 is a schematic plan view showing the arrangement of the P-type anode layer 30 and the guard ring layer 40 of the semiconductor device 6.

As shown in fig. 9 and 10, P-type anode layer 30 of semiconductor device 6 has groove 31 and outer edge 33. The groove portion 31 includes a 1 st area 31a and a 2 nd area 31 b. The 1 st region 31a contains P-type impurities at a higher concentration than the 2 nd region 31 b.

In this embodiment, the outer edge 33 of the P-type anode layer 30 and the guard ring layer 40 also have the P-type impurity profile shown in fig. 3 (a). In contrast, the 1 st region 31a has a P-type impurity profile shown in fig. 3 (b). The Z-direction P-type impurity distribution near the boundary between the 1 st region 31a and the I layer 20 is substantially the same as the Z-direction P-type impurity distribution near the boundary between the outer edge 33 and the I layer 20.

The 2 nd region 31b has a P-type impurity distribution with a lower concentration than the P-type impurity distribution shown in fig. 3 (b). Thus, for example, in the semiconductor device 6, the amount of holes injected from the P-type anode layer 30 into the I-layer 20 can be suppressed as compared with the semiconductor device 1. Further, by controlling the groove amount LA (see fig. 3 (b)) corresponding to the groove portion 31, the amount of holes injected into the I layer 20 can be optimized in a wider range.

The P-type anode layer 30 is formed by, for example, selectively ion-implanting a P-type impurity into an N-type semiconductor layer having a low impurity concentration as the I layer 20, and then diffusing the P-type impurity by heat treatment. The doping amount of the P-type impurity implanted into the 1 st region 31a and the outer edge 33 is set to be larger than the doping amount of the P-type impurity implanted into the 2 nd region 31 b. In this embodiment, the guard ring layer 40 is also formed simultaneously with the P-type anode layer 30. In the P-type anode layer 30, after the P-type impurity is diffused, a part of the P-type diffusion layer is selectively removed.

Fig. 11 is a schematic cross-sectional view showing a semiconductor device 7 according to modification 1 of embodiment 2. The semiconductor device 7 has a planar arrangement of a P-type anode layer 30 and a guard ring layer 40 as shown in fig. 10. Fig. 11 is a schematic view showing a cross section along the line D-D shown in fig. 10.

As shown in fig. 11, the semiconductor device 7 further includes a P-type contact layer 83. The P-type contact layer 83 is disposed between the 1 st region 31a of the P-type anode layer 30 and the anode electrode 60. The P-type contact layer 83 contains P-type impurities at a concentration higher than the peak concentration of P-type impurities in the 1 st region 31a (see fig. 3 (b)). Thereby, ohmic contact can be formed between the P-type contact layer 83 and the anode electrode 60. The P-type contact layer 83 is formed, for example, to have a thickness in the Z direction smaller than that of the groove portion 31.

Fig. 12 and 13 are schematic views showing a semiconductor device 8 according to a 2 nd modification of embodiment 2. Fig. 12 is a schematic view showing a cross section along the line E-E shown in fig. 13. Fig. 13 is a schematic plan view showing the arrangement of the P-type anode layer 30 and the guard ring layer 40 of the semiconductor device 8.

As shown in fig. 12 and 13, P-type anode layer 30 of semiconductor device 8 has groove 31, outer edge 33, and low concentration portion 85. The recessed portion 31 is formed by selectively removing a part of the P-type diffusion layer having substantially the same P-type impurity profile as the outer edge portion 33. Low concentration portion 85 contains a lower concentration of P-type impurities than groove portion 31.

As shown in fig. 13, groove portion 31 is configured to be island-shaped, and low-concentration portion 85 is provided so as to surround groove portion 31. The outer edge portion 33 is provided so as to surround the low concentration portion 85. The guard ring layer 40 is provided so as to surround the P-type anode layer 30.

In this embodiment, the outer edge 33 of the P-type anode layer 30 and the guard ring layer 40 have the P-type impurity profile shown in fig. 3 (a). In contrast, the groove portion 31 has a P-type impurity distribution shown in fig. 3 (b). The Z-direction P-type impurity distribution near the boundary of the groove portion 31 and the I layer 20 is substantially the same as the Z-direction P-type impurity distribution near the boundary of the outer edge portion 33 and the I layer 20.

The low concentration portion 85 has a P-type impurity distribution having a lower concentration than the P-type impurity distribution shown in fig. 3 (b). This can suppress the amount of holes injected from the P-type anode layer 30 into the I-layer 20 in the semiconductor device 8. Further, by controlling the groove amount LA (see fig. 3 (b)) corresponding to the groove portion 31, the amount of holes injected into the I layer 20 can be optimized.

Fig. 14 is a schematic cross-sectional view showing a semiconductor device 9 according to modification 3 of embodiment 2. The semiconductor device 9 has a planar arrangement of a P-type anode layer 30 and a guard ring layer 40 as shown in fig. 13. Fig. 14 is a schematic view showing a cross section along the line E-E shown in fig. 13.

As shown in fig. 14, the semiconductor device 9 further includes a P-type contact layer 87. The P-type contact layer 87 is disposed between the groove portion 31 of the P-type anode layer 30 and the anode electrode 60. P-type contact layer 87 contains P-type impurities at a higher concentration than the peak concentration of P-type impurities in groove portion 31 (see fig. 3 (b)). Thereby, ohmic contact can be formed between the P-type contact layer 87 and the anode electrode 60. The P-type contact layer 87 is formed to have a thickness in the Z direction smaller than that of the groove portion 31, for example.

In the above embodiment, by providing the groove portion 31 in which a part of the P-type diffusion layer constituting the P-type anode layer 30 is selectively removed, hole injection into the I layer 20 is suppressed, and the switching speed from the on state to the off state is increased. Meanwhile, by forming the outer edge portion 33 of the P-type anode layer 30 and the guard ring layer 40 to have substantially the same P-type impurity distribution, the amount of damage tolerance in the end portion can be improved.

In addition, when the contact resistance between the P-type anode layer 30 and the anode electrode 60 is increased due to selective removal of a part of the P-type diffusion layer, the contact resistance can be reduced by appropriately disposing the P-type contact layers 35, 37, 39, 83, and 87 between the groove portion 31 and the anode electrode 60. In the ion implantation of the P-type impurity, each P-type contact layer is formed, for example, under conditions of low energy and low doping amount, and is formed using heat treatment conditions capable of suppressing diffusion of the P-type impurity.

Although the semiconductor devices according to embodiments 1 and 2 have been described above, the embodiments are not limited to these. For example, in the above structure, the conductivity type may be inverted. The planar arrangements of the P-type anode layer 30 and the guard ring layer 40 shown in fig. 2, 7 (a), 7 (b), 10, and 13 are examples, and are not limited to these. For example, the P-type anode layer 30 may have a structure having a plurality of groove portions 31 formed in a stripe shape.

Some embodiments of the present invention have been described, but these embodiments are presented as examples and are not intended to limit the scope of the invention. These new embodiments may be implemented in other various forms, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalent scope thereof.