阅读说明：本技术 一种含埋层结构的碳化硅PiN二极管 (Silicon carbide PiN diode containing buried layer structure ) 是由 王帅 张有润 罗佳敏 钟炜 罗茂久 于 2019-11-28 设计创作，主要内容包括：一种含埋层结构的碳化硅PiN二极管,包括从下至上依次设置的阴极、N型碳化硅衬底、N型碳化硅外延层、P型区和金属阳极,N型碳化硅外延层内还设置有N型埋层和/或P型埋层,N型埋层位于N型碳化硅衬底上方,用于增强N型碳化硅衬底与N型碳化硅外延层边界处的电场；P型埋层位于P型区下方,用于增强P型区与N型碳化硅外延层边界处的电场。本发明通过引入P型埋层增强P型区与N型碳化硅外延层边界处的电场,通过引入N型埋层增强N型碳化硅衬底与N型碳化硅外延层边界处的电场,增强了电导调制的效果,提高了碳化硅PiN二极管正向导通电流,提高了碳化硅PiN二极管的正向导通性能。(A silicon carbide PiN diode with a buried layer structure comprises a cathode, an N-type silicon carbide substrate, an N-type silicon carbide epitaxial layer, a P-type region and a metal anode which are sequentially arranged from bottom to top, wherein the N-type buried layer and/or the P-type buried layer are/is further arranged in the N-type silicon carbide epitaxial layer and located above the N-type silicon carbide substrate and used for enhancing an electric field at the boundary of the N-type silicon carbide substrate and the N-type silicon carbide epitaxial layer; the P-type buried layer is positioned below the P-type region and used for enhancing an electric field at the boundary of the P-type region and the N-type silicon carbide epitaxial layer. According to the invention, the electric field at the boundary of the P-type region and the N-type silicon carbide epitaxial layer is enhanced by introducing the P-type buried layer, and the electric field at the boundary of the N-type silicon carbide substrate and the N-type silicon carbide epitaxial layer is enhanced by introducing the N-type buried layer, so that the effect of conductivity modulation is enhanced, the forward conduction current of the silicon carbide Pin diode is improved, and the forward conduction performance of the silicon carbide Pin diode is improved.)

1. A silicon carbide PiN diode with a buried layer structure comprises a cathode, an N-type silicon carbide substrate, an N-type silicon carbide epitaxial layer, a P-type region and a metal anode which are sequentially arranged from bottom to top;

the silicon carbide epitaxial layer is characterized in that an N-type buried layer and/or a P-type buried layer are/is further arranged in the N-type silicon carbide epitaxial layer, and the N-type buried layer is positioned above the N-type silicon carbide substrate and used for enhancing an electric field at the boundary of the N-type silicon carbide substrate and the N-type silicon carbide epitaxial layer; the P-type buried layer is located below the P-type region and used for enhancing an electric field at the boundary of the P-type region and the N-type silicon carbide epitaxial layer.

2. The PiN diode of silicon carbide containing a buried layer structure as claimed in claim 1, wherein a distance between a lower surface of the N-type buried layer and an upper surface of the N-type silicon carbide substrate is not more than 2 μm, and a distance between an upper surface of the P-type buried layer and a lower surface of the P-type region is not more than 2 μm.

3. The PiN diode of silicon carbide containing buried layer structure as claimed in claim 1, wherein the distance between the upper surface of the P-type buried layer and the lower surface of the P-type region is 1 μm, and the doping concentration of the P-type buried layer is 10¹⁸cm^-3(ii) a The distance between the lower surface of the N-type buried layer and the upper surface of the N-type silicon carbide substrate is 1 mu m, and the doping concentration of the N-type buried layer is 10¹⁸cm^-3。

4. The buried-structure-containing silicon carbide PiN diode as claimed in claim 3, wherein the doping concentration of the P-type region is 10¹⁹cm^-3The thickness is 1 μm; the doping concentration of the N-type silicon carbide substrate is 10¹⁹cm^-3(ii) a The thickness of the N-type silicon carbide epitaxial layer is 30 mu m, and the doping concentration is 3 multiplied by 10¹⁵cm^-3。

5. The PiN diode of silicon carbide containing a buried layer structure as claimed in any one of claims 1 to 4, wherein said P-type buried layer and N-type buried layer are formed by means of ion implantation and said P-type region is formed by means of epitaxy.

Technical Field

The invention belongs to the technical field of power semiconductor devices, and relates to a silicon carbide PiN diode with a buried layer structure.

Background

The wide-bandgap semiconductor material silicon carbide (SiC) has the advantages of wide bandgap, high critical breakdown electric field, high thermal conductivity, high electronic saturation rate, good thermal stability and the like, and is an ideal material for manufacturing semiconductor devices in high-temperature, high-voltage, high-frequency, high-power and strong-irradiation environments. Under the same conditions, the silicon carbide PiN diode has higher breakdown voltage and lower on-state resistance than the silicon PiN diode. The improvement of the performance of the silicon carbide Pin diode is derived from the excellent material characteristics: the drift region of the silicon carbide PiN diode can be made thinner by the high-critical breakdown electric field, and the doping is correspondingly larger, so that the forward on-resistance is reduced, and the switching speed is increased; the silicon carbide has excellent thermal conductivity, so that heat generated in the working process of the silicon carbide PiN diode can be diffused more quickly, and higher power density can be obtained at the same junction temperature; the large forbidden band width of silicon carbide enables the junction leakage current of the silicon carbide PiN diode at 500 ℃ to be approximately zero, thereby allowing the device to operate normally at high temperature without generating too large leakage current or heat dissipation. Therefore, the high-power silicon carbide PiN diode plays a significant role in the field of power semiconductors, is also the key point in the research field of future power rectifiers, and has very wide application prospects in military and civil aspects.

The traditional silicon carbide PiN diode is limited by the defects of silicon carbide epitaxial materials (with lower minority carrier lifetime), the conductance modulation effect is reduced when the silicon carbide PiN diode is conducted in the forward direction, the conduction resistance is increased, so that the forward current is smaller, the forward conduction characteristic of the silicon carbide PiN diode is seriously influenced, and the application of the silicon carbide PiN diode in the field of high voltage and large current is limited.

Disclosure of Invention

Aiming at the problem of small forward current of the traditional silicon carbide Pin diode, the invention provides the silicon carbide Pin diode with the buried layer structure, the electric field at the boundary of a P-type region 6 and an N-type silicon carbide epitaxial layer 4 is enhanced by introducing a P-type buried layer 5, and the electric field at the boundary of an N-type silicon carbide substrate and the N-type silicon carbide epitaxial layer 4 is enhanced by introducing an N-type buried layer 3.

The technical scheme of the invention is as follows:

a silicon carbide PiN diode with a buried layer structure comprises a cathode, an N-type silicon carbide substrate, an N-type silicon carbide epitaxial layer, a P-type region and a metal anode which are sequentially arranged from bottom to top;

an N-type buried layer and/or a P-type buried layer are/is further arranged in the N-type silicon carbide epitaxial layer, and the N-type buried layer is located above the N-type silicon carbide substrate and used for enhancing an electric field at the boundary of the N-type silicon carbide substrate and the N-type silicon carbide epitaxial layer; the P-type buried layer is located below the P-type region and used for enhancing an electric field at the boundary of the P-type region and the N-type silicon carbide epitaxial layer.

Specifically, the distance between the lower surface of the N-type buried layer and the upper surface of the N-type silicon carbide substrate is not more than 2 microns, and the distance between the upper surface of the P-type buried layer and the lower surface of the P-type region is not more than 2 microns.

Specifically, the distance between the upper surface of the P-type buried layer and the lower surface of the P-type region is 1 μm, and the doping concentration of the P-type buried layer is 10¹⁸cm^-3(ii) a The distance between the lower surface of the N-type buried layer and the upper surface of the N-type silicon carbide substrate is 1 mu m, and the doping concentration of the N-type buried layer is 10¹⁸cm^-3。

Specifically, the doping concentration of the P-type region is 10¹⁹cm^-3The thickness is 1 μm; the doping concentration of the N-type silicon carbide substrate is 10¹⁹cm^-3(ii) a The thickness of the N-type silicon carbide epitaxial layer is 30 mu m, and the doping concentration is 3 multiplied by 10¹⁵cm^-3。

Specifically, the P-type buried layer and the N-type buried layer are formed by means of ion implantation, and the P-type region is formed by means of epitaxy.

The invention has the beneficial effects that: the invention provides a silicon carbide Pin diode with a buried layer structure, which enhances an electric field at the boundary of a P-type region and an N-type silicon carbide epitaxial layer by introducing a P-type buried layer, enhances an electric field at the boundary of an N-type silicon carbide substrate and the N-type silicon carbide epitaxial layer by introducing an N-type buried layer, enhances the effect of conductivity modulation, improves the forward conduction current of the silicon carbide Pin diode, and improves the forward conduction performance of the silicon carbide Pin diode.

Drawings

Fig. 1 is a schematic diagram of a unit cell of a PiN diode of silicon carbide with a buried layer structure according to the present invention.

Fig. 2 is a comparison graph of forward current-voltage curves of a silicon carbide PiN diode simulation cell with a buried layer structure and a conventional silicon carbide PiN diode simulation cell according to the present invention.

Fig. 3 is a comparison graph of hole concentration distribution in the drift region of a silicon carbide PiN diode with a buried layer structure and a silicon carbide PiN diode with a conventional structure according to the present invention.

Detailed Description

The advantages of the buried-structure silicon carbide PiN diode of the present invention are further illustrated by way of example, and by way of illustration in conjunction with simulations and drawings.

As shown in fig. 1, the buried-layer-structure-containing silicon carbide PiN diode provided by the invention comprises an N-type silicon carbide substrate 2, wherein a cathode 1 is connected to the lower end of the N-type silicon carbide substrate 2, an N-type silicon carbide epitaxial layer 4 is connected to the upper end of the N-type silicon carbide substrate 2, a P-type region 6 is arranged on the upper surface of the N-type silicon carbide epitaxial layer 4, a metal anode 7 is connected to the upper side of the P-type region 6, and the P-type region 6 and the metal anode 7 form ohmic contact.

The invention provides three modes of only arranging the N-type buried layer 3 in the N-type silicon carbide epitaxial layer 4, only arranging the P-type buried layer 5 in the N-type silicon carbide epitaxial layer 4 or arranging the N-type buried layer 3 and the P-type buried layer 5 in the N-type silicon carbide epitaxial layer 4 to improve the forward conduction performance of the silicon carbide Pin diode. The N-type buried layer 3 and the P-type buried layer 5 are arranged in the N-type silicon carbide epitaxial layer 4, the P-type buried layer 5 is arranged below the P-type region 6, and the N-type buried layer 3 is arranged above the N-type silicon carbide substrate 2. The N-type buried layer 3 is used for enhancing an electric field at the boundary of the N-type silicon carbide substrate 2 and the N-type silicon carbide epitaxial layer 4, the distance between the N-type buried layer 3 and the N-type silicon carbide substrate 2 cannot be too large, and the effect of enhancing the electric field at the boundary of the N-type silicon carbide substrate 2 and the N-type silicon carbide epitaxial layer 4 cannot be realized if the distance is too large; similarly, the P-type buried layer 5 is used for enhancing the electric field at the boundary between the P-type region 6 and the N-type silicon carbide epitaxial layer 4, and the distance between the P-type buried layer 5 and the P-type region 6 cannot be too large, so that the buried layer structure of the invention is a P-type shallow buried layer and an N-type deep buried layer. In the embodiment, it is preferable to set the distance between the lower surface of the N-type buried layer 3 and the upper surface of the N-type silicon carbide substrate 2 to be not more than 2 μm, and the distance between the upper surface of the P-type buried layer 5 and the lower surface of the P-type region 6 to be not more than 2 μm.

The scheme provided by the invention enhances the electric field at the boundary of the N-type silicon carbide substrate 2 and the N-type silicon carbide epitaxial layer 4 and the electric field at the boundary of the P-type region 6 and the N-type silicon carbide epitaxial layer 4, so that the injection of non-equilibrium carriers is enhanced, the minority carrier injection efficiency of the diode is improved, the effect of enhancing conductivity modulation is achieved, the forward on resistance is reduced, the forward conducting current of the silicon carbide Pin diode is improved, and the forward conducting performance of the silicon carbide Pin diode is improved.

In some embodiments, the P-type region 6 is epitaxially formed on the upper surface of the N-type silicon carbide epitaxial layer 4, and the P-type buried layer 5 and the N-type buried layer 3 are ion-implanted.

In order to illustrate the advantages of the diode device of the present invention compared to the conventional PiN diode, the present invention provides an embodiment, which performs simulation comparative analysis on the diode device of this embodiment and the conventional PiN diode without the buried layer structure. In the embodiment, the N-type silicon carbide substrate 2 with the simulated cellular structure adopts the N-type doping concentration of 10¹⁹cm^-34H-SiC substrate of (1); the N-type silicon carbide epitaxial layer 4 is selected to have a thickness of 30 μm and a doping concentration of 3 × 10¹⁵cm^-3(ii) a The P-type region 6 has a thickness of 1 μm and a doping concentration of 10¹⁹cm^-3(ii) a The distance from the upper surface of the P-type buried layer 5 to the lower surface of the P-type region 6 is set to be 1 μm, and the doping concentration of the P-type buried layer 5 is set to be 10¹⁸cm^-3(ii) a The distance between the lower surface of the N-type buried layer 3 and the upper surface of the N-type silicon carbide substrate 2 is set to be 1 μm, and the doping concentration of the N-type buried layer 3 is set to be 10¹⁸cm^-3。

Fig. 2 shows a current-voltage curve of the device of the present embodiment when a forward bias is applied, and for comparison, fig. 2 also includes a forward current-voltage curve of the conventional planar PiN diode. As can be seen from fig. 2, the application of the buried layer structure provided by the present invention effectively improves the forward current of the diode, and the current gain reaches 54.5% when the diode is forward biased at 5V.

Fig. 3 shows a comparison graph of hole concentration distribution in the N-type drift region when the device of the present embodiment and the conventional PiN device are forward biased at 5V, where the ordinate is hole concentration and the abscissa is the distance from top to bottom of the cross-sectional view of the silicon carbide PiN diode of the structure of fig. 1 proposed by the present invention.

Those skilled in the art can make various other specific changes and combinations based on the teachings of the present invention without departing from the spirit of the invention, and these changes and combinations are within the scope of the invention.