阅读说明：本技术 用于确保通用串行总线接口中的电力输送的设备和方法 (Apparatus and method for ensuring power delivery in a universal serial bus interface ) 是由 金济国 于 2019-04-12 设计创作，主要内容包括：一种确保设备和对方设备之间的通用串行总线USB接口中的电力输送的方法,该设备包括端口控制器和USB插座。该方法包括端口控制器尝试使用USB插座的至少一个引脚来检测USB插座中发生漏电流的异常状态；以及当检测到异常状态时,端口控制器断开连接在USB插座的电力引脚和设备的内部电路之间的开关,并且确定进入与对方设备分离的未附接状态。(A method of ensuring power transfer in a Universal Serial Bus (USB) interface between a device and a counterpart device, the device including a port controller and a USB receptacle. The method includes the port controller attempting to detect an abnormal state in which a leakage current occurs in the USB socket using at least one pin of the USB socket; and when the abnormal state is detected, the port controller opens a switch connected between the power pin of the USB socket and the internal circuit of the device, and determines to enter an unattached state separated from the counterpart device.)

1. A method of ensuring power transfer in a universal serial bus, USB, interface between a device and a counterpart device, the device comprising a port controller and a USB socket, the method comprising:

the port controller attempting to detect an abnormal state in which a leakage current occurs in the USB socket by using at least one pin of the USB socket; and

when the abnormal state is detected, the port controller opens a switch connected between a power pin of the USB socket and an internal circuit of the device, and determines to enter an unattached state separated from the counterpart device.

2. The method of claim 1, wherein the at least one pin is any pin in the USB socket that is different from a power pin.

3. The method of claim 2, wherein the USB socket is configured to support USB Type-C^TMIn the standard of the art,

the power pin is a VBUS pin, an

The at least one pin comprises at least one pin of a CC1 pin, a CC2 pin, a D + pin, a D-pin, an SBU1 pin, an SBU2 pin, a TX1+ pin, a TX1 pin, a TX2+ pin, a TX2 pin, an RX1+ pin, an RX1 pin, an RX2+ pin and an RX2 pin.

4. The method of claim 1, wherein the attempting to detect an abnormal state comprises:

applying a test signal to the at least one pin; and

detecting the abnormal state based on a response to the test signal from the at least one pin.

5. The method of claim 1, wherein the attempting to detect an abnormal state comprises:

detecting an impedance between two pins of the USB socket, the two pins including the at least one pin; and

detecting the abnormal state based on the detected impedance.

6. The method of claim 1, wherein the attempting to detect an abnormal state is repeated at a preset period.

7. The method of claim 1, further comprising: the port controller detects an attachment state of the partner device,

wherein the attempting to detect an abnormal state is performed immediately after the attachment state is detected.

8. The method of claim 7, further comprising: the port controller turns on the switch when the attachment state is detected and the abnormal state is not detected.

9. The method of claim 8, further comprising: the port controller detects an unattached state separated from the counterpart device after the switch is turned on,

wherein the attempting to detect an abnormal state is performed when there is no signal transmission/reception for a certain period of time after the non-attached state is not detected.

10. The method of claim 1, further comprising: when the abnormal state occurs, the port controller outputs an activated detection signal.

11. An apparatus configured to provide a Universal Serial Bus (USB) interface, the apparatus comprising:

a USB socket including a power pin;

a switch connected between the power pin and an internal circuit of the device; and

a port controller configured to detect an abnormal state in which a leakage current occurs in the USB socket by using at least one pin of the USB socket, and when the abnormal state is detected, open the switch and determine to enter an unattached state separated from a counterpart device.

12. The method of claim 11, wherein the USB socket is configured to support USB Type-C^TMIn the standard of the art,

the power pin is a VBUS pin, an

The at least one pin comprises at least one pin of a CC1 pin, a CC2 pin, a D + pin, a D-pin, an SBU1 pin, an SBU2 pin, a TX1+ pin, a TX1 pin, a TX2+ pin, a TX2 pin, an RX1+ pin, an RX1 pin, an RX2+ pin and an RX2 pin.

13. The device of claim 11, wherein the switch comprises two or more transistors connected in series between the power pin and the internal circuit, and each transistor comprises a control terminal connected to the port controller.

14. The apparatus of claim 11, wherein the port controller is configured to output an activated detection signal upon occurrence of the abnormal state,

the device also includes a master controller configured to enter an interrupt state in response to the activated detection signal.

15. The apparatus of claim 14, further comprising a signal generator configured to output a signal recognizable by a user of the apparatus,

wherein the main controller is configured to control the signal generator to output the signal recognizable by the user in response to the activated detection signal.

16. A port controller for a device is provided,

wherein the port controller is configured to detect an abnormal state in which a leakage current occurs in a USB socket of the device by using at least one pin different from a power pin of the USB socket, and generate a switch control signal for opening a switch connected between the power pin and an internal circuit of the device in response to detection of the abnormal state.

17. The port controller of claim 16, wherein the power pin is a VBUS pin, and

the at least one pin comprises at least one pin of a CC1 pin, a CC2 pin, a D + pin, a D-pin, an SBU1 pin, an SBU2 pin, a TX1+ pin, a TX1 pin, a TX2+ pin, a TX2 pin, an RX1+ pin, an RX1 pin, an RX2+ pin and an RX2 pin.

18. The port controller of claim 16, wherein the port controller is further configured to attempt to detect the abnormal state immediately after detecting an attachment state of the device to a counterpart device.

19. The port controller of claim 18, wherein the port controller is further configured to turn on the switch when the attachment state is detected and the abnormal state is not detected.

20. The port controller according to claim 19, wherein the port controller is further configured to detect an unattached state in which the device is detached from the counterpart device after the switch is turned on, and to detect the abnormal state when no signal is transmitted or received for a certain period of time after the unattached state is not detected.

Technical Field

The present disclosure relates to a Universal Serial Bus (USB) interface, and more particularly, to an apparatus and method for ensuring power delivery in a USB interface.

Background

Universal Serial Bus (USB) (or USB standard) is a standard for defining cables, connectors, and communication protocols for inter-device communication. USB interfaces are widely used in a variety of applications. USB defines a standard of power transmission and a protocol for transmitting and receiving data, and USB Power Delivery (PD) defines high power delivery such as 20V and 5A. However, when a conductive foreign substance enters the USB socket or when a short circuit occurs in the USB cable, excessive power consumption occurs in the device used as a power source for supplying power through the USB interface, the device may be damaged, and the USB socket and the USB plug may also be damaged.

Disclosure of Invention

Embodiments of the inventive concept provide a Universal Serial Bus (USB) interface, and more particularly, an apparatus and method to stably perform power transmission in a USB interface.

Embodiments of the inventive concept provide a method of ensuring power transfer in a Universal Serial Bus (USB) interface between a device including a port controller and a USB socket and a counterpart device. The method includes the port controller attempting to detect an abnormal state in which a leakage current occurs in the USB socket by using at least one pin of the USB socket; and when the abnormal state is detected, the port controller opens a switch connected between the power pin of the USB socket and an internal circuit of the device, and determines to enter an unattached state separated from the counterpart device.

Embodiments of the inventive concept also provide an apparatus to provide a Universal Serial Bus (USB) interface, the apparatus including a USB socket, the USB socket including: a power pin; a switch connected between the power pin and an internal circuit of the device; and a port controller configured to detect an abnormal state in which a leakage current occurs in the USB socket by using at least one pin of the USB socket, and when the abnormal state is detected, open the switch and determine to enter an unattached state separated from a counterpart device.

Embodiments of the inventive concept also provide a port controller of a device, wherein the port controller is configured to detect an abnormal state in which a leakage current occurs in a USB socket of the device by using at least one pin different from a power pin of the USB socket, and generate a switch control signal for turning off a switch connected between the power pin and an internal circuit of the device in response to the detection of the abnormal state.

Drawings

These and/or other aspects will become apparent and more readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 illustrates a block diagram of a USB device according to an embodiment of the inventive concept;

fig. 2 illustrates a block diagram of an example of the USB receptacle of fig. 1, according to an embodiment of the inventive concept;

fig. 3 illustrates a block diagram showing USB devices connected through a USB interface according to an embodiment of the inventive concept;

fig. 4 illustrates a diagram of an example of the switch of fig. 1, according to an embodiment of the inventive concept;

FIG. 5 illustrates a flow chart of a method of ensuring power delivery at a USB interface according to an embodiment of the present inventive concept;

fig. 6 illustrates a flowchart of a method of performing connection and disconnection at a USB interface according to an embodiment of the inventive concept;

fig. 7 illustrates a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept;

fig. 8A illustrates a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept;

fig. 8B illustrates a flowchart of another method of detecting an abnormal state according to an embodiment of the inventive concept;

fig. 9 illustrates a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept;

fig. 10 illustrates a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept; and

fig. 11 illustrates a flowchart of a method of processing an abnormal state according to an embodiment of the inventive concept.

Detailed Description

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to like elements throughout. In this regard, the embodiments may have different forms and should not be construed as limited to the descriptions set forth herein. Accordingly, the embodiments are described below to illustrate aspects of the present specification only by referring to the drawings. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items. Expressions such as "at least one of" modify the entire list of elements when preceded by the list of elements, rather than modifying individual elements in the list.

Embodiments may be described and illustrated in terms of blocks performing one or more of the described functions, as is common in the art of inventive concepts. These blocks, which may be referred to herein as units or modules, are physically implemented by analog and/or digital circuitry, such as logic gates, integrated circuits, microprocessors, microcontrollers, memory circuits, passive electronic components, active electronic components, optical components, hardwired circuitry, and the like, and may optionally be driven by firmware and/or software. For example, the circuitry may be embodied in one or more semiconductor chips, or on a substrate support such as a printed circuit board. The circuitry making up the block may be implemented by dedicated hardware or by a processor (e.g., one or more programmed microprocessors and associated circuitry), or by a combination of dedicated hardware for performing some of the functions of the block and a processor for performing other functions of the block. Each block of an embodiment may be physically separated into two or more interactive and discrete blocks without departing from the scope of the inventive concept. Similarly, the blocks of an embodiment may be physically combined into more complex blocks without departing from the scope of the inventive concept.

Fig. 1 illustrates a block diagram of a USB device 100 according to an embodiment of the inventive concept, and fig. 2 illustrates a block diagram showing an example of the USB socket 110 of fig. 1 according to an embodiment of the inventive concept. USB device 100 is any device capable of communicating with other devices via a USB interface, and may be a fixed device (e.g., a desktop computer, a server, or any other fixed device that communicates via a USB interface), may be a mobile device (e.g., a laptop computer, a mobile phone, a tablet PC, or any other mobile device that communicates via a USB interface), or may be a component included in the above-described device and providing a USB interface. As shown in fig. 1, the USB device 100 includes a USB socket 110, a termination circuit 120, a port controller 130, a power circuit 140, a main controller 150, a signal generator 160, and a switch 170.

The USB socket 110 may be coupled to a USB cable or a USB plug, which is a part of a USB entity, for connecting with a counterpart USB entity. The USB socket 110 may include a plurality of exposed pins, and may transmit or receive signals via the plurality of exposed pins. For example, as shown in fig. 2, the USB socket 110 may include pins for transmitting transmission signals TX + and TX- (i.e., signals TX1+, TX1-, TX2+ and TX2-), pins for receiving reception signals RX + and RX- (i.e., signals RX1+, RX1-, RX2+ and RX2-), pins for channel-constituting signals CC1 and CC2, a pin for VBUS voltage V _ BUS (i.e., VBUS), and a pin for ground voltage (i.e., GND). In some embodiments, USB socket 110 may have a USB Type-C according to^TMStandard pin arrangement (as shown in FIG. 2), but other embodiments are not limited to USB Type-C^TMThe pins are arranged. In fig. 2, the pins are represented as pins a 1-a 12 and B1-B12.

When foreign matter enters the USB socket 110 during the time when the USB plug is not coupled to the USB socket 110, or when a short circuit occurs in a USB cable coupled to the USB socket 110, two or more pins included in the USB socket 110 may be electrically connected to each other. Pins that are incorrectly electrically connected to each other may induce leakage currents, may interrupt communications conducted via the USB interface, and may damage USB device 100. In particular, when the USB device 100 is a portable device or a component included in the portable device, conductive materials such as water and metal may easily enter the USB socket 110, and thus excessive power consumption may occur and/or the USB device 100 may be damaged. In particular, when an attachment state in which USB entities are attached to each other is established, even if a leakage current may occur, USB Type-C^TMThe standard does not adjust or take measures to account for leakage currents until the USB entities are in an unattached state with the USB entities separated from each other. Herein, the attached state may refer to a state in which the USB device 100 (or the port controller 130) determines that the USB device 100 is connected to a counterpart USB entity. The unattached state may refer to a state in which the USB device 100 (or the port controller 130) determines that the USB device 100 is separated from the counterpart USB entity.

The USB device 100 of the present inventive concept may detect an abnormal state in which a leakage current may occur, and may stop power transmission through the USB socket 110 when the abnormal state is detected. For example, when an abnormal state is detected, the switch 170 may electrically disconnect the power pin receiving the VBUS voltage V _ BUS or outputting the VBUS voltage V _ BUS in the USB socket 110 from the power circuit 140. Therefore, unnecessary power consumption in the USB device 100 can be reduced, and the USB device 100 can be protected from damage due to excessive leakage current. Hereinafter, the occurrence of the leakage current due to the foreign substance entering the USB socket 110 will be mainly described, but it should be understood that the leakage current may occur due to other various factors in other cases, and the inventive concept is also applicable to such other cases.

Termination circuit 120 may be controlled by port controller 130 and may provide termination for USB receptacle 110 according to USB requirements. For example, the termination circuit 120 may transmit the channel constituting signals CC1 and CC2 to the USB socket 110 or the channel constituting signals CC1 and CC2 to the port controller 130 under the control of the port controller 130. The termination circuit 120 may also provide the VCONN voltage from the power circuit 140 to the USB receptacle 110 under the control of the port controller 130 to power the active cable.

The port controller 130 may control the termination circuit 120 by communicating with the termination circuit 120 and may control the USB interface according to signals received through the termination circuit 120. The port controller 130 may control port power supplied to or received from the outside through the USB socket 110, or may process the channel configuration signals CC1 and CC2 according to USB requirements. According to some embodiments, port controller 130 may be a logic block implemented by logic synthesis, a processor, a software block contained in a memory that stores instructions for execution by the processor, or a combination thereof. According to some embodiments, the port controller 130 may be referred to as a Power Delivery Integrated Circuit (PDIC). Further, according to some embodiments, the termination circuit 120 and the port controller 130 may be included in one integrated circuit, and such an integrated circuit may be referred to as a PDIC.

According to some embodiments, port controller 130 may detect an abnormal situation in which a leakage current may occur. For example, as will be described later with reference to fig. 7, the port controller 130 may apply a test signal to at least one pin, receive a response to the test signal from the at least one pin, and detect an abnormal state based on the received response. Further, as will be described later with reference to fig. 9, the port controller 130 may detect impedance between two pins included in the USB socket 110, and may detect an abnormal state based on the detected impedance.

Power circuit 140 may be electrically connected to a power pin of USB socket 110 via switch 170. According to some embodiments, when USB device 100 supports an up port (UFP), power circuitry 140 may receive VBUS voltage V _ BUS from a power pin of USB socket 110 through switch 170, and may also distribute power supplied by VBUS voltage V _ BUS to other components of USB device 100. According to some embodiments, when USB device 100 supports downstream port (DFP), power circuit 140 may provide VBUS voltage V _ BUS to the power pin of USB socket 110 through switch 170. According to some embodiments, the USB device 100 may support Dual Role Ports (DRPs) that can switch between a source (or host) and a sink (or device). Further, the power circuit 140 may generate a VCONN voltage that supplies the active cable and provide the VCONN voltage to the termination circuit 120. The VCONN voltage may be provided to the CC1 pin (e.g., a5 of fig. 2) or the CC2 pin (e.g., B5 of fig. 2) of the USB socket 110 by operation of the termination circuit 120 under the control of the port controller 130. In this specification, the positive power supply voltage that transfers power like the VBUS voltage V _ BUS and the VCONN voltage may be referred to as a power supply voltage.

The switch 170 may be connected between a power pin included in the USB socket 110 and the power circuit 140, and may be turned on or off according to a switch control signal SW provided from the port controller 130. For example, in response to the switch control signal SW being activated, the switch 170 may be turned on, and thus, the power pin and the power circuit 140 (also an internal circuit of the USB device 100) may be electrically connected to each other. On the other hand, in response to the deactivated switch control signal SW, the switch 170 may be opened, and thus, the power pin and the power circuit 140 may be electrically disconnected. As described below with reference to fig. 5, the port controller 130 may open the switch 170 when an abnormal state is detected, thereby preventing a leakage current from occurring due to the supply voltage.

The main controller 150 may generate transmit signals TX + and TX-, or may process receive signals RX + and RX-, and may communicate with the port controller 130. For example, the host controller 150 may include a USB port manager, and the USB port manager may operate a port policy and a USB PD (power delivery) protocol by communicating with the port controller 130. The state machine of the USB interface may be implemented by both the host controller 150 and the port controller 130.

The main controller 150 may receive the detection signal DET from the port controller 130 and perform a desired operation according to the detection signal DET. In some embodiments, when the detection signal DET indicating activation of an abnormal state occurring in the USB socket 110 is received from the port controller 130, the main controller 150 may generate the alarm control signal CTRL and provide the alarm control signal CTRL to the signal generator 160, so that the signal generator 160 generates the alarm signal S _ ALA. Further, according to some embodiments, the port controller 130 may stop generating the supply voltage by controlling the power circuit 140 in response to the activated detection signal DET.

The signal generator 160 may generate an alarm signal S _ ALA that may be recognized by a user of the USB apparatus 100 according to the alarm control signal CTRL provided from the main controller 150. According to some embodiments, the alarm signal S _ ALA may be a sound, and the signal generator 160 may comprise, for example, a speaker and/or a buzzer for outputting the sound. According to some embodiments, the alarm signal S _ ALA may be a visible signal and the signal generator 160 may comprise a display component, e.g. a Liquid Crystal Display (LCD) and/or a lamp like a Light Emitting Device (LED). When the signal generator 160 includes a display component, an alarm window may be displayed on the display component according to the alarm control signal CTRL. Further, according to some embodiments, the alarm signal S _ ALA may be a vibration of the USB device 100, and the signal generator 160 may include a component (e.g., a motor) that generates the vibration.

Referring to fig. 2, the USB socket 110' may have USB Type-C compliant^TMThe structure of (1). USB socket 110 'may have a symmetrical pin arrangement, and thus, the USB socket 110' and the USB plug may be normally coupled to each other in any direction. The USB socket 110' may include a TX1+ pin A2, a TX 1-pin A3, an RX1+ pin B11, an RX 1-pin B10, a TX2+ pin B2, a TX 2-pin B3, an RX2+ pin A11, and an RX 2-pin A10 as a data bus. The USB socket 110 'may include VBUS pins a4, a9, B4, and B9 as power buses, wherein the CC1 pin a5 or the CC2 pin B5 may transmit VCONN voltage according to a direction in which the USB socket 110' is coupled with a USB plug. In addition, the USB socket 110' may include two Side Band Use (SBU) pins A8 and B8 for SBU1 and SBU2, respectively, and two Configuration Channel (CC) pins a5 and B5. The CC1 pin a5 and the CC2 pin B5 may be collectively referred to as CC pins. Unlike the USB socket 110 ', the USB plug coupled to the USB socket 110' may include one channel configuration pin CC, and may include a dedicated VCONN pin. The USB socket 110' also includes pins A6 and A7 as a first differential pair D + and D-, and pins B6 and B7 as a second differential pair D + and D-. Finally, the USB socket 110' may include four ground pins a1, a12, B1, and B12 disposed at the outside. The four VBUS pins a4, a9, B4, and B9 may be electrically connected to each other within the USB socket 110' or at the termination circuit 120 of fig. 1 (i.e., the four VBUS pins a4, a9, B4, and B9 may have equal potentials). The four ground pins a1, a12, B1, and B12 may also be electrically connected to each other within the USB socket 110' or at the termination circuit 120 of fig. 1.

As described above, when a foreign object enters the USB socket 110 'or a short circuit occurs in the USB cable connected to the USB socket 110', a leakage current may occur, particularly when an electrical path is formed between the power pins (i.e., the VBUS pins a4, a9, B4, and B9, and the CC1 pin a5 or the CC2 pin B5 that provides the VCONN voltage) and the other pins (e.g., the ground pins a1, a12, B1, and B12), the leakage current may significantly increase.

Fig. 3 illustrates a block diagram showing a first USB apparatus 100a and a second USB apparatus 100b connected through a USB interface according to an embodiment of the inventive concept. In detail, fig. 3 shows a first USB device 100a (i.e., USB device 1) serving as a source (or host) and a second USB device 100b (i.e., USB device 2) serving as a sink (or device), wherein the first USB device 100a and the second USB device 100b are connected to each other via a cable 200 (i.e., USB interface). The USB device 100 described above with reference to fig. 1 may be used as a source for a first USB device 100a as in fig. 3, or may be used as a sink for a second USB device 100b as in.

Referring to fig. 3, the first USB apparatus 100a includes a USB socket 110a, a port controller 130a, an AC/DC converter 140a, and a switch 170 a. In order to provide the VBUS voltage V _ BUS to the second USB device 100b, the AC/DC converter 140a may generate the VBUS voltage V _ BUS, which is a DC voltage, from the AC voltage. According to some embodiments, the first USB device 100a may include a battery, and may include a DC/DC converter or a linear regulator instead of the AC/DC converter 140a in order to generate the VBUS voltage V _ BUS from the DC voltage.

The port controller 130a may control the switch 170a by the switch control signal SWa. When an abnormal state occurs, the port controller 130a may generate the deactivated switch control signal SWa, and thus, since the switch 170a is turned off, the AC/DC converter 140a (i.e., the internal circuit of the first USB device 100 a) and the VBUS pin may be turned off, and the VBUS voltage V _ BUS generated by the AC/DC converter 140a may not be output through the VBUS pin of the USB socket 110 a. Accordingly, a leakage current due to the VBUS voltage V _ BUS can be prevented.

The second USB device 100b may include a USB socket 110b, a port controller 130b, a charger 140b, and a switch 170 b. The charger 140b may charge the battery included in the second USB apparatus 100b according to the VBUS voltage V _ BUS supplied from the first USB apparatus 100 a. According to some embodiments, second USB device 100b may include circuitry (e.g., a voltage regulator) for generating one or more supply voltages from VBUS voltage V _ BUS provided from first USB device 100a for powering other components included in second USB device 100 b.

The port controller 130b may control the switch 170b by the switch control signal SWb. When an abnormal state occurs, the port controller 130b may generate the deactivated switch control signal SWb, and thus, since the switch 170b is turned off, the charger 140b (i.e., the internal circuit of the second USB device 100 b) and the VBUS pin may be turned off, and the VBUS voltage V _ BUS supplied from the first USB device 100a may not be supplied to the charger 140b and other internal circuits of the second USB device 100 b. Accordingly, a leakage current due to the VBUS voltage V _ BUS can be prevented.

In the following, one or more embodiments will be described mainly with reference to a USB device serving as a source of a first USB device 100a as in fig. 3. However, it should be understood that other embodiments may be applicable to a USB device used as a sink for the second USB device 100b of FIG. 3.

Fig. 4 illustrates a diagram of an example of the switch 170 of fig. 1, according to an embodiment of the inventive concept. As described above with reference to fig. 1, the switch 170' of fig. 4 may receive the switch control signal SW from the port controller 130 and may be turned on or off according to the switch control signal SW.

Referring to fig. 4, the switch 170' includes a first transistor T1 and a second transistor T2 connected in series between a first terminal P1 and a second terminal P2. The switch control signal SW may be provided to the control terminals P3 and P4 of the first and second transistors T1 and T2, and the first and second terminals P1 and P2 may be electrically connected to each other according to the switch control signal SW. Although fig. 4 shows that the switch 170 'includes two N-channel metal oxide semiconductor (NMOS) transistors, the switch 170' may include a P-channel metal oxide semiconductor (PMOS) transistor, or may include an NMOS transistor and a PMOS transistor connected in parallel to each other, according to some embodiments. In some embodiments, the switch 170' may include more than two transistors connected in series between the first terminal P1 and the second terminal P2.

As shown in fig. 4, the switch control signals SW may include a first switch control signal SW1 and a second switch control signal SW 2. According to some embodiments, the port controller 130 of fig. 1 may turn on or off the first transistor T1 and the second transistor T2 at different points in time. For example, the port controller 130 may generate the first and second switch control signals SW1 and SW2 such that the second transistor T2 is turned on after the first transistor T1 is turned on. Similarly, the port controller 130 may generate the first and second switch control signals SW1 and SW2 such that the first transistor T1 is turned off after the second transistor T2 is turned off.

Fig. 5 illustrates a flowchart of a method of ensuring Power Delivery (PD) at a USB interface between the USB device 100 and a counterpart USB device according to an embodiment of the inventive concept. For example, the method of fig. 5 may be performed by the port controller 130 of fig. 1, and fig. 5 will be described below with reference to fig. 1.

In operation S12, an operation for attempting to detect an abnormal state is performed. As described above with reference to fig. 1, the abnormal state may refer to a state in which a leakage current may occur in the USB socket 110, and a state different from the abnormal state may be referred to as a normal state. The port controller 130 may detect the abnormal state in various ways. For example, the port controller 130 may detect an abnormal state as disclosed in the applicant's U.S. patent application nos. 15/981,157, 16/025,335, 16/053,155 and korean patent application KR 10-2018 0062092 (which are incorporated herein by reference in their entirety). An example of an operation of the port controller 130 to detect an abnormal state will be described below with reference to fig. 7 to 10. In some embodiments, when there is no signal transmission/reception for a certain period of time, operation S12 may be performed. For example, the operation of detecting the non-attached state is performed after the switch 170 is turned on, and when there is no signal transmission/reception for a certain period of time after the non-attached state is not detected, operation S12 may be performed. When the abnormal state is detected in operation S12, in operation S14, operations for turning off the switch 170 and determining that the USB entities (i.e., the USB device 100 and the counterpart USB device) enter the unattached state are performed. As described above with reference to fig. 1 and 3, the switch 170 may be between the power pin included in the USB socket 110 and the internal circuit (i.e., the power circuit 140) of the USB device 100, and the port controller 130 may open the switch 170 when an abnormal state is detected to prevent a leakage current and/or damage caused by the leakage current from occurring. Further, the port controller 130 may open the switch 170 and determine to enter an unattached state separated from each other. For example, even when the USB device 100 is in an attached state connected to a counterpart USB device by a cable, the switch 170 may be switched off if an abnormal state is detected. That is, conventionally, when the USB Type-C is satisfied^TMThe USB device 100 will enter the unattached state under the detachment conditions specified by the standard. In contrast, in the embodiment of the inventive concept, when the abnormal state is detected, the switch 170 is turned off and the USB entity also enters the unattached state. Here, as described, the abnormal state may refer to a state in which a leakage current occurs in the USB socket 110. In other words, the detection of the abnormal state may be newly included in the separation condition.

Fig. 6 illustrates a flowchart of a method of performing connection and disconnection at a USB interface according to an embodiment of the inventive concept. As described below with reference to fig. 6, at least one operation for determining whether an abnormal state exists may be added to a general method of performing connection and disconnection. For example, the method of FIG. 6 may be performed by USB device 100 of FIG. 1, and FIG. 6 will be described below with reference to FIG. 1.

Referring to fig. 6, in operation S20, an operation for determining whether an abnormal state exists in the USB socket 110 is performed. That is, even in an unattached state where the USB device 100 is not connected to the counterpart USB device, an operation for determining whether there is an abnormal state, that is, an operation for attempting to detect an abnormal state, may be performed. According to some embodiments, operation S20 may be performed at preset intervals, or in other words, operation S20 may be repeated at preset cycles. As shown in fig. 6, when the abnormal state is detected (yes in S20), operation S20 is repeated periodically or non-periodically. Otherwise, when the abnormal state is not detected (no in S20), operation S21 is subsequently performed.

In operation S21, an operation for determining whether the USB device 100 is in an attached state to a counterpart USB device is performed. For example, the USB device 100 may determine whether the USB device 100 is in an attached state to a counterpart USB device by using the channel composition signals CC1 and CC 2. For example, when the USB device 100 recognizes the sync CC terminal Rd of the counterpart USB device through one of the channel configuration signals CC1 and CC2, the USB device 100 may recognize that the counterpart USB device is connected as a sink. As shown in fig. 6, when the USB device 100 is not in the attached state (no in S21), operation S20 is subsequently performed. Otherwise, when the USB device 100 is in the attached state (yes in S21), operation S22 is performed immediately thereafter.

In operation S22, an operation for determining whether an abnormal state exists in the USB socket 110 is performed. Unlike operation S20, an operation for determining whether an abnormal state exists in the attached state, that is, an operation for attempting to detect an abnormal state may be performed. As shown in fig. 6, when the abnormal state is detected (yes in S22), operation S20 is subsequently performed. Otherwise, when the abnormal state is not detected (no in S22), operation S23 is subsequently performed.

In operation S23, an operation for turning on the switch 170 is performed. Accordingly, when both the attached state and the normal state are satisfied, the switch 170 may be turned on, and as a result, the VBUS voltage V _ BUS may be supplied to the counterpart USB device. Therefore, when USB socket 110 is in an abnormal state, VBUS voltage V _ BUS can be prevented from being output through the power pin of USB socket 110.

In operation S24, an operation for determining whether the USB device 100 is in an unattached state separated from a counterpart USB device is performed. For example, the USB device 100 may determine whether the USB device 100 is in an unattached state separated from a counterpart USB device by using the channel configuration signals CC1 and CC 2. For example, when the USB device 100 fails to recognize the synchronization CC terminal Rd through one of the channel composition signals CC1 and CC2, it may be determined that the USB device 100 is in an unattached state. As shown in fig. 6, when it is determined that the USB device 100 is in the unattached state (yes in S24), operation S30 is subsequently performed. Otherwise, when it is determined that the USB device 100 is not in the unattached state (no in S24), operation S25 is subsequently performed.

When it is determined in operation S24 that the USB device 100 is not in the unattached state (or determined to be in the attached state), an operation for enabling a timer is performed in operation S25. For example, a timer may be reset and run. Timer interrupts may be used to periodically determine if an exception condition exists. When an interrupt occurs, it is determined whether an abnormal state exists. After operation S25, operation S28 and operation S26 may be performed in parallel.

In operation S26, power negotiation is performed. During power negotiation, USB device 100 and the counterpart USB device may determine the magnitude of VBUS voltage V _ BUS, the magnitude of current, and other conditions. Next, after the condition determined in operation S26 is set, an operation for transmitting and receiving a message is performed in operation S27.

In parallel with operation S26 and operation S27, it is determined in operation S28 whether a timer interrupt occurs. For example, it is determined whether the timer is not running (go off). When the interrupt has not occurred (no in S28), operation S28 is repeated. When the interrupt occurs (yes in S28), operation S29 is performed. In operation S29, an operation for determining whether an abnormal state exists is performed. That is, the port controller 130 may periodically attempt to detect an abnormal state during normal communication through the USB interface in the attached state. When the abnormal state is detected (yes in S29), operation S30 is subsequently performed.

When the unattached state is determined in operation S24 or the abnormal state is determined in operation S29, an operation for opening the switch 170 is performed in operation S30. Since the switch 170 is turned on in operation S23 and it is determined in operation S24 that the USB device 100 is in the unattached state, the switch 170 is turned off in operation S30, stopping the VBUS voltage V _ BUS from being output through the power pin. Further, since it is determined in operation S29 that there is an abnormal state, the switch 170 is turned off in operation S30, stopping the output of the VBUS voltage V _ BUS through the power pin. After operation S30, operation S20 is performed.

Fig. 7 illustrates a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept. For example, the method of fig. 7 may be an example of operation S12 of fig. 5 and operations S20, S22, and S29 of fig. 6. The method of fig. 7 may be performed by the port controller 130 of fig. 1, according to some embodiments, and fig. 7 will be described below with reference to fig. 1.

Referring to fig. 7, in operation S40, an operation for applying a test signal to at least one pin is performed. According to some embodiments, the port controller 130 may directly apply the test signal to any pin other than the power pin among pins included in the USB socket 100, or may control the termination circuit 120 to apply the test signal to the any pin. For example, the port controller 130 may apply a test signal to at least one of a CC1 pin, a CC2 pin, a D + pin, a D-pin, an SBU1 pin, an SBU2 pin, a TX1+ pin, a TX1 pin, a TX2+ pin, a TX2 pin, an RX1+ pin, an RX1 pin, an RX2+ pin, and an RX2 pin. An example of operation S40 will be described later with reference to fig. 8A and 8B.

In operation S50, an operation for determining whether an abnormal state exists based on the response to the test signal is performed. For example, the port controller 130 may receive a response to the test signal from at least one pin, and may determine (i.e., detect) whether an abnormal state exists based on the received response. An example of operation S50 will be described later with reference to fig. 8A and 8B.

Fig. 8A and 8B illustrate a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept. For example, the method of fig. 8A includes operation S40a and operation S50a as respective examples of operation S40 and operation S50 of fig. 7, and the method of fig. 8B includes operation S40B and operation S50B as respective examples of operation S40 and operation S50 of fig. 7. Specifically, in fig. 8A, an abnormal state may be detected by charging at least one pin, and in fig. 8B, an abnormal state may be detected by discharging at least one pin. In the following description of fig. 8A and 8B, overlapping description may be omitted.

Referring to fig. 8A, operation S40a includes a plurality of operations including operation S41a, operation S43a, operation S45a, operation S47a, and operation S49 a. In operation S41a, an operation for pulling down the first pin is performed. For example, the port controller 130 may pull down the first pin by using a switching circuit, a resistor, and/or a current source included in the termination circuit 120. According to some embodiments, the first pin may be any pin other than the power pin among pins included in the USB socket 110.

In operation S43a, operations for resetting the timer and detecting the voltage V1 of the first pin are performed. The voltage V1 of the first pin detected in operation S43a may be referred to as a first voltage V1. Since the first pin is pulled down in operation S41a, the first voltage V1 may have a relatively low level. As described below, the timer may be reset such that the voltage of the first pin rises from the first voltage V1 during a certain latency time.

In operation S45a, an operation for pulling up the first pin is performed. For example, the port controller 130 may pull up the first pin by using a switching circuit, a resistor, and/or a current source included in the termination circuit 120. Therefore, the voltage of the first pin may gradually rise from the first voltage V1.

In operation S47a, an operation for determining whether the waiting time has elapsed is performed. As shown in fig. 8A, when the waiting time has not elapsed (no in S47 a), operation S47a may be performed again. Otherwise, when the waiting time has elapsed (yes in S47 a), operation S49a is subsequently performed. That is, the port controller 130 waits until the timer, which has been reset in operation S43a, times out, and when the timer times out, performs operation S49 a.

In operation S49a, an operation for detecting the voltage V2 of the first pin is performed. The voltage detected in operation S49a may be referred to as a second voltage V2. During the waiting time, the voltage of the first pin may rise from the first voltage V1 to the second voltage V2, and thus the second voltage V2 may have a higher level than that of the first voltage V1. When there is no foreign object in the USB socket 110 (i.e., a normal state), the first pin may be in an open state, and thus the voltage of the first pin may relatively quickly rise when the first pin is pulled up. On the other hand, when foreign matter is present in the USB socket 110 (i.e., an abnormal state), the first pin may have an increased capacitance value due to the foreign matter, and thus the voltage of the first pin may relatively slowly rise as the first pin is pulled up.

As shown in fig. 8A, operation S50a includes a plurality of operations, i.e., operation S52a, operation S54a, operation S56a, and operation S58A. In operation S52a, an operation for calculating a charging slope is performed. For example, the port controller 130 may calculate the charging slope by dividing the difference between the second voltage V2 and the first voltage V1 by the waiting time. As described above, in the normal state, since the voltage of the first pin may relatively rapidly rise, the charging slope may have a relatively large value. In contrast, in the abnormal state, the voltage of the first pin may rise relatively slowly, and thus the charging slope may have a relatively small value.

In operation S54a, an operation for comparing the charging slope with a first reference value is performed. When the charging slope is greater than the first reference value (i.e., when the voltage of the first pin rises relatively rapidly) (yes in S54 a), it is determined that no foreign substance contacts the first pin, and thus it is determined as a normal state in operation S56 a. On the other hand, when the charging slope is less than the first reference value (i.e., when the voltage of the first pin rises relatively slowly) (no in S54 a), it is determined that a foreign object contacts the first pin, and thus an abnormal state may be determined in operation S58 a.

Referring to fig. 8B, operation S40B includes a plurality of operations including operation S41B, operation S43B, operation S45B, operation S47B, and operation S49B. In operation S41b, an operation for pulling up the second pin is performed. For example, the port controller 130 may pull up the second pin by using a switching circuit, a resistor, and/or a current source included in the termination circuit 120. According to some embodiments, the second pin may be any pin other than the power pin among pins included in the USB socket 110.

In operation S43b, operations for resetting the timer and detecting the voltage V1 of the second pin are performed. The voltage V1 of the second pin detected in operation S43b may be referred to as a first voltage V1. Since the second pin is pulled up in operation S41b, the first voltage V1 may have a relatively high level. As described below, the timer may be reset such that the voltage of the second pin drops from the first voltage V1 during a certain latency time.

In operation S45b, an operation for pulling down the second pin is performed. For example, the port controller 130 may pull down the second pin by using a switching circuit, a resistor, and/or a current source included in the termination circuit 120. Therefore, the voltage of the second pin may gradually decrease from the first voltage V1.

In operation S47b, an operation for determining whether the waiting time has elapsed is performed. As shown in fig. 8B, when the waiting time has not elapsed (no in S47B), operation S47B may be performed again. In contrast, when the waiting time has elapsed (yes in S47 b), operation S49b is subsequently performed. That is, the port controller 130 waits until the timer, which has been reset in operation S43b, times out, and when the timer times out, performs operation S49 b.

In operation S49b, an operation for detecting the voltage V2 of the second pin is performed. The voltage detected in operation S49b may be referred to as a second voltage V2. During the waiting time, the voltage of the second pin may drop from the first voltage V1 to the second voltage V2, and thus the second voltage V2 may have a lower level than the first voltage V1. When there is no foreign object in the USB socket 110 (i.e., a normal state), the second pin may be in an open state, and thus the voltage of the second pin may relatively quickly drop when the second pin is pulled down. On the other hand, when foreign matter is present in the USB socket 110 (i.e., an abnormal state), the second pin may have an increased capacitance value due to the foreign matter, and thus the voltage of the second pin may relatively slowly drop when the second pin is pulled down.

As shown in fig. 8B, operation S50B includes a plurality of operations, i.e., operation S52B, operation S54B, operation S56B, and operation S58B. In operation S52b, an operation for calculating a discharge slope is performed. For example, the port controller 130 may calculate the discharging slope by dividing the difference between the first voltage V1 and the second voltage V2 by the waiting time. As described above, in the normal state, since the voltage of the second pin may relatively rapidly drop, the discharge slope may have a relatively large value. In contrast, in the abnormal state, the voltage of the second pin may relatively slowly decrease, and thus the discharge slope may have a relatively small value.

In operation S54b, an operation for comparing the discharge slope with a second reference value is performed. When the discharging slope is greater than the second reference value (i.e., when the voltage of the second pin relatively rapidly drops) (yes in S54 b), it is determined that no foreign substance contacts the second pin, and thus it is determined as a normal state in operation S56 b. On the other hand, when the discharging slope is less than the second reference value (i.e., when the voltage of the second pin relatively slowly decreases) (no in S54 b), it is determined that a foreign object contacts the second pin, and thus an abnormal state is determined in operation S58 b.

Fig. 9 illustrates a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept. For example, the method of fig. 9 may be an example of operation S12 of fig. 5 and operations S20, S22, and S29 of fig. 6. The method of fig. 9 may be performed by the port controller 130 of fig. 1, according to some embodiments, and fig. 9 will be described below with reference to fig. 1.

Referring to fig. 9, in operation S60, an operation for detecting an impedance between two pins is performed. According to some embodiments, in order to detect the impedance, the port controller 130 may directly apply a voltage and/or a current between any two pins other than the power pin among the pins included in the USB socket 110, or may control the termination circuit 120 to apply a voltage and/or a current between the any two pins. For example, the port controller 130 may apply a test signal to at least one of a CC1 pin, a CC2 pin, a D + pin, a D-pin, an SBU1 pin, an SBU2 pin, a TX1+ pin, a TX1 pin, a TX2+ pin, a TX2 pin, an RX1+ pin, an RX1 pin, an RX2+ pin, and an RX2 pin. An example of operation S60 will be described later with reference to fig. 10.

In operation S70, an operation for determining whether an abnormal state exists based on the impedance is performed. For example, when the detected impedance is low, the port controller 130 may recognize that a short circuit occurs between two pins, thereby determining an abnormal state. On the other hand, when the detected impedance is high, the port controller 130 may recognize that a short circuit has not occurred between the two pins, thereby determining a normal state. An example of operation S70 will be described below with reference to fig. 10.

Fig. 10 illustrates a flowchart of a method of detecting an abnormal state according to an embodiment of the inventive concept. For example, the method of fig. 10 includes operations S60 'and S70', which are respective examples of operations S60 and S70 of fig. 9. In particular, fig. 10 illustrates a method of detecting an impedance between a third pin and a ground pin (e.g., the ground pin of fig. 2).

Referring to fig. 10, operation S60' includes a plurality of operations, i.e., operation S62, operation S64, and operation S66. In operation S62, an operation for pulling up the third pin is performed. For example, the port controller 130 may pull up the third pin by using a switching circuit, a resistor, and/or a current source included in the termination circuit 120. Next, in operation S64, an operation for detecting a voltage of the third pin is performed. Since the third pin is pulled up in operation S62, the voltage of the third pin may depend on the impedance between the third pin and the ground potential. In operation S66, an operation for estimating an impedance between the third pin and the ground pin is performed. For example, when the third pin is pulled up by the pull-up resistor, the port controller 130 may estimate an impedance between the third pin and the ground pin based on a resistance value of the pull-up resistor and a voltage of the third pin. In addition, when the third pin is pulled up by the current source, the port controller 130 may estimate an impedance between the third pin and the ground pin based on the current of the current source and the voltage of the third pin.

In operation S70', an operation for generating the detection signal DET is performed. For example, the port controller 130 may generate the activated detection signal DET when the estimated impedance is low. On the other hand, when the estimated impedance is high, the port controller 130 may generate the deactivated detection signal DET.

Fig. 11 illustrates a flowchart of a method of processing an abnormal state according to an embodiment of the inventive concept. In detail, when the abnormal state is determined in operation S12 of fig. 5 and operation S20, operation S22, and operation S29 of fig. 6, respectively, the method of fig. 11 is subsequently performed. For example, when the abnormal state is determined in operation S20 of fig. 6, operation S81, operation S82, and operation S83 of fig. 11 may be performed, and then operation S20 of fig. 6 may be performed. The method of FIG. 11 may be performed by USB device 100 of FIG. 1, according to some embodiments, and FIG. 11 will be described below with reference to FIG. 1.

In operation S81, an operation for outputting the activated detection signal DET is performed. For example, the port controller 130 may generate the activated detection signal DET when the abnormal state is detected, and the main controller 150 may recognize the abnormal state by receiving the activated detection signal DET from the port controller 130.

In operation S82, an operation for causing an interrupt of the main controller 150 is performed. For example, the detection signal DET may cause an interrupt of the main controller 150. That is, the main controller 150 may be configured to enter an interrupt state in response to the activated detection signal DET. As described above with reference to the drawings, the abnormal state may cause a leakage current, and may cause excessive power consumption and damage due to the leakage current. Accordingly, the main controller 150 can process the activated detection signal DET through an interrupt.

In operation S83, an operation for outputting an alarm signal S _ ALA is performed. For example, the main controller 150 may output the control signal CTRL in response to the activated detection signal DET, so that the signal generator 160 generates the alarm signal S _ ALA. Accordingly, the user of the USB device 100 can recognize the occurrence of the abnormal state and take necessary measures.

It is to be understood that the embodiments described herein are to be considered in all respects only as illustrative and not restrictive. Descriptions of features or aspects within each embodiment should generally be considered as available for other similar features or aspects in other embodiments.

Although one or more embodiments have been described with reference to the accompanying drawings, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope defined by the following claims.