阅读说明：本技术 一种通用型emccd单板相机系统 (Universal EMCCD single-board camera system ) 是由 何伟基 杨俊超 陈钱 顾国华 张闻文 夏一凡 朱海奇 吴才勇 于 2019-11-01 设计创作，主要内容包括：本发明公开了一种通用型EMCCD单板相机系统,包括镜头、计算机、EMCCD器件背板和底板,底板包括系统供电单元、FPGA控制单元、串口控制单元、DDR2存储单元、转移时钟驱动单元、倍增时钟驱动单元、低通滤波单元、两路相关双采样A/D转换单元、电平转换单元、Cameralink输入接口单元、Cameralink输出接口单元。本发明采用单板驱动,相较于之前多板系统,避免了板间时序相位关系的错位麻烦,相较于相机而言又可满足多种芯片的测试应用,满足工业级别测试系统的需求；针对不同型号的EMCCD,软件上更改时许驱动,硬件上只需要设计不同的EMCCD底座即可。(The invention discloses a universal EMCCD single-board camera system which comprises a lens, a computer, an EMCCD device back board and a bottom board, wherein the bottom board comprises a system power supply unit, an FPGA control unit, a serial port control unit, a DDR2 storage unit, a transfer clock driving unit, a multiplication clock driving unit, a low-pass filtering unit, two paths of related double-sampling A/D conversion units, a level conversion unit, a Cameralink input interface unit and a Cameralink output interface unit. Compared with the prior multi-board system, the single-board driving system avoids the dislocation trouble of the time sequence phase relationship between boards, can meet the test application of various chips compared with a camera, and meets the requirement of an industrial-level test system; for EMCCD of different models, the software is modified while driving, and hardware only needs to design different EMCCD bases.)

1. A universal EMCCD single-board camera system is characterized by comprising a lens (1), a computer (2), an EMCCD device backboard (3) and a bottom board (4), wherein the bottom board (4) comprises a system power supply unit (4-1), an FPGA control unit (4-2), a serial port control unit (4-3), a transfer clock driving unit (4-5), a multiplication clock driving unit (4-6), a low-pass filtering unit (4-7), two paths of related double-sampling A/D conversion units (4-8), a level conversion unit (4-9) and a Cameralink output interface unit (4-10), and the system power supply unit (4-1) is respectively connected with each unit to provide stable voltage; the FPGA control unit (4-2) is respectively connected with the transfer clock driving unit (4-5), the multiplication clock driving unit (4-6), the level conversion unit (4-9), the CameraLink interface unit (4-10) and the serial port control unit (4-3);

the EMCCD device backboard (3) comprises an EMCCD sensor chip (3-1), a bias voltage unit (3-2) and an analog signal reading unit (3-3), the EMCCD device backboard (3) is connected with a system power supply unit (4-1), a transfer clock driving unit (4-5), a multiplication clock driving unit (4-6) and a low-pass filtering unit (4-7) on the bottom plate (4) through connectors, the low-pass filtering unit (4-7) receives analog signals output by the analog signal reading unit (3-3), then is connected with a related double-sampling A/D conversion unit (4-8) to perform analog-to-digital conversion, and then is transmitted to an FPGA control unit (4-2) through a level conversion unit (4-9); the EMCCD device backboard (3) is connected with the lens (1) through a fixing structure;

the computer (2) comprises a display unit (2-1), a serial software unit (2-2) and an image acquisition card unit (2-3), and the serial software unit (2-2) is connected with a serial control unit (4-3) and used for sending instructions; the image acquisition card unit (2-3) is connected with the Cameralink output interface unit (4-10) and is used for receiving image data.

2. The system of claim 1, wherein the process of direct imaging as an electronics system is: programming a driving program which is matched with a specific EMCCD sensor chip (3-1) and compiled by a Verilog hardware language into an FPGA control unit (4-2), wherein the FPGA control unit (4-2) generates different time sequence control signals required by the work of the EMCCD sensor chip (3-1), one part of the time sequence control signals pass through a transfer clock driving unit (4-5), and the other part of the time sequence control signals pass through a multiplication clock driving unit (4-6) to obtain driving signals matched with the EMCCD sensor chip (3-1); an EMCCD sensor chip (3-1) receives a correct driving signal and direct current bias to generate a point-to-point packet representing image data, and the point-to-point packet is transferred and converted to be output as an analog image data signal, specifically a weak analog level signal; the driving capability of an analog level signal is improved through an analog signal reading unit (3-3), the analog level signal is connected to a low-pass filtering unit (4-7) for filtering, denoising and amplifying, then the analog level signal enters a related double-sampling A/D conversion unit (4-8) for sampling and analog-to-digital conversion, the analog level signal is sent to an FPGA control unit (4-2) for caching through a level conversion unit (4-9), the FPGA control unit (4-2) sequentially reads cached data to a Cameralink output interface unit (4-10), the Cameralink output interface unit (4-10) is connected with a computer (2) through a cable, and finally imaging is carried out.

3. The system of claim 1, characterized in that as the electronic system imaging needs to control various parameters and working modes of the camera system, the FPGA control unit (4-2) receives the instruction of the computer (2) through the serial port control unit (4-3) to control the pixel rate, the integration time, the multiplication gain, the output channel selection parameter; the serial port control unit (4-3) adopts an RS232 protocol, the serial port control unit (4-3) sends an instruction to be cached in the FPGA control unit (4-2), and the FPGA control unit (4-2) reads the instruction to change the values of different registers.

4. The system according to claim 1, further comprising a DDR2 memory unit (4-4) and a Cameralink input interface unit (4-11) as a camera system for presentation imaging, the DDR2 memory unit (4-4) being connected to the FPGA control unit (4-2) for storing image data; the Cameralink input interface unit (4-11) is connected with the FPGA control unit (4-2) and used for receiving external input data streams; the FPGA control unit (4-2) stores the EMCCD image data into a DDR2 storage unit (4-4), and the read-write of video data signals is completed by controlling the DDR2 storage unit (4-4); external video data signals are input into the FPGA control unit (4-2) through the Cameralink input interface unit (4-11), stored into the DDR2 storage unit (4-4) through the FPGA control unit (4-2), and read and write of the video data signals are completed through control over the DDR2 storage unit (4-4).

5. The system of claim 1, wherein the system power supply unit (4-1) comprises four parts, the system is powered by means of LDO, and the power supply V1 part is provided for the FPGA control unit (4-2) through the LDO power chip; the +3.3V is also used by a CameraLink input interface unit (4-11), a CameraLink output interface unit (4-10), a serial port control unit (4-3) and a level conversion unit (4-9); +3.3V and +1.8V generate +0.9V for DDR2 memory cells (4-4) to use through TPS 51200; the power supply V2 partially supplies power to the transfer clock driving units (4-5) and the related double-sampling A/D conversion units (4-8) through the LDO power chip; the power supply V3 part supplies power to the high-voltage operational amplifier part of the multiplication clock driving unit (4-6) through a pi-type filter consisting of magnetic bead capacitors; the power supply V4 part generates +28V through the MSK5230 to supply power to the bias voltage unit (3-2) part, and the power is supplied to the EMCCD sensor chip (3-1) after being subjected to resistance voltage division.

6. The system according to claim 1, wherein the core chip used by the transfer clock driving unit (4-5) is an EL7457, and the EL7457 receives the timing pulse signal generated by the FPGA control unit (4-2) to perform level conversion and then outputs the timing pulse signal as the transfer clock driving signal meeting the requirements of the EMCCD sensor chip (3-1); 16 paths of transfer clock driving signals are led out through 4 EL7457, 8 paths of the transfer clock driving signals are provided with downward clamping circuits after the level conversion unit, and the other 8 paths of the transfer clock driving signals are not clamped by negative voltage.

7. The system according to claim 1, wherein the multiplying clock driving unit (4-6) comprises a DAC part, a low-voltage filtering operational amplifier part, a high-voltage operational amplifier part and a clamping circuit part, the FPGA control unit (4-2) generates 14 pairs of differential data signals, 1 pair of differential clock signals and 1 single-ended control signal required by the DAC, and the DAC converts the digital signals into analog sine-like wave signals after receiving the signals; the low-voltage filtering operational amplifier part smoothes the signal and then sends the signal to the high-voltage operational amplifier part for amplification to obtain a multiplication driving signal meeting the requirement of the working amplitude of the EMCCD sensor; after passing through an adjustable upward clamping circuit, the signal is transmitted to an EMCCD device backboard (3) to drive an EMCCD sensor chip (3-1).

8. The system according to claim 1, wherein the transfer clock driving unit (4-5) and the multiplication clock driving unit (4-6) are connected to the backplane (3) through connectors, the generated timing driving signal is directly supplied to the EMCCD sensor chip (3-1), the +28V generated by the power supply V4 is connected to the backplane (3) through connectors, different bias voltages required by the EMCCD sensor chip (3-1) are generated through resistance voltage division, the EMCCD sensor chip (3-1) generates photo-generated electrons under the action of the clock driving signal and the bias voltage driving signal, and outputs an analog image signal from a readout register inside the EMCCD sensor chip, the image signal is sent to an analog signal reading unit (3-3), and is output to a low-pass filtering unit (4-7) on a bottom plate (4) after the driving capability is improved; the analog signal readout unit (3-3) employs an operational amplifier ADA4800 for CCD output by ADI.

9. The system according to claim 1, characterized in that the low-pass filtering unit (4-7) adopts a structure of four-order low-pass filters formed by cascading two second-order active low-pass filters; when the device works, video analog signals output by the EMCCD sensor chip (3-1) are input into a low-pass filtering unit (4-7) after passing through ADA4800 for improving driving capacity; the low-pass filtering unit (4-7) adopts an LMH6715 chip which is composed of two identical operational amplifiers, each part is matched with a proper resistance-capacitance to form a low-pass filter, and signals are output after completing impedance conversion and filtering amplification functions from the low-pass filtering unit (4-7) and enter a related double-sampling A/D conversion unit (4-8).

10. The system according to claim 1, characterized in that the Cameralink output interface unit (4-10) adopts Base mode to transmit data, and uses the coding chip DS90CR287 to output the 14-bit data signal buffered by the FPGA control unit (4-2) as 5 pairs of differential signals conforming to the Cameralink protocol; the Cameralink input interface unit (4-11) adopts the Base mode to transmit data, and a decoding chip DS90CR288 is used for decoding five pairs of externally input differential signals into single-ended data signals with 14 bits, and the single-ended data signals are buffered for the FPGA control unit (4-2).

Technical Field

The invention belongs to the technical field of low-light-level imaging, and particularly relates to a universal EMCCD (electron multiplying CCD) single-board camera system.

Background

The CCD (charge coupled device) was invented in the last 70 th century and has the advantages of small size, low noise, long service life and the like. In recent years, people are not satisfied with the application of CCDs in the visible light field, and gradually expand to the low-light-level field. Dim light refers to relatively dim light or light that is low enough in energy to cause human visual senses at night or in low light ambient conditions. Under such conditions, detection imaging of weak light emitted by a target or reflecting starlight moonlight or the like which is far below normal illumination requires a low-light-level imaging technique. The technical principle is that after a detector detects a weak signal, the weak signal is amplified, transmitted, converted, processed and the like, and finally a clear image which can be identified by human vision is obtained. The technology converts a dim light image which is difficult to observe by human eyes into a clear image which is easy to recognize under the condition of not needing active illumination, and makes up the limitation of human vision.

At present, three kinds of CCD sensors, such as enhanced CCD (ICCD), electron impact CCD (EBCCD), electron multiplication CCD (EMCCD), are widely applied in the field of low light level.

ICCD combines an image intensifier with a common CCD, weak incident light irradiates a photocathode to generate photo-generated electrons, electron multiplication is realized in a microchannel plate, the multiplied electrons bombard a fluorescent screen to generate a photon image higher than the incident light, and then the CCD collects the photon image through an optical fiber. The series of steps enables enhanced detection of incident light. ICCD has advantages in increased sensitivity and resolution; the disadvantages are its large noise, low quantum efficiency, image distortion, etc.

The EBCCD removes the design of the phosphor screen in the ICCD, thereby making the volume smaller. The photo-generated electrons directly bombard the CCD imaging area after being multiplied by the microchannel plate, thereby realizing the enhancement of incident light. The disadvantage is that the EBCCD generates some ions while photo-generated electrons are generated, and these additionally generated ions can cause radiation damage to the CCD after acceleration, resulting in increase of dark current and leakage current, and affecting the service life of the device.

EMCCD differs from ICCD and EBCCD in that electrons are not multiplied before CCD imaging, but rather during CCD signal readout; because no image intensifier with vacuum characteristic is used, the all-solid-state electron multiplication register is embedded into the CCD device, on-chip gain is realized, and strong light is not afraid. The structure is only increased in stages after the CCD reads out the register, so that the advantage of long service life of the CCD is inherited. Meanwhile, due to the fact that an electron multiplication structure is simplified, the size of the sensor is greatly reduced, charge multiplication noise is effectively reduced, and higher detection sensitivity can be obtained.

There are TI companies in the united states and E2V companies in the uk that are currently capable of producing mature EMCCD devices worldwide. With the breakthrough of semiconductor manufacturing process and production process, russia, ukraine and other countries have achieved many achievements in EMCCD manufacturing. China starts late in the field of EMCCD, but until now, an EMCCD device with the resolution of 1024 x 1024 has been developed.

Mature chip test platforms and mature electronic control systems are also required for different EMCCD devices. Patent 201510890489.9 "CCD Camera, Multi-parameter controllable Electron multiplying CCD imaging System and method" designs an EMCCD camera system, makes EMCCD chip use the computerization, miniaturization, but this system only aims at a chip, if be used for testing, can have very big limitation. Patent 201710524708.0 universal electron multiplying CCD driving system and method and paper universal EMCCD driving system designs a universal EMCCD driving electronic system which can drive most of EMCCD chips, however, the system is composed of a plurality of board cards, and the chip replacement debugging is complicated. The single-board camera system designed in the thesis EMCCD imaging component research is limited to a circuit design only for one chip, and has no image processing function.

Disclosure of Invention

The invention aims to provide a universal EMCCD single-board camera system, which can realize imaging of chips of multiple models, provide an electronic control part for a chip test platform, can control parameters and a working mode of the camera system by sending instructions through a computer, can receive input video data streams and can perform algorithm processing on the images on hardware.

The technical solution for realizing the purpose of the invention is as follows: a universal EMCCD test system comprises a lens, a computer, an EMCCD device backboard and a bottom plate, wherein the bottom plate comprises a system power supply unit, an FPGA control unit, a serial port control unit, a DDR2 storage unit, a transfer clock driving unit, a multiplication clock driving unit, a low-pass filtering unit, two paths of related double-sampling A/D conversion units, a level conversion unit, a Cameralink input interface unit and a Cameralink output interface unit, and the system power supply unit is used for connecting other units and providing stable voltage; the FPGA control unit is respectively connected with the clock driving unit, the high-speed A/D conversion unit, the CameraLink interface unit and the serial port control unit; the EMCCD device backboard comprises an EMCCD sensor chip and a bias voltage unit and is connected with a system power supply unit, a clock driving unit and a low-pass filtering unit on the bottom board through a connector; the computer comprises a display unit, a serial port software unit and an image acquisition card unit, wherein the serial port software unit is connected with the serial port control unit and used for sending instructions; the image acquisition card unit is connected with the Cameralink output interface unit and used for receiving image data.

Compared with the prior art, the invention has the following remarkable advantages: (1) for EMCCDs of different models, the driver is allowed to be driven when the codes are changed, and only different EMCCD bases need to be designed on hardware, namely, the Verilog codes written in advance are programmed by one key, so that the driver for electron multiplication CCDs of different models is conveniently realized. (2) Parameters such as horizontal, vertical and multiplication clock driving phase, period and amplitude can be modified through the serial port, and debugging and testing of different chips are greatly facilitated. (3) Different EMCCD device backplanes are designed for different EMCCD chips, different bias voltages are provided on the backplanes through resistance voltage division, complex SPI control DAC is not needed for realization, power consumption is low, and debugging is simpler. (4) As an electronic system which can be used for testing, control instructions such as pixel rate, integration time, gain multiple, output channel selection and the like can be sent through a serial port, controllable selection of multiple parameters is achieved, and testing is facilitated. (5) As a camera system for demonstration imaging, the system circuit is designed with two pieces of DDR2, and can perform simple image processing on an obtained original image on hardware, and can realize functions such as image enhancement, edge detection, and the like. (6) The circuit is designed with one path of base mode Cameralink output and one path of base mode Cameralink input, and can realize the processing of external input video signals and EMCCD output video signals, such as cutting, gating output and the like.

The present invention is described in further detail below with reference to the attached drawing figures.

Drawings

Fig. 1 is a schematic block diagram of the general structure of a universal EMCCD single-board camera system according to the present invention.

Fig. 2 is a block diagram showing the flow of code data written in the present invention.

FIG. 3 is a schematic block diagram of the multiplied clock drive of the present invention.

Fig. 4 is a circuit diagram of a low-pass filtering unit according to the present invention.

Fig. 5 is a schematic circuit diagram of an analog-to-digital conversion unit according to the present invention.

FIG. 6 is a circuit diagram of a level shift unit according to the present invention.

Fig. 7 is a diagram showing the effect of CCD97 imaging using an electron-multiplying CCD chip.

Fig. 8 is a diagram showing the imaging effect of the CCD201 using an electron-multiplying CCD chip.

FIG. 9 is an image before and after image processing according to the present invention.

Detailed Description

Referring to fig. 1, the universal EMCCD single-board camera system of the present invention includes a lens 1, a computer 2, an EMCCD device back plate 3 and a bottom plate 4, wherein the bottom plate 4 is a main component of the present invention. The bottom plate 4 comprises a system power supply unit 4-1, an FPGA control unit 4-2, a serial port control unit 4-3, a transfer clock driving unit 4-5, a multiplication clock driving unit 4-6, a low-pass filtering unit 4-7, two-path related double-sampling A/D conversion units 4-8, a level conversion unit 4-9 and a Cameralink output interface unit 4-10. The system power supply unit 4-1 is respectively connected with the other units to provide stable voltage; the FPGA control unit 4-2 is respectively connected with a transfer clock driving unit 4-5, a multiplication clock driving unit 4-6, a level conversion unit 4-9, a CameraLink interface unit 4-10 and a serial port control unit 4-3. The EMCCD device backboard 3 comprises an EMCCD sensor chip 3-1, a bias voltage unit 3-2 and an analog signal reading unit 3-3, and the EMCCD device backboard 3 (multiple models can be realized by replacing the EMCCD sensor chip 3-1) is connected with a system power supply unit 4-1, a transfer clock driving unit 4-5, a multiplication clock driving unit 4-6 and a low-pass filtering unit 4-7 on the bottom plate 4 through connectors. The low-pass filtering unit 4-7 receives the analog signal output by the analog signal reading unit 3-3, then is connected with the related double-sampling A/D conversion unit 4-8 for analog-to-digital conversion, and finally is transmitted to the FPGA control unit 4-2 through the level conversion unit 4-9. The EMCCD device backboard 3 is connected with the lens 1 through a fixing structure. The computer 2 comprises a display unit 2-1, a serial port software unit 2-2 and an image acquisition card unit 2-3. The serial port software unit 2-2 is connected with the serial port control unit 4-3 and used for sending instructions; the image acquisition card unit 2-3 is connected with the Cameralink output interface unit 4-10 and is used for receiving image data.

The universal EMCCD single-board camera system is used as an electronic system in a test system, and the direct imaging process of the camera system comprises the following steps: a driver program which is compiled by a Verilog hardware language and is adaptive to a specific EMCCD sensor chip 3-1 is burnt into an FPGA control unit 4-2, the FPGA control unit 4-2 generates different time sequence control signals required by the work of the EMCCD sensor chip 3-1, a part of the time sequence control signals pass through a transfer clock driving unit 4-5, and a part of the time sequence control signals pass through a multiplication clock driving unit 4-6 to obtain a driving signal adaptive to the EMCCD sensor chip 3-1. The system power supply unit 4-1 generates bias voltage required by the EMCCD sensor chip 3-1 through the bias voltage unit 3-2, the EMCCD sensor chip 3-1 generates a point packet representing image data after receiving correct driving signals and direct current bias, and the point packet is converted and output into analog image data signals which are expressed as weak analog level signals. The driving capability of the analog level signal is improved through the analog signal reading unit 3-3, and then the analog level signal is connected to the low-pass filtering unit 4-7 for filtering, denoising and amplifying, and the process is called as preprocessing. The preprocessed analog image data signals enter a related double-sampling A/D conversion unit 4-8 for sampling and analog-to-digital conversion, due to the difference of level standards, the analog image data signals need to be sent to an FPGA control unit 4-2 for buffering through a level conversion unit 4-9 after being sampled and analog-to-digital converted, and the FPGA control unit 4-2 reads out the buffered data to a Cameralink output interface unit 4-10 in sequence. The Cameralink output interface units 4-10 are connected with the computer 2 by cables, and finally imaging is carried out. If some parameters need to be controlled and changed, the FPGA control unit 4-2 changes the corresponding register to change after receiving and decoding the control instruction of the serial port control unit 4-3.

The universal EMCCD single-board camera system is used as an electronic system in a test system, and various parameters and working modes of the camera system need to be controlled in the imaging of the camera system. The FPGA control unit 4-2 receives the instruction of the computer 2 through the serial port control unit 4-3 to control the parameters of pixel rate, integration time, multiplication gain, output channel selection and the like. The serial port control unit 4-3 adopts RS232 protocol, 40 bits are transmitted each time, wherein the high 8 bit zone bit and the low 32bit content bit, the zone bit is the item to be changed by the positioning system, the content bit is the content that tells the system to change the positioned item into specific content. The 40-bit instruction sent by the serial port control unit 4-3 is cached in the FPGA control unit 4-2, the FPGA control unit 4-2 reads the instruction, the value of different registers is changed, the different registers correspond to different items, and the content of the item is correspondingly changed by changing the value of the register. Specifically, the pixel rate is changed by changing a register corresponding to a clock frequency, the integration time is changed by changing a register corresponding to delay time after the transfer of a packet of each frame of image points, the multiplication gain is changed by changing a register corresponding to an input amplitude of a DAC, and the selection of an output channel is controlled by changing a register corresponding to a phase of a timing signal.

With reference to fig. 1, the universal EMCCD single-board camera system of the present invention can also be used as a camera system for demonstrating imaging. Besides the above-mentioned component units and connections, the device also comprises a DDR2 memory unit 4-4 and a Cameralink input interface unit 4-11, and a DDR2 memory unit 4-4 is connected with the FPGA control unit 4-2 for storing image data. The Cameralink input interface unit 4-11 is connected with the FPGA control unit 4-2 and is used for receiving an external input data stream. The FPGA control unit 4-2 stores the EMCCD image data to the DDR2 storage unit 4-4. Through the control of the DDR2 memory cell 4-4, the reading and writing of video data signals are completed, and finally some simple image processing is completed. The universal EMCCD single-board camera system can also be used for receiving and processing video data streams, and the specific implementation flow is as follows: an external video data signal is input to the FPGA control unit 4-2 through the Cameralink input interface unit 4-11, and stored in the DDR2 storage unit 4-4 by the FPGA control unit 4-2. Through the control of the DDR2 memory cell 4-4, the reading and writing of video data signals are completed, and finally some simple image processing is completed. And may also be processed with EMCCD image data output by the camera system itself.

The system power supply unit 4-1 comprises four parts, and the system adopts the LDO mode to supply power. The power supply V1 part generates +3.3V, +2.5V, +1.8V, +1.2V and the like through LDO power chips TPS74401, MSK5230 and the like for the FPGA control unit 4-2 to use; +3.3V is also used by the CameraLink input interface unit 4-11, the CameraLink output interface unit 4-10, the serial port control unit 4-3 and the level conversion unit 4-9; +3.3V and +1.8V generate +0.9V for DDR2 memory cells 4-4 to use through TPS 51200; the power supply V2 generates +5V, +12V and-5V to supply power to the transfer clock driving unit 4-5 and the related double-sampling A/D conversion unit 4-8 through the LDO power supply chips MSK5201, MSK5231, LM137 and the like. The power supply V3 part supplies power to the high-voltage operational amplifier part of the multiplication clock driving unit 4-6 through a pi-type filter consisting of magnetic bead capacitors; the power supply V4 part generates +28V through MSK5230 to supply power to the bias voltage unit 3-2 part, and the power is supplied to the EMCCD sensor chip 3-1 after being subjected to resistance voltage division.

The FPGA control unit 4-2 of the invention controls the work of the whole system, Verilog hardware codes are needed to be written into the FPGA control unit 4-2 before the work, and figure 2 is the composition of the whole system codes. When the system needs to be used as an electronic system for testing for imaging, the FPGA control unit 4-2 generates a correct and strict time sequence driving signal and sends the correct and strict time sequence driving signal to the transfer clock driving unit 4-5 and the multiplication clock driving unit 4-6 to obtain a driving signal required by the EMCCD sensor chip 3-1; and receiving image signals output by the related double-sampling A/D conversion units 4-8 and the level conversion units 4-9 for buffering and transmitting data to the computer 2 for imaging according to a Cameralink interface protocol. When the system needs to be used as a demonstration camera for imaging, the FPGA control unit 4-2 buffers an image signal to the DDR2 storage unit 4-4 for post processing. FPGA control unit 4-2 may also accept image data input by Cameralink input interface unit 4-11 and buffer it to DDR2 memory unit 4-4 for post-processing.

The core chip used by the transfer clock driving unit 4-5 of the present invention is EL 7457. The EL7457 can receive a timing pulse signal generated by the FPGA control unit 4-2, perform level conversion and output the timing pulse signal to a transfer clock driving signal meeting the requirements of the EMCCD sensor chip 3-1; the invention uses 4 EL7457 sheets to lead out 16 paths of transfer clock driving signals, wherein 8 paths are added with downward clamping circuits after the level conversion unit, and the other 8 paths have no negative voltage clamping. The total swing amplitude can reach-5-12V, and the working requirements of most of EMCCD sensor chips can be met.

Referring to fig. 3, the multiplying clock driving unit 4-6 of the present invention includes a DAC part, a low-voltage filtering operational amplifier part, a high-voltage operational amplifier part, and a clamp circuit part. The FPGA control unit 4-2 generates 14 pairs of differential data signals, 1 pair of differential clock signals and 1 single-ended control signal required by the DAC. The DAC converts the digital signals into analog sine-like wave signals after receiving the digital signals. The low-voltage filtering operational amplifier part carries out smoothing processing on the signal and then sends the signal to the high-voltage operational amplifier part for amplification processing, and a multiplication driving signal meeting the requirement of the work amplitude of the EMCCD sensor is obtained. And finally, the signal is transmitted to an EMCCD device backboard 3 to drive an EMCCD sensor chip 3-1 after passing through an adjustable upward clamping circuit. The multiplication clock driving unit 4-6 only comprises one multiplication channel, so the method is not suitable for imaging of the multi-channel EMCCD.

The EMCCD device backboard 3 comprises an EMCCD sensor chip 3-1, a bias voltage unit 3-2 and an analog signal reading unit 3-3. The transfer clock driving unit 4-5 and the multiplication clock driving unit 4-6 are connected to the backplane 3 through connectors, and the generated timing driving signals are directly supplied to the EMCCD sensor chip 3-1. The +28V generated by the power supply V4 is connected to the backboard 3 through a connector, and different bias voltages required by the EMCCD sensor chip 3-1 are generated through resistance voltage division. The EMCCD sensor chip 3-1 generates photo-generated electrons under the action of the clock driving signal and the bias voltage driving signal, and outputs an analog image signal from a read register inside the chip. The image signal is supplied to an analog signal read out unit 3-3, and after the driving capability is improved, the image signal is outputted to a low pass filter unit 4-7 on a bottom plate 4. The analog signal readout unit 3-3 employs an operational amplifier ADA4800 by ADI for CCD output, improves the driving capability with almost no analog signal distortion, and can avoid introduction of noise of a later stage circuit.

With reference to fig. 4, the low-pass filtering units 4-7 adopt a structure in which two second-order active low-pass filters are cascaded to form a fourth-order low-pass filter. When the EMCCD sensor chip works, a video analog signal output by the EMCCD sensor chip 3-1 is input into the low-pass filtering unit 4-7 after passing through the ADA4800 for improving the driving capability. The low-pass filtering units 4-7 of the invention adopt LMH6715 chips which are composed of two identical operational amplifiers, and each part is matched with a proper resistance-capacitance to form a low-pass filter. The signal is output after completing the impedance conversion and filtering amplification functions from the low-pass filtering units 4-7 and enters the related double-sampling A/D conversion units 4-8

Referring to fig. 5, the correlated double sampling a/D conversion unit 4-8 selects the adc ds1410 chip of the original DATEL company, and pins 3, 4, and 5 of the chip are analog signals sent from the low pass filter unit 4-7 connected in different modes; the No. 10 pin to the No. 24 pin are 14-bit parallel digital signals and one full scale mark signal after ADC conversion; pin 27 is the data valid signal; pins 25 and 26 receive signals such as sampling points and the like sent by the FPGA control unit 4-2; 30. pin 31 is used to control the clock frequency at which the chip operates.

With reference to fig. 6, since the digital signal output by the adcs 1410 is selected to be at 5V logic level, and the FPGA accepts 3.3V logic level, level shifting units 4-9 are added. The present invention employs SN74ALVC164245 from TI corporation. In addition to the parallel output of 14-bit data signals, the ADCDS1410 also outputs 2-bit flag signals, and the SN74ALVC164245 supports 16-channel parallel conversion, so that the problem of asynchronization among signals caused by chip elements can be eliminated.

The Cameralink output interface unit 4-10 transmits data in a typical Base mode, and outputs 14-bit data signals buffered by the FPGA control unit 4-2 as 5 pairs of differential signals conforming to the Cameralink protocol by using the coding chip DS90CR 287. Its advantages are high anti-interference power, long transmission distance and universal image transmission interface. Similarly, the Cameralink input interface unit 4-11 of the present invention also adopts the Base mode to transmit data, and uses the decoding chip DS90CR288 to decode five pairs of externally input differential signals into single-ended data signals with 14 bits, which are buffered by the FPGA control unit 4-2, so as to facilitate the post-processing.

DDR2 memory cell 4-4 is used primarily for storage of image data. Due to the fact that data of one frame of image is large, when the complete one frame of image is needed to calculate the relevant parameters, the buffer capacity of the FPGA is not enough, and the FPGA needs to be stored in the DDR 2. The DDR2 memory cell 4-4 of the invention is composed of 2 pieces of MT47H64M16HR-3IT DDR2 chips of MICRON company, the total capacity is 2 Gbit; 2 DDR2 constitute 32bit bus mode, FPGA and DDR2 between the read and write data bandwidth up to 8.5 Gb; such a configuration can meet most video processing requirements. DDR2 normal operation requires the address and control lines to be supplied with termination voltage VTT and DDR2 reference voltage VREF, both 0.9V, with the present invention using TPS51200 dedicated to DDR2 to supply power.

The computer 1 is mainly used for collecting and displaying image data, and the CameraLink collecting card is arranged on a back board slot of the computer 1 and matched with corresponding software, so that the frame frequency, the resolution ratio and other information of the image data can be displayed in real time, and images or video sequences can be stored on the computer 1.

By replacing different EMCCD device backplates 3 and the convenience of the Verilog hardware language, the invention can support the work requirements of EMCCDs of various models and realize the driving imaging, image processing and testing of EMCCDs of different models. Fig. 7 and 8 show the imaging effect of different models of EMCCD used outdoors in the invention. The invention also supports DDR2 reading and writing and processing, and FIG. 9 shows the comparison before and after image processing, and the image processed by the invention is clearer.