阅读说明：本技术 接收器电路 (Receiver circuit ) 是由 张元硕 高子铭 于 2018-08-24 设计创作，主要内容包括：本发明提出一种收发器中的接收器电路,其包含：一校正电路,设置成依据一同相检测信号与一正交相检测信号进行一同相/正交相不匹配校正运作,以产生一个或多个补偿参数；一参数储存电路；一干扰检测电路,设置成依据该同相检测信号与该正交相检测信号,产生一信号干扰比估算值；以及一接收端控制电路,设置成依据该信号干扰比估算值来判断是否要舍弃该一个或多个补偿参数,其中,只有在该信号干扰比估算值超过一预定临界值的情况下,该接收端控制电路才会把该一个或多个补偿参数储存至该参数储存电路中。(The present invention provides a receiver circuit in a transceiver, which comprises: a correction circuit configured to perform an in-phase/quadrature-phase mismatch correction operation according to an in-phase detection signal and a quadrature-phase detection signal to generate one or more compensation parameters; a parameter storage circuit; an interference detection circuit configured to generate a signal-to-interference ratio estimate based on the in-phase detection signal and the quadrature-phase detection signal; and a receiver control circuit configured to determine whether to discard the one or more compensation parameters based on the sir estimate, wherein the receiver control circuit stores the one or more compensation parameters in the parameter storage circuit only if the sir estimate exceeds a predetermined threshold.)

1. A receiver circuit in a transceiver, comprising:

a correction circuit configured to perform an in-phase/quadrature-phase mismatch correction operation according to an in-phase detection signal and a quadrature-phase detection signal to generate one or more compensation parameters;

a parameter storage circuit;

an interference detection circuit configured to generate a signal-to-interference ratio estimate based on the in-phase detection signal and the quadrature-phase detection signal; and

a receiving end control circuit, coupled to the calibration circuit, the parameter storage circuit, and the interference detection circuit, and configured to determine whether to discard the one or more compensation parameters according to the sir estimate, wherein the receiving end control circuit stores the one or more compensation parameters in the parameter storage circuit only if the sir estimate exceeds a predetermined threshold.

2. The receiver circuit of claim 1, further comprising:

an analog signal processing circuit configured to process a signal received by a receiving antenna of the transceiver;

an in-phase signal processing circuit configured to generate the in-phase detection signal according to a signal output by the analog signal processing circuit; and

a quadrature phase signal processing circuit configured to generate the quadrature phase detection signal according to a signal output by the analog signal processing circuit.

3. The receiver circuit of claim 2 wherein the operation of the jammer detection circuit to generate the sir estimate is performed simultaneously with the operation of the correction circuit to generate the one or more compensation parameters.

4. The receiver circuit of claim 2, wherein the receiver control circuit instructs a transmitter circuit of the transceiver to transmit a predetermined signal at a specific time point through a transmitter antenna, the in-phase signal processing circuit generates the in-phase detection signal according to the signal output by the analog signal processing circuit at the specific time point, and the quadrature-phase signal processing circuit generates the quadrature-phase detection signal according to the signal output by the analog signal processing circuit at the specific time point.

5. The receiver circuit of claim 2, wherein the interference detection circuit comprises:

a time domain signal strength estimation circuit configured to generate a time domain signal strength estimation value corresponding to a target frequency according to the in-phase detection signal and the quadrature-phase detection signal;

a first frequency domain signal strength estimation circuit configured to generate a frequency domain target signal strength estimation value corresponding to the target frequency according to the in-phase detection signal and the quadrature-phase detection signal;

a second frequency-domain signal strength estimation circuit configured to generate a frequency-domain mirror frequency signal strength estimation value corresponding to a mirror frequency of the target frequency according to the in-phase detection signal and the quadrature-phase detection signal; and

a sir estimation circuit, coupled to the time domain signal strength estimation circuit, the first frequency domain signal strength estimation circuit, and the second frequency domain signal strength estimation circuit, configured to generate the sir estimate based on the time domain signal strength estimate, the frequency domain target signal strength estimate, and the frequency domain mirror frequency signal strength estimate.

6. The receiver circuit of claim 5, wherein the SIR estimation circuit calculates a frequency-domain wide-band interference strength estimate based on the time-domain signal strength estimate, the frequency-domain target signal strength estimate, and the frequency-domain mirror frequency signal strength estimate, and divides the frequency-domain target signal strength estimate by the frequency-domain wide-band interference strength estimate to generate the SIR estimate.

7. The receiver circuit of claim 2, wherein the interference detection circuit comprises:

a first frequency domain signal strength estimation circuit configured to generate a frequency domain target signal strength estimation value corresponding to a target frequency according to the in-phase detection signal and the quadrature-phase detection signal;

a second frequency domain signal strength estimation circuit configured to generate a frequency domain narrowband interference strength estimation value corresponding to a narrowband interference frequency according to the in-phase detection signal and the quadrature-phase detection signal; and

a sir estimation circuit, coupled to the first and second frequency domain signal strength estimation circuits, configured to generate the sir estimate based on the frequency domain target signal strength estimate and the frequency domain narrowband interference strength estimate.

8. The receiver circuit of claim 7, wherein the sir estimation circuit divides the frequency domain target signal strength estimate by the frequency domain narrowband interference strength estimate to produce the sir estimate.

Technical Field

The present invention relates to a transceiver, and more particularly, to a receiver circuit capable of determining whether to discard an in-phase/quadrature phase mismatch compensation parameter according to a signal-to-interference ratio.

Background

In many receiver circuits of wireless communication devices, there are often gain mismatch (gain mismatch) and/or phase mismatch (phase mismatch) between an in-phase signal (I signal) and a quadrature signal (Q signal), i.e., so-called in-phase/quadrature phase mismatch (I/Q mismatch).

The mismatch between the in-phase and the quadrature phase causes image frequency interference (mirror frequency interference), which results in a decrease in the signal-to-noise ratio (SNR) of the receiver circuit, and thus reduces the data transmission throughput (throughput) of the overall system.

Disclosure of Invention

In view of the above, how to effectively improve the in-phase/quadrature phase mismatch in the receiver circuit is a problem to be solved.

This specification provides an embodiment of a receiver circuit in a transceiver, comprising: a correction circuit configured to perform an in-phase/quadrature-phase mismatch correction operation according to an in-phase detection signal and a quadrature-phase detection signal to generate one or more compensation parameters; a parameter storage circuit; an interference detection circuit configured to generate a signal-to-interference ratio estimate based on the in-phase detection signal and the quadrature-phase detection signal; and a receiver control circuit, coupled to the calibration circuit, the parameter storage circuit, and the interference detection circuit, configured to determine whether to discard the one or more compensation parameters according to the sir estimate, wherein the receiver control circuit stores the one or more compensation parameters in the parameter storage circuit only if the sir estimate exceeds a predetermined threshold.

One of the advantages of the above embodiments is that whether to retain the compensation parameter generated by the calibration circuit is determined according to the sir estimate, which can prevent the compensation parameter generated under the influence of interference from being used in subsequent normal operations, thereby more effectively reducing the in-phase/quadrature-phase mismatch of the receiver circuit.

Another advantage of the above embodiments is that the signal-to-noise ratio of the receiver circuit can be improved, so that the overall data transmission capacity of the transceiver can be improved.

Other advantages of the present invention will be described in more detail with reference to the following description and drawings.

Drawings

Fig. 1 is a simplified functional block diagram of a transceiver according to an embodiment of the present invention.

Fig. 2 is a simplified functional block diagram of an embodiment of the interference detection circuit of fig. 1.

FIG. 3 is a simplified functional block diagram of another embodiment of the interference detection circuit of FIG. 1.

Detailed Description

The embodiments of the present invention will be described with reference to the accompanying drawings. In the drawings, the same reference numbers indicate the same or similar elements or process flows.

Fig. 1 is a simplified functional block diagram of a transceiver 100 according to an embodiment of the present invention. The transceiver 100 includes a receiver circuit 110 and a transmitter circuit 120. In normal operation, the receiver circuit 110 processes the Rx signal Rx from the Rx antenna 102, and the transmitter circuit 120 generates the Tx signal Tx to be transmitted through the Tx antenna 104.

Before normal operation, the receiver circuit 110 performs an in-phase/quadrature phase mismatch correction procedure to eliminate or reduce the in-phase/quadrature phase mismatch in the receiver circuit 110.

As shown in fig. 1, the receiver circuit 110 in this embodiment includes an analog signal processing circuit 111, an in-phase signal processing circuit 112, a quadrature-phase signal processing circuit 113, a calibration circuit 114, a parameter storage circuit 115, an interference detection circuit 116, and a receiver control circuit 117.

The analog signal processing circuit 111 is arranged to process signals received by the receiving antenna 102. The in-phase signal processing circuit 112 is coupled to the analog signal processing circuit 111 and configured to generate an in-phase detection signal DI according to a signal output by the analog signal processing circuit 111. The quadrature-phase signal processing circuit 113 is coupled to the analog signal processing circuit 111 and configured to generate a quadrature-phase detection signal DQ according to a signal output by the analog signal processing circuit 111.

The calibration circuit 114 is coupled to the in-phase signal processing circuit 112 and the quadrature-phase signal processing circuit 113, and configured to perform an in-phase/quadrature-phase mismatch calibration operation according to the in-phase detection signal DI and the quadrature-phase detection signal DQ to generate one or more compensation parameters IQK.

For example, the calibration circuit 114 may calculate the power of the image frequency component (image frequency component) caused by the in-phase/quadrature phase mismatch according to the in-phase detection signal DI and the quadrature-phase detection signal DQ, and perform various suitable calibration algorithms to adjust the related compensation coefficient in the calibration circuit 114 and/or the gain value of the related amplifier (not shown in the figure) in the analog signal processing circuit 111, so as to minimize the power of the image frequency component. When the calibration circuit 114 reduces the power of the aforementioned mirror frequency component to a minimum value, the current in-phase/quadrature-phase mismatch calibration operation is completed. At this time, the correction circuit 114 may output the obtained compensation coefficient and/or gain value of the associated amplifier in a suitable data format as the aforementioned one or more compensation parameters IQK.

The interference detection circuit 116 is coupled to the in-phase signal processing circuit 112 and the quadrature-phase signal processing circuit 113, and configured to perform an interference detection (interference detection) operation according to the in-phase detection signal DI and the quadrature-phase detection signal DQ to generate a SIR estimate corresponding to an interference level in a current environment of the transceiver 100.

The generation of the SIR estimate SIR by the SIR detection circuit 116 is performed simultaneously with the generation of the one or more compensation parameters IQK by the correction circuit 114.

The receiver control circuit 117 is coupled to the calibration circuit 114, the parameter storage circuit 115, and the interference detection circuit 116, and configured to determine whether to discard the compensation parameter IQK generated by the current operation of the calibration circuit 114 according to the SIR estimate SIR generated by the current operation of the interference detection circuit 116. In operation, the receiver control circuit 117 compares the SIR estimate generated by the interference detection circuit 116 with a predetermined threshold to determine whether the interference level in the current environment of the transceiver 100 is high or low.

In this embodiment, the receiver control circuit 117 stores one or more compensation parameters IQK generated by the current operation of the calibration circuit 114 into the parameter storage circuit 115 only when the SIR exceeds a predetermined threshold. In subsequent normal operation, the calibration circuit 114 and/or the associated amplifiers in the analog signal processing circuit 111 may be operated according to the one or more compensation parameters IQK stored in the parameter storage circuit 115 to reduce or eliminate the in-phase/quadrature-phase mismatch in the receiver circuit 110.

On the contrary, if the SIR is lower than the predetermined threshold, the receiver control circuit 117 discards the compensation parameter IQK generated by the current operation of the calibration circuit 114 and does not store the compensation parameter in the parameter storage circuit 115. This is because there are many deviations in the compensation parameters generated by the correction circuit 114 under the influence of disturbances in the current environment. If the calibration circuit 114 and/or the associated amplifiers in the analog signal processing circuit 111 use the biased error compensation parameters in the subsequent normal operation, the performance of the receiver circuit 110 is degraded by the in-phase/quadrature-phase mismatch.

In practice, the analog signal processing circuit 111, the in-phase signal processing circuit 112, the quadrature-phase signal processing circuit 113, and the transmission circuit 120 can be implemented by various appropriate conventional circuits. The parameter storage circuit 115 may be implemented using any suitable non-volatile storage device. The calibration circuit 114 and the interference detection circuit 116 can be implemented by various suitable circuits with digital computing capability. The receiver control circuit 117 may be implemented using various suitable digital processing circuits.

In addition, the different functional blocks of the transceiver 100 can be implemented by different circuits, respectively, or can be integrated into a single circuit chip. For example, different functional blocks in the receiver circuit 110 may be integrated into a single circuit chip, and the transmitter circuit 120 may be implemented in another circuit chip. Alternatively, the receiver circuit 110 and the transmitter circuit 120 may be integrated into a single circuit chip.

Referring to fig. 2, a simplified functional block diagram of an embodiment of the interference detection circuit 116 of fig. 1 is shown.

In the embodiment of fig. 2, the interference detection circuit 116 includes a time-domain signal strength estimation circuit 210, a first frequency-domain signal strength estimation circuit 220, a second frequency-domain signal strength estimation circuit 230, and a sir estimation circuit 240. The time-domain signal strength estimation circuit 210, the first frequency-domain signal strength estimation circuit 220, and the second frequency-domain signal strength estimation circuit 230 are coupled to the output terminals of the in-phase signal processing circuit 112 and the quadrature-phase signal processing circuit 113, and the sir estimation circuit 240 is coupled to the output terminals of the time-domain signal strength estimation circuit 210, the first frequency-domain signal strength estimation circuit 220, and the second frequency-domain signal strength estimation circuit 230.

When the receiver circuit 110 needs to perform the in-phase/quadrature-phase mismatch calibration procedure, the receiver control circuit 117 instructs the transmitter circuit 120 to transmit a predetermined signal Tst with a given frequency through the transmitter antenna 104 at a specific time, so that the receiver antenna 102 receives the signal transmitted by the transmitter antenna 104.

At this time, the analog signal processing circuit 111 processes the signal received by the receiving antenna 102 at the specific time point, and sends the processed signal to the in-phase signal processing circuit 112 and the quadrature-phase signal processing circuit 113. The in-phase signal processing circuit 112 generates the in-phase detection signal DI according to the signal output by the analog signal processing circuit 111 at the specific time point, and the quadrature-phase signal processing circuit 113 generates the quadrature-phase detection signal DQ according to the signal output by the analog signal processing circuit 111 at the specific time point.

In the jammer detection circuit 116, the time domain signal strength estimation circuit 210 is configured to generate a time domain signal strength estimation value corresponding to a target frequency according to the in-phase detection signal DI and the quadrature-phase detection signal DQ. In the present embodiment, the aforementioned target frequency is the frequency of the predetermined signal Tst.

The first frequency-domain signal strength estimation circuit 220 is configured to generate a frequency-domain target signal strength estimation value corresponding to a target frequency according to the in-phase detection signal DI and the quadrature-phase detection signal DQ.

The second frequency-domain signal strength estimation circuit 230 is configured to generate a frequency-domain signal strength estimation value corresponding to a specific frequency according to the in-phase detection signal DI and the quadrature-phase detection signal DQ.

In the present embodiment, the SIR estimation circuit 240 is configured to generate an SIR estimation value corresponding to a wide band interference (wideband interference) level of the current environment of the transceiver 100 according to the estimation values generated by the time-domain signal strength estimation circuit 210, the first frequency-domain signal strength estimation circuit 220, and the second frequency-domain signal strength estimation circuit 230, or generate an SIR estimation value corresponding to a narrow band interference (narrowband interference) level of the current environment of the transceiver 100 at a specific frequency point according to the estimation values generated by both the first frequency-domain signal strength estimation circuit 220 and the second frequency-domain signal strength estimation circuit 230.

If the receiver control circuit 117 wants to measure the wide-band interference level in the current environment of the transceiver 100, the second frequency-domain signal strength estimation circuit 230 can generate a frequency-domain mirror frequency signal strength estimation value corresponding to a mirror frequency of the target frequency according to the in-phase detection signal DI and the quadrature-phase detection signal DQ according to the indication of the receiver control circuit 117.

In this case, the SIR estimation circuit 240 may generate an SIR estimate corresponding to the level of wideband interference in the current environment of the transceiver 100 according to the time-domain signal strength estimate, the frequency-domain target signal strength estimate, and the frequency-domain mirror frequency signal strength estimate.

In operation, the sir estimation circuit 240 may calculate a frequency-domain wide-band sir estimate based on the time-domain sir estimate, the frequency-domain target sir estimate, and the frequency-domain mirror frequency sir estimate. For example, the sir estimation circuit 240 may generate the frequency-domain wide-band sir estimate according to the following equation (1):

frequency domain wide frequency interference intensity estimated value-N x time domain signal intensity estimated value-frequency domain target signal intensity estimated value-frequency domain mirror frequency signal intensity estimated value … … (1)

Where N is the number of times of sampling both the in-phase detection signal DI and the quadrature-phase detection signal DQ.

The SIR estimation circuit 240 then divides the frequency-domain target SIR by the frequency-domain wide-band SIR to generate an SIR estimate that reflects the level of wide-band interference in the current environment of the transceiver 100.

The receiver control circuit 117 may compare the SIR estimate with a first predetermined threshold to determine whether the level of wideband interference in the current environment of the transceiver 100 is high or low. In this embodiment, if the SIR is greater than or equal to the first predetermined threshold, it indicates that the current level of wideband interference is still within an acceptable range. Otherwise, if the SIR estimate is lower than the first predetermined threshold, it represents that the current level of wideband interference is too high, which may cause the compensation parameter generated by the correction circuit 114 to be unreliable.

Therefore, the receiver control circuit 117 may store the one or more compensation parameters IQK generated by the current operation of the correction circuit 114 into the parameter storage circuit 115 for the correction circuit 114 and/or the associated amplifiers in the analog signal processing circuit 111 to use in the subsequent normal operation if the SIR exceeds the first predetermined threshold.

On the other hand, if the receiver control circuit 117 wants to measure the narrowband interference level of the current environment of the transceiver 100 at the specific frequency point, the receiver control circuit 117 may send the specific frequency point of interest to the second frequency-domain signal strength estimation circuit 230 in the form of appropriate parameters or data, so that the second frequency-domain signal strength estimation circuit 230 generates a frequency-domain narrowband interference strength estimation value corresponding to a narrowband interference frequency according to the in-phase detection signal DI and the quadrature-phase detection signal DQ, wherein the narrowband interference frequency corresponds to the specific frequency point of interest of the receiver control circuit 117.

In this case, the SIR estimation circuit 240 may divide the frequency-domain target SIR estimate by the frequency-domain narrowband SIR estimate to generate an SIR estimate that reflects the level of narrowband interference in the particular frequency bin in which the transceiver 100 is currently located.

The receiver control circuit 117 may compare the SIR estimate with a second predetermined threshold to determine whether the narrowband interference level of the current environment of the transceiver 100 is at a specific frequency point. In this embodiment, if the SIR is greater than or equal to the second predetermined threshold, it indicates that the current level of narrowband interference at the specific frequency point is still within an acceptable range. Conversely, if the SIR estimate is below the second predetermined threshold, it indicates that the narrowband interference level of the transceiver 100 at the specific frequency point is too high, which may cause the compensation parameter currently generated by the correction circuit 114 to be unreliable.

Therefore, the receiver control circuit 117 may store the one or more compensation parameters IQK generated by the current operation of the correction circuit 114 into the parameter storage circuit 115 for the correction circuit 114 and/or the associated amplifiers in the analog signal processing circuit 111 to use in the subsequent normal operation if the SIR exceeds the second predetermined threshold.

As can be seen from the foregoing description, discarding the compensation parameter IQK generated by the correction circuit 114 during the current operation when the SIR estimate generated by the SIR detection circuit 116 is lower than the relevant threshold value can effectively prevent the correction circuit 114 and/or the relevant amplifier in the analog signal processing circuit 111 from using the wrong compensation parameter during the subsequent normal operation. By doing so, the degree of in-phase/quadrature phase mismatch of the receiver circuit 110 can be more effectively reduced.

As a result, the signal-to-noise ratio of the receiver circuit 110 can be effectively improved, and the overall data transmission capacity of the transceiver 100 can be improved.

It should be noted that the circuit architecture in FIG. 2 is only an exemplary embodiment and is not intended to limit the practical implementation of the present invention.

For example, in an application where the receiver control circuit 117 only needs to determine whether to discard the compensation parameter currently generated by the calibration circuit 114 according to the narrowband interference level of the transceiver 100 in a specific frequency point, the time-domain signal strength estimation circuit 210 in fig. 2 may be omitted to form the architecture shown in fig. 3.

The foregoing descriptions regarding the connection, implementation, operation, and related advantages of the other elements in fig. 2 also apply to the embodiment in fig. 3. For the sake of brevity, the description is not repeated here.

Certain terms are used throughout the description and claims to refer to particular elements, and those skilled in the art may refer to like elements by different names. In the present specification and claims, the difference in name is not used as a means for distinguishing elements, but the difference in function of the element is used as a reference for distinguishing. In the description and claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. Also, the term "coupled" is intended to include any direct or indirect connection. Therefore, if a first element is coupled to a second element, the first element can be directly connected to the second element through an electrical connection or a signal connection such as wireless transmission or optical transmission, or indirectly connected to the second element through another element or a connection means.

The description of "and/or" as used in this specification is inclusive of any combination of one or more of the items listed. In addition, any reference to singular is intended to include the plural unless the specification specifically states otherwise.

The above are only preferred embodiments of the present invention, and all equivalent changes and modifications made by the claims of the present invention should be covered by the present invention.

[ notation ] to show

100 transceiver (transceiver)

102 receiving antenna (receiving antenna)

104 transmitting antenna (transmitting antenna)

110 receiver circuit (receiver circuit)

111 analog signal processing circuit (analog signal processing circuit)

112 in-phase signal processing circuit (in-phase signal processing circuit)

113 quadrature phase signal processing circuit (quadrature signal processing circuit)

114 correction circuit (calibration circuit)

115 parameter storage circuit (parameter storage circuit)

116 interference detection circuit (interference detection circuit)

117 receive end control circuit (receiver control circuit)

120 transmitting circuit (transmitter circuit)

210 time-domain signal power estimation circuit (time-domain signal power estimation circuit)

220 first frequency-domain signal power estimation circuit (first frequency-domain signal power estimation circuit)

230 second frequency domain signal power estimation circuit (second frequency-domain signal power estimation circuit)

240 signal-to-interference ratio estimation circuit (signal-to-interference ratio estimation circuit)

DI in-phase detection signal (in-phase detection signal)

DQ Quadrature detection Signal

IQK Compensation parameter (compensation parameter)

SIR signal-to-interference ratio estimation (estimated signal-to-interference ratio)

Rx received Signal (received signal)

Tx Transmission Signal (Transmission Signal)

Tst predetermined signal (predetermined signal).