Single-key startup and shutdown and reset circuit
阅读说明：本技术 一种单键开关机与复位电路 (Single-key startup and shutdown and reset circuit ) 是由 张江 于 2019-10-30 设计创作，主要内容包括：本发明提供一种单键开关机与复位电路,包括三极管电路、与所述三极管电路相连接的MOS管电路以及与所述三极管电路、MOS管电路相连接的7404非门电路；所述三级管电路包括三极管Q2以及与所述三级管Q2相连接的电阻R4、电阻R5以及电容C1；所述三极管Q2的基极与7404非门电路一端相连接,且在该7404非门电路与三级管Q2基极的连接线路上串接有一电阻R3；所述三极管Q2的发射极接公共地；所述MOS管电路包括MOS管Q1,该MOS管Q1为P沟道增强型MOS管；且所述MOS管Q1的漏极接外部电源电压VBAT,MOS管Q1的源极接外部电源BAT,MOS管Q1的栅极接三极管Q2的集电极,实际应用过程中,可避免MCU程序跑飞而意外关机,也可以实现MCU任意状态的软硬件复位,产品电源不受影响。(The invention provides a single-key startup and shutdown and reset circuit, which comprises a triode circuit, an MOS (metal oxide semiconductor) tube circuit connected with the triode circuit and a 7404 NOT gate circuit connected with the triode circuit and the MOS tube circuit; the triode circuit comprises a triode Q2, a resistor R4, a resistor R5 and a capacitor C1, wherein the resistor R4, the resistor R5 and the capacitor C1 are connected with the triode Q2; the base electrode of the triode Q2 is connected with one end of a 7404 NOT gate circuit, and a resistor R3 is connected in series on a connecting line between the 7404 NOT gate circuit and the base electrode of a triode Q2; the emitter of the triode Q2 is connected with the common ground; the MOS tube circuit comprises an MOS tube Q1, and the MOS tube Q1 is a P-channel enhancement type MOS tube; and the drain electrode of the MOS tube Q1 is connected with an external power supply voltage VBAT, the source electrode of the MOS tube Q1 is connected with an external power supply BAT, and the grid electrode of the MOS tube Q1 is connected with the collector electrode of the triode Q2.)
1. A single bond switching on and shutting down and reset circuit which characterized in that: the circuit comprises a triode circuit, an MOS (metal oxide semiconductor) tube circuit connected with the triode circuit and a 7404 NOT gate circuit connected with the triode circuit and the MOS tube circuit; the triode circuit comprises a triode Q2, a resistor R4, a resistor R5 and a capacitor C1, wherein the resistor R4, the resistor R5 and the capacitor C1 are connected with the triode Q2; the base electrode of the triode Q2 is connected with one end of a 7404 NOT gate circuit, and a resistor R3 is connected in series on a connecting line between the 7404 NOT gate circuit and the base electrode of a triode Q2; the emitter of the triode Q2 is connected with the common ground; the MOS tube circuit comprises an MOS tube Q1, and the MOS tube Q1 is a P-channel enhancement type MOS tube; the drain of the MOS transistor Q1 is connected with an external power supply voltage VBAT, the source of the MOS transistor Q1 is connected with an external power supply BAT, and the gate of the MOS transistor Q1 is connected with the collector of the triode Q2; a first resistance circuit is connected between the source electrode and the grid electrode of the MOS transistor Q1 in parallel, and a resistor R1 is connected in series in the first resistance circuit; the base electrode of the triode Q2 is connected with the drain electrode of the MOS tube Q1 through a second resistor circuit, and the resistor R5 is connected in the second resistor circuit in series; a third resistor circuit and a first capacitor circuit are connected in parallel between the base electrode and the emitter electrode of the triode Q2; the resistor R4 is connected in series in the third resistor circuit; the capacitor C1 is connected in series in the first capacitor circuit; the grid electrode of the MOS tube Q1 is also connected with a diode circuit; a diode D1 and a control button SW1 are connected in series in the diode circuit, and the other end of the diode circuit, which is opposite to the grid of the MOS tube Q1, is connected with a common ground; the reset circuit is connected with the connecting part of the diode D1 of the diode circuit and the control button SW 1; a diode D2 is connected in series in the RESET circuit, and one end of the RESET circuit is connected with an MCU-RESET contact of an external chip; the other end of the 7404 NOT gate circuit relative to the base of the transistor Q2 is connected with a POWER-HOLD contact of an external chip.
2. The single key switch on/off and reset circuit of claim 1, wherein: the reset circuit is also connected with a fourth resistor circuit; a resistor R2 is connected in series in the fourth resistor circuit; and one end of the fourth resistor circuit is connected with an external power supply voltage VCC.
[ technical field ]
The invention relates to the technical field of startup and shutdown and reset circuits, in particular to a single-key startup and shutdown and reset circuit which can effectively avoid accidental shutdown caused by program runaway of an MCU (microprogrammed control unit), can realize software and hardware reset of the MCU in any state and can not influence a product power supply.
[ background art ]
Along with the popularization of intelligent home furnishing, modern intelligent equipment is smaller and smaller, and the performance is stronger and stronger. Many equipment all need accomplish energy-conserving as far as possible, so all be necessary in many times and shut down and reset function, because the volume problem of product, these two functions can be accomplished a button as far as possible.
At present, a common single-key switching on and off and reset circuit generally has the following principle: when the SW1 key is pressed, the grid of the Q1 PMOS is low, Q1 is conducted, VBAT has voltage, VBAT obtains voltage VCC supplied by the MCU through DCDC conversion, meanwhile, the MCU works to provide a continuous high level for POWER _ HOLD, so that the conduction state of Q1 is kept, after the key is released, the product is also powered, and the POWER _ HOLD outputs the low level to realize the shutdown function. However, this circuit has a serious drawback that the MCU must give a stable POWER _ HOLD high level signal, and once the MCU is disturbed by radiation or has a problem with its own program, the product will be powered down.
How to improve on the basis of the circuit to solve the defects is a problem which is frequently considered by a person skilled in the art, and a great deal of research and development and experiments are also carried out to obtain better results.
[ summary of the invention ]
In order to overcome the problems in the prior art, the invention provides a single-key startup and shutdown and reset circuit which can effectively avoid accidental shutdown caused by program runaway of an MCU (microprogrammed control unit), can also realize software and hardware reset of the MCU in any state, and has no influence on the power supply of a product.
The invention provides a single-key startup and shutdown and reset circuit, which comprises a triode circuit, an MOS (metal oxide semiconductor) tube circuit connected with the triode circuit and a 7404 NOT gate circuit connected with the triode circuit and the MOS tube circuit; the triode circuit comprises a triode Q2, a resistor R4, a resistor R5 and a capacitor C1, wherein the resistor R4, the resistor R5 and the capacitor C1 are connected with the triode Q2; the base electrode of the triode Q2 is connected with one end of a 7404 NOT gate circuit, and a resistor R3 is connected in series on a connecting line between the 7404 NOT gate circuit and the base electrode of a triode Q2; the emitter of the triode Q2 is connected with the common ground; the MOS tube circuit comprises an MOS tube Q1, and the MOS tube Q1 is a P-channel enhancement type MOS tube; the drain of the MOS transistor Q1 is connected with an external power supply voltage VBAT, the source of the MOS transistor Q1 is connected with an external power supply BAT, and the gate of the MOS transistor Q1 is connected with the collector of the triode Q2; a first resistance circuit is connected between the source electrode and the grid electrode of the MOS transistor Q1 in parallel, and a resistor R1 is connected in series in the first resistance circuit; the base electrode of the triode Q2 is connected with the drain electrode of the MOS tube Q1 through a second resistor circuit, and the resistor R5 is connected in the second resistor circuit in series; a third resistor circuit and a first capacitor circuit are connected in parallel between the base electrode and the emitter electrode of the triode Q2; the resistor R4 is connected in series in the third resistor circuit; the capacitor C1 is connected in series in the first capacitor circuit; the grid electrode of the MOS tube Q1 is also connected with a diode circuit; a diode D1 and a control button SW1 are connected in series in the diode circuit, and the other end of the diode circuit, which is opposite to the grid of the MOS tube Q1, is connected with a common ground; the reset circuit is connected with the connecting part of the diode D1 of the diode circuit and the
Preferably, the reset circuit is further connected with a fourth resistor circuit; a resistor R2 is connected in series in the fourth resistor circuit; and one end of the fourth resistor circuit is connected with an external power supply voltage VCC.
Compared with the prior art, the single-key on-off and reset circuit of the invention simultaneously arranges a triode circuit, an MOS tube circuit connected with the triode circuit and a 7404 NOT gate circuit connected with the triode circuit and the MOS tube circuit, the triode circuit comprises a triode Q2, a resistor R4, a resistor R5 and a capacitor C1 which are connected with the triode Q2, the base of the triode Q2 is connected with one end of the 7404 NOT gate circuit, a resistor R3 is connected in series with a connecting circuit of the 7404 NOT gate circuit and the base of a triode Q2, the emitter of the triode Q2 is connected with common ground, the MOS tube circuit comprises an MOS tube Q1, the MOS tube Q1 is a P-channel enhanced MOS tube, the drain of the MOS tube Q1 is connected with an external power supply voltage VBAT, the source of the MOS tube Q1 is connected with an external power supply, the gate of the MOS tube Q1 is connected with the collector of the triode Q2, and the circuit connection relationship of other parts is combined, in the practical application process, the accidental shutdown caused by the running away of the MCU program can be avoided, the software and hardware reset of the MCU in any state can be realized, and the product power supply is not influenced.
[ description of the drawings ]
Fig. 1 is a schematic diagram of a circuit connection structure of a conventional single-key power on/off and reset circuit.
Fig. 2 is a schematic diagram of a circuit connection structure of a single-key power on/off and reset circuit of the invention.
[ detailed description of the invention ]
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Referring to fig. 1 and fig. 2, a single-key power on/off and
The device is characterized in that a triode circuit, an MOS tube circuit connected with the triode circuit and a 7404 NOT gate circuit connected with the triode circuit and the MOS tube circuit are arranged at the same time, the triode circuit comprises a triode Q2, a resistor R4, a resistor R5 and a capacitor C1 which are connected with the triode Q2, the base of the triode Q2 is connected with one end of the 7404 NOT gate circuit, a resistor R3 is connected in series on a connecting line of the 7404 NOT gate circuit and the base of the TRI tube Q2, the emitter of the triode Q2 is connected with the common ground, the MOS tube circuit comprises an MOS tube Q1, the MOS tube Q1 is a P-channel enhanced MOS tube, the drain of the MOS tube Q1 is connected with an external power supply voltage VBAT, the source of the MOS tube Q1 is connected with an external power supply BAT, the gate of the MOS tube Q1 is connected with the collector of the triode Q2, and the circuit connection relation of other parts is combined, so that the device can avoid the MCU from accidentally flying off due to the, and software and hardware reset of the MCU in any state can be realized, and the power supply of the product is not influenced.
The POWER _ HOLD is in low level when the circuit is started, so that accidental shutdown caused by interference reset of the MCU can be avoided. The principle is as follows:
when the SW1 key is pressed and the gate of Q1 PMOS is low, Q1 is turned on and VBAT has voltage. VBAT obtains the voltage VCC supplied by the MCU through DCDC conversion. Meanwhile, the MCU works, and a high-level signal for POWER _ HOLD is not needed at the moment. After the base of Q2 charges C1 through R5, a voltage of about 0.7V is obtained through voltage division of R5 and R4, Q2 is turned on, and Q1 is kept on. And the POWER _ HOLD outputs high level to realize the shutdown function.
Preferably, the reset circuit is further connected with a fourth resistor circuit; a resistor R2 is connected in series in the fourth resistor circuit; and one end of the fourth resistor circuit is connected with an external power supply voltage VCC.
A resistor R5 and a capacitor C1 are added to the base of Q2, the other end of R5 is connected to VBAT, and the other end of C1 is connected to ground. The POWER _ HOLD POWER-on HOLD signal is coupled to the base of Q2 through R3 through the 7404 NOT gate circuit.
Compared with the prior art, the single-key startup/shutdown and
The above-described embodiments of the present invention do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.
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