阅读说明：本技术 低功耗快响应电平变换电路 (Low-power-consumption quick-response level conversion circuit ) 是由 张亭 冯显声 黄勍隆 于 2019-12-05 设计创作，主要内容包括：本发明涉及集成电路结构领域,公开了一种低功耗快响应电平变换电路,包括：电平移位电路,用于接收外部输入并进行电平变换；开关模块,与电位平移电路电连接,用于启动信号并立即提供运行电流；偏置模块,与电位平移电路电连接,用于接收启动信号并延后提供参考电流；所述电平移位电路在接收到运行电路和/或参考电流后才可根据外部输入进行电平变化。本发明具有在确保低功耗的同时使电路实现快速响应的优点。(The invention relates to the field of integrated circuit structure, and discloses a low-power-consumption fast-response level conversion circuit, which comprises: the level shift circuit is used for receiving external input and carrying out level conversion; the switch module is electrically connected with the potential translation circuit and used for starting a signal and immediately providing running current; the bias module is electrically connected with the potential translation circuit and used for receiving a starting signal and providing reference current after delaying; the level shift circuit can change the level according to the external input after receiving the operation circuit and/or the reference current. The invention has the advantage of ensuring low power consumption and simultaneously enabling the circuit to realize quick response.)

1. A low power consumption fast response level shift circuit, comprising:

a level shift circuit (1) for receiving an external input and performing level conversion;

the switch module (2) is electrically connected with the potential translation circuit and is used for starting a signal and immediately providing running current;

the bias module (3) is electrically connected with the potential translation circuit and used for receiving a starting signal and providing reference current after delaying;

the level shift circuit (1) can change the level according to the external input after receiving the operating circuit and/or the reference current.

2. The low-power consumption fast-response level conversion circuit according to claim 1, the switch module (2) comprises a logic control circuit (21) and a switch element, wherein the logic control circuit (21) comprises a first inverter (211) coupled to a starting signal, a second inverter (212) coupled to the first inverter (211), an exclusive-OR gate (214) with two inputs coupled to the starting signal and the second inverter (212) respectively, and a first capacitor coupled to the connection midpoint of the first inverter (211) and the second inverter (212), the first capacitor is grounded, the output end of the exclusive-OR gate (214) is coupled with a switch element, the switching element is a field effect transistor, the output end of the exclusive-OR gate (214) is coupled with the grid electrode of the switching element, the drain of the switching element is coupled to the level shift circuit (1) and the source is grounded.

3. The low-power-consumption fast-response level conversion circuit according to claim 2, wherein the charging and discharging time of the first capacitor is longer than the starting time of the bias module (3).

4. The low-power-consumption fast-response level shift circuit according to claim 1, wherein the bias module (3) comprises a bias circuit (31) and a first field effect transistor, an input terminal of the bias circuit (31) is coupled to the start signal, an output terminal of the bias circuit (31) is coupled to a gate of the first field effect transistor, a drain of the first field effect transistor is coupled to the level shift circuit (1), and a source of the first field effect transistor is grounded.

5. The low-power-consumption fast-response level shifting circuit according to claim 1, wherein the level shifting circuit (1) comprises a third inverter (11) with an input connected to a control input, a second field effect transistor (12) with a gate coupled to an output of the third inverter (11), a fourth inverter (13) with an input coupled to an output of the third inverter (11), a third field effect transistor (14) with a gate coupled to an output of the fourth inverter (13), a fourth field effect transistor (15) with a drain coupled to a drain of the second field effect transistor (12), a fifth field effect transistor (16) with a drain coupled to a drain of the third field effect transistor (14), and a fifth inverter (17) with an input coupled to a drain of the fifth field effect transistor (16), wherein sources of the fourth field effect transistor (15) and the fifth field effect transistor (16) are both connected to a high voltage, the grid electrode of the fourth field effect transistor (15) is coupled with the drain electrode of a fifth field effect transistor (16), the grid electrode of the fifth field effect transistor (16) is coupled with the drain electrode of the fourth field effect transistor (15), and the enabling end of the third phase inverter (11) is connected with low voltage.

6. The low-power-consumption fast-response level conversion circuit according to claim 5, wherein a first voltage regulator diode (18) is connected in parallel to the fourth field effect transistor (15), an anode of the first voltage regulator diode (18) is coupled to a drain of the fourth field effect transistor (15), a cathode of the first voltage regulator diode is coupled to a source of the fourth field effect transistor (15), a second voltage regulator diode (19) is connected in parallel to the fifth field effect transistor (16), an anode of the second voltage regulator diode (19) is coupled to a drain of the fifth field effect transistor (16), and a cathode of the second voltage regulator diode is coupled to a source of the fifth field effect transistor (16).

Technical Field

The invention relates to the technical field of integrated circuit structures, in particular to a low-power-consumption fast-response level conversion circuit.

Background

Level conversion circuits are widely used in almost all integrated circuits to provide a method for converting high and low voltages to each other.

Referring to fig. 1, in order to realize a low power consumption design of level shift, a bias circuit 31 is required to control the operating current of level shift, the level shift is provided by high voltage vm and low voltage vcc, pd is a level shift enable signal, and an appropriate bias circuit is required to provide a reference current for level shift before the level shift output is ready.

Referring to fig. 2, in order to reduce the response time of the level shift by using the logic control circuit 21 for fast response, once the PD pin is enabled, the logic control circuit 21 will operate as soon as possible, and mn1 acts as a switch and it will respond to the control signal from the logic control circuit 21 immediately.

The above prior art solutions have the following drawbacks: in the design of realizing low power consumption, although the running current is controllable, because the bias circuit 31 has a starting time, the delay caused by the starting of the bias circuit 31 influences the response time of the level shift, and in a motor driver or other applications with severe response time, when the system is switched between the switch states, the response time of the level shift has an adverse effect on the application system; in the design for realizing the fast response, although the response is fast, the operation current cannot be controlled, a certain amount of current (through mn 1) is wasted, and the effect of low power consumption is difficult to realize.

Disclosure of Invention

Aiming at the defects in the prior art, the invention provides the low-power-consumption and quick-response level conversion circuit which has the advantage of ensuring low power consumption and simultaneously realizing quick response of the circuit.

In order to achieve the purpose, the invention provides the following technical scheme: a low power consumption fast response level shift circuit comprising:

the level shift circuit is used for receiving external input and carrying out level conversion;

the switch module is electrically connected with the potential translation circuit and used for starting a signal and immediately providing running current;

the bias module is electrically connected with the potential translation circuit and used for receiving a starting signal and providing reference current after delaying;

the level shift circuit can change the level according to the external input after receiving the operation circuit and/or the reference current.

By adopting the technical scheme, when the circuit works, the logic control circuit receives the starting signal and outputs the control signal, the switch element judges whether to provide the running current according to the control signal, the bias module receives the starting signal and prepares to provide the reference current, when the switch element provides the running current, the level shift circuit works, the level conversion is carried out according to the external input, after the bias module is started, the logic control circuit does not output the control signal any more, the switch element does not provide the running current any more, the bias module provides the reference current, the level shift circuit carries out the level conversion according to the external input, thereby realizing the effects of early-stage quick response and later-stage low power consumption.

The invention is further configured to: the switch module comprises a logic control circuit and a switch element, wherein the logic control circuit comprises a first phase inverter coupled to a starting signal, a second phase inverter coupled to the first phase inverter, an exclusive-OR gate with two inputs coupled to the starting signal and the second phase inverter respectively, and a first capacitor coupled to the connection midpoint of the first phase inverter and the second phase inverter, the first capacitor is grounded, the output end of the exclusive-OR gate is coupled to the switch element, the switch element is a field effect transistor, the output end of the exclusive-OR gate is coupled to the gate of the switch element, the drain of the switch element is coupled to a level shift circuit, and the source of the switch element is grounded.

By adopting the technical scheme, when the starting signal is not received, the input end of the first phase inverter is at a low level, the output end of the first phase inverter is at a high level, the first capacitor is in a charging state, after the starting signal is received, the input end of the first phase inverter is changed into the high level, the output end of the first phase inverter is changed into the low level, the first capacitor discharges, the input end of the second phase inverter is at the high level, the output end of the second phase inverter is at the low level, the two input ends of the exclusive-or gate are respectively at the high level and the low level, the output end of the exclusive-or gate is at the high level, and the switching element is switched on, so that the operating current is immediately provided, and the level shifting circuit; after the first capacitor finishes discharging, the input end of the second inverter becomes low level, the output end of the second inverter becomes high level, the two input ends of the exclusive-or gate are both high level, the output end of the exclusive-or gate is low level, the switch element is cut off, and therefore the operation current stops being provided, and the level shift circuit works through the reference current.

The invention is further configured to: and the charging and discharging time of the first capacitor is longer than the starting time of the biasing module.

By adopting the technical scheme, the charging and discharging time of the first capacitor is longer than the starting time of the bias module, so that the bias module is started before the switching element is cut off, and the condition that the level shift circuit stops working in midway is not easy to occur.

The invention is further configured to: the bias module comprises a bias circuit and a first field effect transistor, wherein the input end of the bias circuit is coupled with a starting signal, the output end of the bias circuit is coupled with the grid electrode of the first field effect transistor, the drain electrode of the first field effect transistor is coupled with the level shift circuit, and the source electrode is grounded.

By adopting the technical scheme, the bias circuit performs starting preparation after receiving the starting signal, and outputs a high level to the first field effect transistor after the starting is completed, so that the first field effect transistor is conducted, and the reference current is provided.

The invention is further configured to: the level shift circuit comprises a third phase inverter with an input end connected with a control input, a second field effect transistor with a grid electrode coupled with the output end of the third phase inverter, a fourth phase inverter with an input end coupled with the output end of the third phase inverter, a third field effect transistor with a grid electrode coupled with the output end of the fourth phase inverter, a fourth field effect transistor with a drain electrode coupled with the drain electrode of the second field effect transistor, a fifth field effect transistor with a drain electrode coupled with the drain electrode of the third field effect transistor, and a fifth phase inverter with an input end coupled with the drain electrode of the fifth field effect transistor, wherein the source electrodes of the fourth field effect transistor and the fifth field effect transistor are both connected with a high voltage, the grid electrode of the fourth field effect transistor is coupled with the drain electrode of the fifth field effect transistor, and the enable end of the third phase inverter is connected with a low voltage.

By adopting the technical scheme, if the input end of the third phase inverter is changed from low level to high level, the second field effect transistor is cut off, the third field effect transistor is switched on, the level of the input end of the fifth phase inverter is gradually reduced, the current flowing into the fifth field effect transistor is reduced, the level of the input end of the fifth phase inverter is further reduced, the output end of the fifth phase inverter is heightened, otherwise, if the input end of the third phase inverter is changed from high level to low level, the output end of the fifth phase inverter is lowered.

The invention is further configured to: the fourth field effect transistor is connected with a first voltage stabilizing diode in parallel, the anode of the first voltage stabilizing diode is coupled with the drain electrode of the fourth field effect transistor, the cathode of the first voltage stabilizing diode is coupled with the source electrode of the fourth field effect transistor, the fifth field effect transistor is connected with a second voltage stabilizing diode in parallel, the anode of the second voltage stabilizing diode is coupled with the drain electrode of the fifth field effect transistor, and the cathode of the second voltage stabilizing diode is coupled with the source electrode of the fifth field effect transistor.

Through adopting above-mentioned technical scheme, first zener diode and second zener diode stabilize voltage to make the difficult change that takes place of voltage of output.

In conclusion, the invention has the following beneficial effects:

through setting up switch module and biasing module, switch module works in advance to make level shift circuit can carry out the level conversion operation, when biasing module finishes working after preparing, switch module stop work, level shift circuit realizes the level conversion operation through the biasing module, makes the circuit realize quick response when guaranteeing low-power consumption.

Drawings

FIG. 1 is a diagram of a prior art bias circuit architecture;

FIG. 2 is a prior art logic control circuit block diagram;

FIG. 3 is a circuit block diagram of the present invention;

FIG. 4 is a diagram of a logic control circuit;

fig. 5 is a sequence diagram of the logic control circuit.

Reference numerals: 1. a level shift circuit; 11. a third inverter; 12. a second field effect transistor; 13. a fourth inverter; 14. a third field effect transistor; 15. a fourth field effect transistor; 16. a fifth field effect transistor; 17. a fifth inverter; 18. a first zener diode; 19. a second zener diode; 2. a switch module; 21. a logic control circuit; 211. a first inverter; 212. a second inverter; 214. an exclusive-or gate; 3. a biasing module; 31. a biasing circuit.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings.

Referring to fig. 3 and 4, the low power consumption and fast response level shift circuit disclosed by the present invention includes a level shift circuit 1, where the level shift circuit 1 includes a third inverter 11, a second field effect transistor 12, a fourth inverter 13, a third field effect transistor 14, a fourth field effect transistor 15, a fifth field effect transistor 16, and a fifth inverter 17. The input end of the third inverter 11 is connected with an external control input vin, the enabling end of the third inverter 11 is connected with a low voltage vcc, the grid of the second field effect transistor 12 is coupled with the output end of the third inverter 11, and the drain of the second field effect transistor 12 is coupled with the drain of the fourth field effect transistor 15. The drain of the third fet 14 is coupled to the drain of the fifth fet 16, the source of the third fet 14 is coupled to the source of the second fet 12, the gate of the third fet 14 is coupled to the output of the fourth inverter 13, and the input of the fourth inverter 13 is coupled to the output of the third inverter 11.

The sources of the fourth field effect transistor 15 and the fifth field effect transistor 16 are both connected to the high voltage vm, the gate of the fourth field effect transistor 15 is coupled to the drain of the fifth field effect transistor 16, and the gate of the fifth field effect transistor 16 is coupled to the drain of the fourth field effect transistor 15. The enable terminal of the fifth inverter 17 is connected to the high voltage vm, and the input terminal of the fifth inverter 17 is coupled to the drain of the fifth fet 16. A first voltage stabilizing diode 18 is connected in parallel on the fourth field effect transistor 15, the anode of the first voltage stabilizing diode 18 is electrically connected with the drain electrode of the fourth field effect transistor 15, the cathode of the first voltage stabilizing diode 18 is electrically connected with the source electrode of the fourth field effect transistor 15, a second voltage stabilizing diode 19 is connected in parallel on the fifth field effect transistor 16, the anode of the second voltage stabilizing diode 19 is electrically connected with the drain electrode of the fifth field effect transistor 16, and the cathode of the second voltage stabilizing diode 19 is electrically connected with the source electrode of the fifth field effect transistor 16.

The second field effect transistor 12 and the third field effect transistor 14 are N-channel field effect transistors, and the fourth field effect transistor 15 and the fifth field effect transistor 16 are P-channel field effect transistors.

The switch module 2 further comprises a switch module 2 and a bias module 3, the switch module 2 comprises a logic control circuit 21 and a switch element mn1, the switch element mn1 is an N-channel field effect transistor, the logic control circuit 21 comprises a first inverter 211, a second inverter 212, a first capacitor C1 and an exclusive-or gate 214, an input end of the first inverter 211 is connected with the enable signal pd, an input end of the second inverter 212 is coupled with an output end of the first inverter 211, and one end of the first capacitor C1 is coupled to a connection midpoint between the first inverter 211 and the second inverter 212, and the other end of the first capacitor C1 is grounded. Referring to fig. 4 and 5, two inputs of the xor gate 214 are respectively coupled to the enable signal pd and an output of the second inverter 212, and an output of the second inverter 212 is pd _ dly. The output terminal of the exclusive or gate 214 is coupled to the gate of the switching element mn1, and the output terminal of the exclusive or gate 214 has the signal sn. Referring to fig. 3 and 4, the drain of the switching element mn1 is coupled to the source of the second fet 12, and the source of the switching element mn1 is grounded. The charging and discharging time of the first capacitor C1 is longer than the starting time of the bias module 3.

The bias module 3 includes a bias circuit 31 and a first fet mn2, the first fet mn2 is an N-channel fet, an input terminal of the bias circuit 31 is electrically connected to the enable signal pd, an output terminal of the bias circuit 31 is coupled to a gate of the first fet mn2, a drain of the first fet mn2 is coupled to a source of the third fet 14, and a source of the first fet mn2 is grounded.

The implementation principle of the embodiment is as follows: when the start signal pd is not input, the input end of the first inverter 211 is at a low level, the output end of the first inverter 211 is at a high level at this time, the first capacitor C1 is in a charging state, after the start signal pd is received, the input end of the first inverter 211 is at a high level, the output end of the first inverter 211 is at a low level at this time, the first capacitor C1 discharges, the input end of the second inverter 212 is at a high level at this time, the output end of the second inverter 212 is at a low level, two input ends of the xor gate 214 are respectively at a high level and a low level, the output end of the xor gate 214 is at a high level, the switching element mn1 is turned on, thereby immediately providing a running current, and enabling the level shift circuit 1 to operate; after the first capacitor C1 finishes discharging, the input terminal of the second inverter 212 becomes low, the output terminal of the second inverter 212 becomes high, both input terminals of the xor gate 214 become high, the output terminal of the xor gate 214 becomes low, the switching element mn1 is turned off, and thus the supply of the operating current is stopped, but at this time, after the bias circuit 31 has been started, the bias circuit 31 turns on the first fet mn2 to supply the reference current to the level shift circuit 1, and thus the level shift circuit 1 continues to operate.

When the level shift circuit 1 is in operation, if the input end of the third inverter 11 changes from low level to high level, the second fet 12 is turned off, the third fet 14 is turned on, the level of the input end of the fifth inverter 17 gradually decreases, the current flowing into the fifth fet 16 decreases, the level of the input end of the fifth inverter 17 further decreases, and the output end of the fifth inverter 17 increases; on the other hand, if the input terminal of the third inverter 11 changes from high to low, the output terminal of the fifth inverter 17 goes low.

The embodiments of the present invention are preferred embodiments of the present invention, and the scope of the present invention is not limited by these embodiments, so: all equivalent changes made according to the structure, shape and principle of the invention are covered by the protection scope of the invention.