阅读说明：本技术 存储器地址转换 (Memory address translation ) 是由 乔纳森·柯蒂斯·比尔德 柯蒂斯·格伦·邓纳姆 罗克萨娜·鲁西托鲁 于 2018-07-05 设计创作，主要内容包括：存储器地址转换装置包括：转换数据存储库,用于存储转换数据的一个或多个实例,转换数据提供地址范围边界值,这些地址范围边界值定义虚拟存储器地址空间中的相应虚拟存储器地址边界之间的虚拟存储器地址的范围,并且转换数据指示虚拟存储器地址的范围内的虚拟存储器地址与输出地址空间中的对应输出存储器地址之间的转换；检测器电路,用于检测待转换的给定虚拟存储器地址是否位于由转换数据存储库中的转换数据的实例所定义的虚拟存储器地址的范围内；其中,检测器电路被配置为：当待转换的给定虚拟存储器地址位于由转换数据存储库存储的转换数据的任何实例所定义的虚拟存储器地址的范围之外时,取回转换数据的一个或多个另外实例；以及转换电路,用于将由检测到的转换数据实例所定义的转换应用于给定虚拟存储器地址。(The memory address translation apparatus includes: a translation data store to store one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space; a detector circuit to detect whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store; wherein the detector circuit is configured to: retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by a translation data store; and translation circuitry to apply translations defined by the detected translation data instances to the given virtual memory address.)

1. A memory address translation device, comprising:

a translation data store to store one or more instances of translation data, the translation data providing address range boundary values that define a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space;

a detector circuit to detect whether a given virtual memory address to be translated is within a range of the virtual memory address defined by an instance of the translation data in the translation data store;

wherein the detector circuit is configured to: retrieving one or more further instances of the translation data when the given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of the translation data stored by the translation data store; and

translation circuitry to apply translations defined by the detected instances of translation data to the given virtual memory address.

2. The apparatus of claim 1, wherein the translation data indicates an address offset between a virtual memory address within the range of virtual memory addresses and a corresponding output memory address in an output address space.

3. The apparatus of claim 1, wherein the translation data indicates a reference memory address in the output address space corresponding to a virtual memory address located at a predetermined position relative to the range of virtual memory addresses, the translation circuitry is configured to: translating the given virtual memory address within the range of virtual memory addresses by adding or subtracting an amount to or from a reference memory address in the output address space that depends on a difference in the virtual memory address space between the given virtual memory address and a virtual memory address located at a predetermined position relative to the range of virtual memory addresses.

4. The apparatus of claim 3, wherein:

the predetermined location is the lowest memory address within the range of virtual memory addresses.

5. The apparatus of claim 1, wherein the detector is configured to access one or more storage locations that store additional instances of the translation data.

6. The apparatus of claim 5, wherein the detector is configured to retrieve one or more further instances of the translation data from memory locations defined by one or more location parameters, the location parameters indicating addresses in the output memory space.

7. The apparatus of claim 5, wherein the detector is configured to retrieve one or more further instances of the conversion data in an order of use of the instances of the conversion data.

8. The apparatus of claim 7, wherein the order of use is a most frequently used order.

9. The apparatus of claim 1, wherein each instance of translation data comprises management data indicating access permissions associated with a range of virtual memory addresses of the instance of translation data.

10. A data processing apparatus comprising:

a processor for processing data according to the virtual memory address;

the address translation device of claim 1, an access memory system for translating a virtual memory address associated with a processing operation of the processor to an output memory address in response to the output memory address.

11. The apparatus of claim 10, comprising a cache memory disposed between the address translation apparatus and the memory system, the cache memory being addressable in the output memory address space.

12. The apparatus of claim 10, wherein:

the processor being responsive to context data defining a context applicable to a current task being performed by the processor; and is

The context data includes a location parameter indicating an address in the output memory space at which one or more further instances of translation data are stored.

13. The apparatus of claim 10, comprising:

a memory system responsive to memory addresses in the output memory address space.

14. The apparatus of claim 13, comprising:

two or more processors for processing data in accordance with virtual memory addresses in respective virtual memory address spaces, each processor having respective address translation means for translating virtual memory addresses relating to processing operations of that processor to output memory addresses for accessing the memory system.

15. The apparatus of claim 14, wherein the memory system is configured to operate according to an output memory address space common to interactions with the address translation apparatus of each processor.

16. The apparatus of claim 1, comprising bypass logic to bypass the translation circuitry when the translation is such that a virtual memory address is equal to a corresponding output memory address.

17. A memory address translation device, comprising:

translation data storage means for storing one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space;

means for detecting whether a given virtual memory address to be translated is within a range of the virtual memory address defined by an instance of the translation data in the translation data storage;

wherein the means for detecting is operable to: retrieving one or more further instances of the translation data when the given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of the translation data stored by the translation data store; and

translation means for applying a translation defined by the detected instance of translation data to the given virtual memory address.

18. A memory address translation method, comprising:

storing one or more instances of translation data, the translation data providing address range boundary values that define a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space;

detecting whether a given virtual memory address to be translated is within a range of the virtual memory address defined by an instance of the translation data in a translation data store;

retrieving one or more further instances of the translation data when the given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of the translation data stored by the translation data store; and is

Applying a translation defined by the detected instance of translation data to the given virtual memory address.

Background

The present disclosure relates to memory address translation.

The data processing apparatus may provide each running program or peripheral with access to a virtual address space defined by virtual memory addresses. Each program or device sees its own virtual address space containing instructions and data for use by the program or device. Among other certain advantages, the use of virtual addressing allows the operating system to control memory accesses by prohibiting one program from accessing or corrupting information used by another program.

When a virtual memory address needs to be accessed, it is first necessary to translate the virtual memory address to a physical memory address so that the required information can be obtained from or written to the physical memory or physical memory cache.

A cache, referred to as a Translation Lookaside Buffer (TLB), may be used as part of the address translation process. The TLB stores, page by page, the most recently used or commonly used translations between virtual and physical memory addresses, at a fixed size. Thus, as a first step in the address translation process, the TLB may be consulted to detect whether the TLB already contains the required address translation. If not, a more complex translation process may be used, e.g., involving consulting a so-called page table that holds address translation information, typically resulting in filling the TLB with the required translations.

Disclosure of Invention

In one example arrangement, there is provided a memory address translation apparatus comprising:

a translation data store to store one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space;

a detector circuit to detect whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store;

wherein the detector circuit is configured to: retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by a translation data store; and

translation circuitry to apply a translation defined by the detected translation data instance to the given virtual memory address.

In another example arrangement, there is provided a data processing apparatus comprising:

a processor for processing data according to the virtual memory address;

address translation means as defined above for translating a virtual memory address relating to a processing operation of the processor to an output memory address for accessing a memory system responsive to the output memory address.

In another example arrangement, a memory address translation apparatus is provided, comprising:

translation data storage means for storing one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space;

means for detecting whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store;

wherein the means for detecting is operable to: retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by the translation data store; and

translation means for applying a translation defined by the detected translation data instance to the given virtual memory address.

In another example arrangement, there is provided a memory address translation method comprising:

storing one or more instances of translation data, the translation data providing address range boundary values that define a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space;

detecting whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store;

retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by a translation data store; and is

The translation defined by the detected translation data instance is applied to the given virtual memory address.

Further corresponding aspects and features of the present technology are defined by the appended claims.

Drawings

The present technology will be further described, by way of example only, with reference to embodiments thereof as illustrated in the accompanying drawings, in which:

fig. 1 schematically shows a data processing apparatus;

fig. 2a and 2b schematically show respective examples of transformation data;

FIG. 3 schematically illustrates the storage of multiple instances of transformation data;

FIG. 4 schematically illustrates a memory address translation device;

FIG. 5 is a schematic flow chart diagram illustrating an initialization process;

FIGS. 6 and 7 are schematic flow diagrams illustrating a memory access method;

FIG. 8 is a schematic flow chart diagram illustrating a memory address translation method; and is

FIG. 9 is a schematic flow chart diagram illustrating a memory address translation method.

Detailed Description

The following description of the embodiments is provided before discussing the embodiments with reference to the accompanying drawings.

One example embodiment provides a memory address translation apparatus, comprising:

a translation data store to store one or more instances of translation data, the translation data providing address range boundary values that define a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the virtual memory address range and corresponding output memory addresses in an output address space;

a detector circuit for detecting whether a given virtual memory address to be translated is within a virtual memory address range defined by an instance of translation data in a translation data store;

wherein, when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by the translation data store, the detector circuit is configured to retrieve one or more further instances of translation data; and

translation circuitry to apply translations defined by the detected instances of translation data to the given virtual memory address.

Example embodiments provide a convenient straightforward memory address translation technique that may mitigate the potential latency and processing requirements of other techniques, such as using page table walk, etc. The techniques may provide variable sized regions of virtual memory address space, each region having a mapping to a corresponding region of output memory address space, possibly defined by a single instance of translation data. For example, a simple offset may be provided, or a reference address to a particular address within a range of virtual memory addresses.

Advantageously, the apparatus may store an instance of translation data such that another instance is only required if the required virtual memory address is not within the range of virtual memory addresses defined by the currently saved instance(s).

For example, the translation data may indicate an address offset between a virtual memory address within the range of virtual memory addresses and a corresponding output memory address in the output address space. In other examples, the translation data indicates a reference memory address in the output address space corresponding to a virtual memory address located at a predetermined position relative to the range of virtual memory addresses, so the translation circuitry is configured to: a given virtual memory address within the range of virtual memory addresses is translated by adding or subtracting an amount to or from a reference address in the output address space that depends on a difference in the virtual memory address space between the given virtual memory address and a virtual memory address located at a predetermined position relative to the range of virtual memory addresses. In some examples, the predetermined location is a lowest memory address within a range of virtual memory addresses.

Conveniently, the detector may be configured to access one or more memory locations that store further instances of the translation data. For example, the detector may be configured to retrieve one or more further instances of the translation data from memory locations defined by one or more location parameters, the location parameters indicating addresses in the output memory space.

To aim at retrieving the next most useful instance of the transformation data, in some examples, the detector is configured to retrieve one or more further instances of the transformation data in order of use of the instances of the transformation data. For example, the order of use may be the most frequently used order.

In some examples, each instance of translation data includes management data indicating access permissions associated with a range of virtual memory addresses of the instance of translation data.

Another example embodiment provides a data processing apparatus, comprising:

a processor for processing data according to the virtual memory address;

address translation means as defined above for translating a virtual memory address relating to a processing operation of a processor to an output memory address for accessing a memory system, the memory system being responsive to the output memory address.

In some examples, a cache memory may be disposed between the address translation device and the memory system, the cache memory being addressable in the output memory address space. For example, if the cache does not contain the required data item, the memory system may be referenced, which responds to the memory address in the output memory address space.

A convenient method of establishing a mapping between a virtual memory address space and an output memory address space is the following: wherein the processor is responsive to context data defining a context applicable to a current task being executed by the processor; and the context data includes location parameters indicating addresses in the output memory space where one or more further instances of the translation data are stored. In this way, the amount of context data required to handle the function may be small (one or more pointers to memory holding the translation data).

In some examples, two or more processors may be provided to process data according to virtual memory addresses in respective virtual memory address spaces, each processor having respective address translation means for translating virtual memory addresses relating to processing operations of that processor to output memory addresses for accessing the memory system. Even though the processor has its own virtual memory address space, the output memory address space may be common to the processors. For example, the memory system may be configured to operate according to an output memory address space common to interactions with the address translation devices of each processor.

Some examples provide bypass logic to bypass the translation circuitry when translating such that the virtual memory address is equal to the corresponding output memory address. This may avoid having to use a conversion means when not required. For example, the operating state of the bypass logic may be set task context data.

Another example embodiment provides a memory address translation apparatus, including:

translation data storage means for storing one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the virtual memory address range and corresponding output memory addresses in an output address space;

means for detecting whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store;

wherein the means for detecting is operable to retrieve one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by the translation data store; and

translation means for applying a translation defined by the detected translation data instance to the given virtual memory address.

Another example embodiment provides a memory address translation method, including:

storing one or more instances of translation data, the translation data providing address range boundary values that define a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the virtual memory address range and corresponding output memory addresses in an output address space;

detecting whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store;

retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by a translation data store; and

the translation defined by the detected translation data instance is applied to the given virtual memory address.

Referring now to the drawings, FIG. 1 schematically illustrates a data processing apparatus.

A plurality of processor cores 100, 110 are provided. In the example of fig. 1, two such processor cores are shown, but more may be provided (as schematically illustrated by dashed box 112). Alternatively, the system may include only one processor core.

The processor core is arranged to process data according to the virtual memory address. For example, each processor core may process data according to virtual memory addresses in a respective virtual memory address space, e.g., under control of an operating system or so-called hypervisor that allocates virtual memory address spaces to processes being executed by different processor cores, in part as a technique to avoid processes associated with one processor core from accidentally or maliciously accessing data appropriate for processes being executed by another processor core.

A memory address translation device is provided to translate between virtual memory addresses and so-called real addresses in a virtual memory address space.

In the context of the memory address translation techniques to be discussed below, a real address is an "output" memory address in an output address space (the so-called real address space). This may represent a physical address by which a physical memory device or other addressable unit may be physically addressed. Alternatively, the real (output) memory address may represent an address that requires another stage of address translation before being used to access a physical memory device or other addressable unit. Any of these options are equivalent from the point of view of the address translation technique to be discussed. That is, the address translation technique starts with a virtual memory address and produces an output memory address. Whether the entire device then performs another phase of address translation on the output memory address is not important to the generation of the output memory address itself.

In fig. 1, address translation is performed by so-called Range Table Buffers (RTBs) 105, 115. This performs address translation between virtual memory addresses in the virtual memory address space and output memory addresses in the output (real) address space. Each processor core has a corresponding range table buffer. The operation of the range table buffer will be described in detail below.

Bypass logic 108, 118 is provided to selectively bypass the RTBs 105, 115 when the address translation causes the virtual memory address to equal the corresponding output memory address. The bypass circuit or logic may be controlled by control signals 109, 119 as will be discussed below. When the bypass logic is enabled, either the RTBs 105, 115 do not perform any translations or the translations performed by the RTBs 105, 115 are ignored and the virtual memory addresses are provided by the bypass ways 104, 114 for use as output memory addresses.

The memory address translation operations to be discussed below will assume that bypass logic is not currently enabled (unless otherwise noted).

The processor cores 100, 110 are implemented or fabricated on an integrated circuit substrate in this example, and both (or all in the case of more than two) may be provided on the same integrated circuit substrate. These devices are referred to in fig. 1 as "on-chip".

Cache and/or system cache memory 130 is also provided on-chip to provide temporary storage for subsets of data held by the memory system (such as recently accessed subsets and/or speculatively acquired subsets) as discussed below. As shown in fig. 1, the two processor cores 100, 110 share a common cache/system cache 130, but in other examples more than one may be provided and another cache 140 is shown in dashed lines to illustrate such an arrangement.

The cache/system cache 130(140) operates according to the output (real) memory addresses generated by the RTBs 105, 115.

Dashed line 150 indicates a logical boundary between an on-chip device and an off-chip device, but it will be appreciated that this is merely an example and it is a matter of the system designer to implement any of the modules shown in FIG. 1 on the same integrated circuit or as different circuits. Thus, fig. 1 merely represents an illustrative example of how separation of on-chip and off-chip components may be achieved.

One or more memory node controllers 160, 170 are provided off-chip, which in turn access one or more corresponding physical devices 180, 190, such as random access memory (DRAM). Considering that the physical devices 180, 190 operate in physical address space, the two functions of the memory node controllers 160, 170 may include: (a) if another stage of translation is required, translating the output (real) memory address to a physical memory address; and (b) manage which of the physical devices 180, 190 needs to be accessed in order to achieve the desired memory access operation.

The translation operation (a) described above may be performed either using the techniques discussed below or by known memory address translation techniques. The management operation (b) for managing which of the physical devices 180, 190 should be accessed may be performed, for example, using a table or directory stored at one or more of the memory node controllers 160, 170 to indicate the division of the physical address space between the physical device and the successive memory node controllers.

It is not required that more than one memory node controller 160, 170 be provided, but in the example of fig. 1, two memory node controllers are provided. If one of the memory node controllers, such as memory node controller 160, receives a request for a memory access transaction relating to an address processed by another memory node controller, such as memory node controller 170, first memory node controller 160 may communicate with the other memory node controller 170 via data connection 165, passing an output (real) address relating to the transaction and requesting that the transaction be executed by second memory node controller 170.

The Range Table Buffers (RTBs) 105, 115 operate by storing one or more instances of translation data. Fig. 2a schematically shows such an example of converting data.

Referring to fig. 2a, the instances of the translation data (or indeed each instance) are formed as a 224-bit word comprising 22 reserved bits 200, 10 bits of management data (discussed below) 205, 64 bits of address offset data 210, 64 bits of "base virtual address" data 220, and 64 bits of range data 230.

Together, the data 220, 230 define a range of virtual memory addresses between corresponding virtual memory address boundaries in the virtual memory address space. In the example of FIG. 2a, the range of virtual memory addresses is between the addresses represented by "base VA" up to and including the address represented by "base VA + range". Here, it will of course be appreciated that it is not necessarily the case that the lowest address in the range must be defined by the field "base VA". More generally, the range of virtual addresses may be defined by one reference value located at a predetermined position relative to the range of virtual addresses, so in other examples, field 220 may be occupied by, for example, "highest VA", such that the range of virtual memory addresses is defined by a "highest VA-range" up to "highest VA". In other examples, field 220 may be occupied by, for example, "central VA," such that the range of virtual memory addresses extends between a "central VA-range" to a "central VA + range. Again, the "Central VA" will be an example of a virtual memory address located at a predetermined location relative to a range of virtual memory addresses. However, the present example will assume that field 220 is occupied by a "base VA," and that the corresponding virtual memory address boundaries for the range of virtual memory addresses are a "base VA" and a "base VA + range" in this example.

The offset field 210 contains an address offset between a virtual memory address within a range of virtual memory addresses and a corresponding output memory address in the output address space that is applied as a linear sum to the virtual memory addresses within the range defined by the boundaries discussed above to generate the corresponding output memory address. The offset may be positive, negative, or virtually zero. Thus, for any virtual memory address VA _ test that falls within the range defined by "base VA" and "base VA + range", the translated (output) memory address in the output memory address space can be represented as:

VA _ test + offset

In other words, in this example, the offset represents a simple difference between any virtual memory address within the range of virtual memory addresses and the corresponding output memory address.

Another example is schematically shown in fig. 2b, where the fields 200, 205, 220, 230 may be the same as those shown in fig. 2a, but instead of the offset field 210, a field called base output 240 is provided, which indicates (in this example) an output memory address corresponding to the address "base VA" in the virtual memory address space. More generally, field 240 may indicate a reference memory address in the output address space that corresponds to a virtual memory address located at a predetermined position relative to the range of virtual memory addresses (such as a predetermined position in the examples discussed above), so the translation circuitry to be discussed below is configured to translate a given virtual memory address within the range of virtual memory addresses by adding or subtracting from the reference address in the output address space, and now dependent on a difference in the virtual memory address space between the given virtual memory address and the virtual memory address located at the predetermined position relative to the range of virtual memory addresses. This gives the following conversion function:

(VA _ test-predetermined VA) + reference

The type of translation defined by the translation data of FIG. 2b provides a range of potentially variable sizes covered by a single instance of translation data, and may provide multiple translations mapping different virtual memory addresses to the same output memory address, if desired.

Fig. 3 schematically illustrates the storage of multiple instances of the translation data of fig. 2a or 2b, e.g. in a cache 130(140) or in an off-chip memory system, e.g. in one of the physical devices 180, 190.

The storage locations defining the storage of the set of instances of translation data are provided by variable RT address 300. The derivation of the variable RT address will be discussed further below. The memory address represented by the RT address may be, for example, a real (output) address, a physical memory address, or another memory address. In this example, the variable RT address represents a physical memory address where the instance of translation data is aggregated in physical memory.

As indicated schematically by the dashed arrows of fig. 3, the variable RT address may provide location information for each instance (or more than one of the instances). Or the position may be inferred from the size of each instance (e.g., 224 bits) and the position of the reference instance in the instance.

Instances of translation data may be pre-stored in memory by, for example, an operating system and/or hypervisor, and may be ordered, for example, in order of their applicability to the virtual memory address space. For example, the virtual memory address space is shown as rectangle 310 on the right side of FIG. 3, and the ranges of virtual memory addresses represented by the upper two (as shown) instances of translation data are schematically shown as ranges 312, 314 in FIG. 3. The additional data 320 may be stored either by the RTB (in repository 460 discussed below) or in memory with the instances of the translation data, indicating attributes such as the most frequently used and/or most recently used instances of the translation data, and/or frequency of use of each instance of the translation data, and/or most recently accessed time of each instance of the translation data, and so forth.

FIG. 4 schematically illustrates a memory address translation device, such as RTBs 105, 115 of FIG. 1, as an example of translation circuitry that can apply translations defined by detected translation data instances to a given virtual memory address.

The device includes: an input 400 for receiving a virtual memory address, an output 410 for outputting an output (translated) memory address, a translation data store 420 for storing one or more instances of translation data as discussed above, access circuitry 430, a translator/permission detector 440, detector/fetch logic 450, a memory 460 for storing fetch criteria, and a store 470 for storing an RT address variable.

In operation, as discussed above, translation data store 420 stores one or more instances of translation data (such as the translation data shown in fig. 2a and 2 b) that provide address range boundary values (such as base VA and range) that define a range of virtual memory addresses between corresponding virtual memory address boundaries in a virtual memory address space, and that indicate translations (such as offsets or base output fields) between virtual memory addresses within that virtual memory address range and corresponding output memory addresses in an output memory address space.

In response to the virtual address received on input 400, access circuitry 430 accesses translation data held in translation data store 420. For example, a single instance of the transformation data may be stored in transformation data store 420 at any time. Detector/fetch logic 450 serves as a detector circuit for detecting whether a virtual memory address to be translated is within a range of virtual memory addresses defined by (or to) an instance of translation data in translation data store 420. If so, the detector/acquisition logic provides data indicating the conversion (such as providing an offset or base output field to the converter/permission detector 440) as well as management data in field 205. Translator/permission detector circuit 440 applies the translation defined by the detected instance of translation data (or the instance) to the input (given) virtual memory address to determine a translated (output) memory address. This is provided to the cache/system cache 130 on output 410 and to one or more of the memory node controllers 160, 170 if necessary.

If detector/fetch logic 450 detects that the virtual memory address to be translated is not within the range of virtual memory addresses defined by the instance (or instances) of translation data in translation data store 420, then the detector/fetch logic initiates fetching of another instance (or one or more additional instances) of translation data. To this end, detector/acquisition logic 450 may use acquisition criteria stored in acquisition criteria store 460.

Examples of acquisition criteria have been discussed above and may include: for example, the most recently used translation data instance (which is not the instance currently held by the translation data store), the most frequently used translation data instance that is not currently held in the translation data store, and so on. Detector/fetch logic 450 initiates the fetch of the translation data using the RT address variable stored in storage bank 470. The retrieved translation data instance is then stored in the translation data store, evicting the currently stored instance (if only one is saved) or, if more than one instance is saved there, the least recently used instance and/or the least frequently used instance (of the instances stored in translation data store 420). Thus, when a given virtual memory address to be translated is outside the range of virtual memory addresses defined by any instance of translation data stored by the translation data store, the detector/fetch logic 450 is configured to retrieve one (or indeed more) further instances of translation data. To this end, detector/acquisition logic 450 may access one or more storage locations (e.g., defined or referenced by a variable RT address) that store additional instances of translation data. In this manner, a variable RT address may be used as a location parameter, and the detector/fetch logic 450 is configured to retrieve one or more further instances of translation data from memory locations defined by one or more such location parameters, the one or more location parameters indicating an address in the output memory space (or indeed in the physical memory space if the physical memory spaces are different).

As discussed above, the acquisition criteria 460 may cause the detector/acquisition logic 450 to be configured to retrieve one or more additional instances of the translation data in the order of use of the translation data instances. For example, the order of use may be the most frequently used order, although it may be the most recently used order.

Another function of the translator/permission detector 440 is to detect the management data 205 for the instance of translation data currently used for translation, and the management data 205 indicates access permissions associated with the range of virtual memory addresses for that instance of translation data. The permission data may either be passed to the cache/system cache 130 as permission data associated with the current memory access or may be used to control or gate the currently attempted memory accesses so that they are not forwarded by the translator/permission detector to the cache/system cache 130 if they violate the permission data.

Thus, the arrangement of fig. 1 may provide: one or more processors to process data according to a virtual memory address; and address translation means, such as shown in figure 4, for translating virtual memory addresses associated with processing operations by the one or more processors to output memory addresses for accessing the memory system responsive to the output memory addresses. Cache/system cache 130 may provide an example of a cache memory disposed between the address translation device and the memory system that is addressable in the output memory address space. The memory node controllers 160, 170 and the physical devices 180, 190 may provide a memory system that is responsive to memory addresses in the output memory address space.

If two or more processor cores 100, 110 are used, each processor may have a respective address translation device 105, 115, the address translation devices 105, 115 being used to translate virtual memory addresses relating to processing operations of that processor 100, 110 into output memory addresses for accessing the memory system 160, 170, 180, 190. As described above, each processor 100, 110 may be used to process data according to virtual memory addresses in a corresponding virtual memory address space. However, the real (output) memory address space may be common as between the processors 100, 110, such that the memory systems 160, 170, 180, 190 are configured to operate according to the output memory address space common to the interaction with the address translation devices 105, 115 of each processor.

Fig. 5 is a schematic example of an initialization process.

The variable RT address can simply be established during the entire run time at start-up or boot-up of the system. Similarly, controls 109, 119 for indicating to the device whether the bypass function should be enabled may also be established throughout runtime at boot-up or boot-up. However, in other examples, these items are established at so-called context switches.

By way of background, in an arrangement of one or more interconnected processors, the one or more processors may execute program tasks, such as threads, in sequential portions, which may be interspersed with portions of execution of other program tasks. In a multi-processor or multi-core system, execution may be transferred from one processor to another. To this end, a process called context switching may be performed.

In context switching, each processor is configured to save context data related to or applicable to a program task after execution of the program task by the processing element, and to load context data previously saved by the processing element or another processor upon resumption of execution of the program task.

The context data may indicate the current processing state of the processor when execution of a particular program task is suspended or handed over. However, it may also provide parameters, e.g. established by the operating system and/or the hypervisor, which are common to each case performing the program task. In this example, the context data may indicate whether the bypass function should be enabled, and the location in memory of an instance of the translation data applicable to the execution of the program task. Thus, the bypass function is enabled or disabled when the context data is loaded, and the location in memory of the appropriate address translation data to be used by the RTBs 105, 115 is determined assuming that the bypass function is disabled. Fig. 5 schematically shows this initialization process as a schematic flow chart starting with a context change at step 500 corresponding to a task exchange as discussed above. This causes the relevant processor to load a new context at step 510.

With reference to the parameters defined by the newly loaded context, the processor core detects whether a bypass operation should be used for that portion of program task execution. If the answer is yes, then the bypass logic 108, 118 is enabled at step 530 via control signals 109, 119. If the answer is no, control passes to step 540 where a variable RT address is detected (e.g., from context data applicable to the current task) and stored in the repository 470 of FIG. 4 at step 540. Using the variable RT address, at least one table entry (that is, an instance of translation data) is retrieved and stored in translation data store 420 at step 550.

Fig. 6 and 7 are schematic flow charts showing a memory access method. Specifically, fig. 6 schematically represents a load operation, and fig. 7 schematically represents a stop operation. In each case, an instance 600, 700 of transformation data maintained by transformation data store 420 is referenced.

Referring first to FIG. 6, a load address 605 is generated by one of the processor cores 100, 110, the load address 605 indicating a virtual address from which one or more data items should be loaded. At step 610, access circuitry 430 looks up one or more instances of the translation data held by translation data store 420. Then, at step 615, detector/fetch logic 450 detects whether a given virtual address (representing a load address) is present within one or more ranges defined by the translation data held in translation data store 420. If the answer is no, then further actions 620 discussed below are performed. If, however, the answer is yes, then control passes to step 625, at step 625 the translator/permission detector 440 accesses the management data field 205 within the translation data to detect whether the current operation is permitted based on permission data associated with the range of virtual addresses defined by the instance of the translation data. If the answer is no, control passes to step 620 where further action (in this case an increase in the fault condition) is performed at step 620. However, if the answer is yes, the translator/permission detector 440 calculates an output address at step 630 using the offset field 210 of the instance of translation data held in the translation data store 420.

The output memory address is passed to the cache/system cache 130 and a check is made at step 635 as to whether the data corresponding to the output address is currently held in the cache/system cache 130. If the answer is yes, the required data item is returned to the processor core that initiated the transaction at step 640. If the answer is no, then at step 645 the memory access is made to reference the memory system 160, 170, 180, 190 for processing.

A similar arrangement is schematically illustrated in fig. 7, which shows data storage operations.

Here, as described above, reference is made to an instance 700 of transformation data currently held by transformation data store 420.

At step 705, the associated processor core establishes a virtual address representing the desired memory address.

At step 710, access circuitry 430 accesses the translation data store to detect whether the memory address established at step 705 is within a range defined by one or more stored translation data instances. If, at step 715, the memory address is not within the one or more ranges, then control passes to step 720 and further actions are taken at step 720, discussed below. If, however, the answer is yes, then control passes to step 725 where the translator/permission detector 440 detects whether the current operation is allowed based on the management data field 205 at step 725. If the answer is no, control passes to step 720 and further action (in this example, a fault condition) is performed at step 720.

However, if the answer at step 725 is yes, then control passes to step 730, where step 730 calculates an output address for storing the current data based on the given virtual address representing the store address (735) and the offset field 210 to generate an output address 740 for the store operation.

FIG. 8 is a schematic flow chart diagram illustrating a memory address translation method, and in particular processing a negative result of steps 615, 715 of FIGS. 6 and 7 when it is detected that the currently required virtual address is not within one or more ranges defined by one or more instances of translation data held by the translation data store.

Referring to FIG. 8, at step 800, if there is a "hit," that is, the current virtual memory address to be translated does lie within one of the ranges defined by one or more instances of translation data held by translation data store 420, then control passes to step 810, step 810 summarizes the translation process discussed above, and the current (given) virtual address is translated to a corresponding output memory address.

However, if the result from step 800 is no, corresponding to a negative result of steps 615, 715, then control passes to step 820, where an RT address (RT base address) is accessed at step 820, the RT address forming part of the context format and may optionally be buffered or stored by RTB105, 115 in repository 470.

At step 830, if the RTBs 105, 115 detect that instances of the translation data are indeed available for access (i.e., they are not all currently held by the translation data store 420), then control passes to step 840. If no more instances are available for retrieval, control passes to step 850 where a fault condition is established at step 850.

At step 840, the detector/acquisition logic 450 retrieves the next instance. These may optionally be accessed in a sorted order-for example, they may be sorted in the order of use (e.g., by frequency of use). The following one of the most used instances is accessed. Optionally, at step 860, one or more additional instances may also be speculatively loaded.

The test of step 800 is effectively repeated at step 870. If the given virtual address for translation is within one or more ranges defined by the newly loaded instance, control may pass to step 810 to perform the translation. If not, control returns to step 830 such that one or more other instances are again loaded (if available) using step 840, or if no more instances are available, a fault condition is established at step 850.

FIG. 9 is a schematic flow chart diagram illustrating a memory address translation method comprising:

storing (at step 900) one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space;

detecting (at step 910) whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store;

retrieving (at step 920) one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instances of translation data stored by the translation data store; and

the translation defined by the detected translation data instance is applied (at step 930) to the given virtual memory address.

In this application, the word "configured" is used to indicate that an element of a device has a configuration capable of performing a defined operation. In this context, "configuration" means an arrangement or manner of interconnection of hardware or software. For example, the apparatus may have dedicated hardware providing the defined operations, or a processor or other processing device may be programmed to perform the functions. "configured to" does not imply that the device elements need to be changed in any way in order to provide the defined operation.

Although illustrative embodiments of the present technology have been described in detail herein with reference to the accompanying drawings, it is to be understood that the technology is not limited to those precise embodiments, and that various changes, additions and modifications may be effected therein by one skilled in the art without departing from the scope and spirit of the technology as defined by the appended claims. For example, various combinations of the features of the dependent claims with the features of the independent claims may be made without departing from the scope of the present technology.

Thus, some features of the disclosed embodiments are set forth in the following numbered items:

1. a memory address translation device, comprising: a translation data store to store one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space; a detector circuit to detect whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store; wherein the detector circuit is configured to: retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by a translation data store; and translation circuitry to apply translations defined by the detected translation data instances to the given virtual memory address.

2. The apparatus of item 1, wherein the translation data indicates an address offset between a virtual memory address within the range of virtual memory addresses and a corresponding output memory address in the output address space.

3. The apparatus of item 1, wherein the translation data indicates a reference memory address in the output address space corresponding to a virtual memory address located at a predetermined position relative to the range of virtual memory addresses, so the translation circuitry is configured to: a given virtual memory address within the range of virtual memory addresses is translated by adding or subtracting to or from a reference memory address in the output address space an amount that depends on a difference in the virtual memory address space between the given virtual memory address and a virtual memory address located at a predetermined position relative to the range of virtual memory addresses.

4. The apparatus of item 3, wherein: the predetermined location is the lowest memory address within the range of virtual memory addresses.

5. The apparatus of item 1, wherein the detector is configured to access one or more storage locations that store additional instances of the translation data.

6. The apparatus of item 5, wherein the detector is configured to retrieve one or more further instances of the translation data from memory locations defined by one or more location parameters, the one or more location parameters indicating addresses in the output memory space.

7. The apparatus of item 5, wherein the detector is configured to retrieve the one or more additional instances of the conversion data in an order of use of the instances of the conversion data.

8. The apparatus of item 7, wherein the order of use is a most frequently used order.

9. The apparatus of item 1, wherein each instance of translation data comprises management data indicating access permissions associated with a range of virtual memory addresses of the instance of translation data.

10. A data processing apparatus comprising: a processor for processing data according to the virtual memory address; the address translation apparatus of item 1, for accessing a memory system to translate a virtual memory address associated with a processing operation of the processor to an output memory address in response to the output memory address.

11. The apparatus of item 10 comprising a cache memory disposed between the address translation apparatus and the memory system, the cache memory being addressable in the output memory address space.

12. The apparatus of item 10, wherein: the processor responding to context data defining a context applicable to a current task being executed by the processor; and the context data includes location parameters indicating addresses in the output memory space where one or more further instances of the translation data are stored.

13. The apparatus of item 10, comprising: a memory system responsive to a memory address in an output memory address space.

14. The apparatus of item 13, comprising: two or more processors for processing data in accordance with virtual memory addresses in respective virtual memory address spaces, each processor having respective address translation means for translating virtual memory addresses relating to processing operations of that processor to output memory addresses for accessing the memory system.

15. The apparatus of item 14 wherein the memory system is configured to operate according to an output memory address space common to interactions with the address translation means of each processor.

16. The apparatus of item 1, comprising bypass logic to bypass the translation circuitry when translating such that the virtual memory address is equal to the corresponding output memory address.

17. Memory address translation apparatus comprising: translation data storage means for storing one or more instances of translation data, the translation data providing address range boundary values defining a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space; means for detecting whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in the translation data storage; wherein the means for detecting is operable to: retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by the translation data store; and translation means for applying a translation defined by the detected translation data instance to the given virtual memory address.

18. A memory address translation method, comprising: storing one or more instances of translation data, the translation data providing address range boundary values that define a range of virtual memory addresses between respective virtual memory address boundaries in a virtual memory address space, and the translation data indicating translations between virtual memory addresses within the range of virtual memory addresses and corresponding output memory addresses in an output address space; detecting whether a given virtual memory address to be translated is within a range of virtual memory addresses defined by instances of translation data in a translation data store; retrieving one or more further instances of translation data when a given virtual memory address to be translated is outside a range of virtual memory addresses defined by any instance of translation data stored by a translation data store; and applying the translation defined by the detected translation data instance to the given virtual memory address.