阅读说明：本技术 多相功率转换器的电流共享 (Current sharing for multiphase power converters ) 是由 B·唐 于 2021-04-15 设计创作，主要内容包括：本公开的各实施例涉及多相功率转换器的电流共享。多相功率转换器的功率级包括：第一开关设备,被配置为在功率级的第一切换状态下,将功率级的输出节点连接到电源电压；第二开关设备,被配置为在功率级的第二切换状态下,将输出节点连接到地；驱动器电路装置,被配置为将功率级设置为切换状态或非切换状态,每个状态的持续时间以及状态之间的定时转换由控制信号来指示；电流感测电路装置,被配置为测量流过开关设备中的至少一个开关设备的电流；以及定时电路装置,被配置为基于所测量的电流的幅度来调整切换状态之间的定时转换,以便相对于由控制信号限定的参考持续时间来改变第一切换状态和/或第二切换状态的有效持续时间。(Embodiments of the present disclosure relate to current sharing for multiphase power converters. A power stage of a multiphase power converter includes: a first switching device configured to connect an output node of the power stage to a supply voltage in a first switching state of the power stage; a second switching device configured to connect the output node to ground in a second switching state of the power stage; driver circuitry configured to set the power stage to a switching state or a non-switching state, the duration of each state and the timing transitions between states being indicated by control signals; current sensing circuitry configured to measure current flowing through at least one of the switching devices; and timing circuitry configured to adjust timed transitions between switching states based on the measured magnitude of the current so as to vary the effective duration of the first switching state and/or the second switching state relative to a reference duration defined by the control signal.)

1. A power stage of a multiphase power converter, the power stage comprising:

a first switching device configured to connect an output node of the power stage to a supply voltage in a first switching state of the power stage;

a second switching device configured to connect the output node to ground in a second switching state of the power stage;

driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in the first switching state, the second switching state or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by switching control signals received by the power stage;

current sensing circuitry configured to measure current flowing through at least one of the switching devices; and

timing circuitry configured to adjust the timed transitions between the switching states so as to change an effective duration of the first and/or second switching states relative to a reference duration defined by the switching control signal, wherein adjustment of the timed transitions is based on the magnitude of the current measured by the current sensing circuitry.

2. The power stage of claim 1, wherein as the current measured by the current sensing circuitry increases, the timing circuitry is configured to adjust the timing transitions such that the effective duration of the first switching state is decreased and/or the effective duration of the second switching state is increased relative to the switching control signal.

3. The power stage of claim 1, wherein the timing circuitry is configured to adjust the timing transitions based on a ratio of the magnitude of the current measured by the current sensing circuitry to a reference current level.

4. The power stage of claim 3, wherein the reference current level is a maximum current threshold for the power stage.

5. The power stage of claim 1, wherein the timing circuitry is configured to adjust the timing transitions in a manner that is monotonic and linearly proportional to the magnitude of the current measured by the current sensing circuitry.

6. The power stage of claim 1, wherein the timing circuitry is configured to derive a PWM pulse from the switching control signal for the first and/or second switching device, and wherein the timing circuitry is configured to adjust the timing transitions by spreading the PWM pulse based on a variable delay that is based on the magnitude of the current measured by the current sensing circuitry.

7. The power stage of claim 6, wherein the variable delay is implemented as a flow limit buffer that makes different adjustments to the ON delay and the OFF delay.

8. The power stage of claim 6, wherein the variable delay is implemented as a pulse widening circuit.

9. The power stage of claim 1, wherein the timing circuitry is configured to derive a first PWM pulse from the switching control signal for the first switching device and a second PWM pulse from the switching control signal for the second switching device, wherein the timing circuitry is configured to compare an edge of the first PWM pulse to an edge of the second PWM pulse to determine a dead time between the first switching state and the second switching state, and wherein the timing circuitry is configured to adjust the timing transitions by modifying the dead time based on the magnitude of the current measured by the current sensing circuitry.

10. A multiphase power converter, comprising:

a plurality of phases, each phase configured to transfer a portion of a total current of the multiphase power converter to a load connected with an output of the multiphase power converter and comprising at least two power stages coupled in parallel; and

a controller configured to generate a separate switching control signal for each phase,

wherein the same switching control signal is provided to each parallel coupled power stage of the same phase,

wherein each power stage of each phase is coupled to the output of the multiphase power converter, and the controller comprises:

a first switching device configured to connect the load to a supply voltage in a first switching state of the power stage;

a second switching device configured to connect the load to ground in a second switching state of the power stage;

an inductor configured to couple an output of the power stage to the output of the multiphase power converter;

driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in the first switching state, the second switching state, or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by corresponding switching control signals generated by the controller;

current sensing circuitry configured to measure current flowing through at least one of the switching devices; and

timing circuitry configured to adjust the timed transitions between the switching states so as to change an effective duration of the first and/or second switching states relative to a reference duration defined by the switching control signal generated by the controller for the phase comprising the power stage, wherein adjustment of the timed transitions is based on the magnitude of the current measured by the current sensing circuitry and is independent of currents measured for other power stages of the same phase.

11. The multiphase power converter of claim 10, wherein currents measured for power stages of a same phase are coupled to a same current sense input terminal of the controller.

12. The multiphase power converter of claim 11, wherein currents measured for power stages of a same phase are coupled to the same current sense input terminal of the controller via respective resistors.

13. The multiphase power converter of claim 10, wherein for each power stage of each phase, as the current measured by the current sensing circuitry of the power stage increases, the timing circuitry is configured to adjust the timed transitions such that the effective duration of the first switching state is decreased and/or the effective duration of the second switching state is increased relative to the switching control signal generated by the controller for the phase including the power stage.

14. The multiphase power converter of claim 10, wherein for each power stage of each phase, the timing circuitry is configured to adjust the timing transition based on a ratio of the magnitude of the current measured by the current sensing circuitry of the power stage to a reference current level.

15. The multiphase power converter of claim 14, wherein for each power stage of each phase, the reference current level is a maximum current threshold for the power stage.

16. The multiphase power converter of claim 10, wherein for each power stage of each phase, the timing circuitry is configured to adjust the timing conversion in a manner that is monotonic and linearly proportional to the magnitude of the current measured by the current sensing circuitry of the power stage.

17. An electronic system, comprising:

a circuit board; and

one or more electronic circuits attached to the board and presenting a load to a multiphase power converter or power supply attached to the circuit board,

wherein the multiphase power converter implements the power source, is configured to provide power to the load, and comprises:

a plurality of phases, each phase configured to deliver current to the load and comprising at least two power stages coupled in parallel; and

a controller configured to provide a separate switching control signal to each phase, wherein each power stage of each phase comprises:

a first switching device configured to connect the load to a supply voltage in a first switching state of the power stage;

a second switching device configured to connect the load to ground in a second switching state of the power stage;

driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in the first switching state, the second switching state, or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by corresponding switching control signals generated by the controller;

current sensing circuitry configured to measure current flowing through at least one of the switching devices; and

timing circuitry configured to adjust the timed transitions between the switching states so as to change an effective duration of the first and/or second switching states relative to a reference duration defined by the switching control signal generated by the controller for the phase comprising the power stage, wherein adjustment of the timed transitions is based on the magnitude of the current measured by the current sensing circuitry and is independent of currents measured for other power stages of the same phase.

18. The electronic system of claim 17, wherein for each power stage of each phase of the multiphase power converter, as the current measured by the current sensing circuitry of the power stage increases, the timing circuit is configured to adjust the timed transitions such that the effective duration of the first switching state is decreased and/or the effective duration of the second switching state is increased relative to the switching control signal generated by the controller for the phase including the power stage.

19. The electronic system of claim 17, wherein for each power stage of each phase of the multiphase power converter, the timing circuitry is configured to adjust the timing transitions based on a ratio of the magnitude of the current measured by the current sensing circuitry of the power stage to a reference current level.

20. The electronic system of claim 17, wherein for each power stage of each phase of the multiphase power converter, the timing circuitry is configured to adjust the timing transitions in a manner that is monotonic and linearly proportional to the magnitude of the current measured by the current sensing circuitry of the power stage.

Technical Field

Embodiments of the present disclosure generally relate to current sharing for multiphase power converters.

Background

For high power ICs such as microprocessors, high phase count multi-phase buck voltage regulators are often required to meet high current requirements. Multi-phase buck voltage regulators are an efficient way to connect power stages in parallel, support interleaving of phase PWM (pulse width modulation) pulses, and provide current balancing to ensure that current is distributed evenly among all available power stages. Generally, the greater the number of phases, the more PWM outputs and current sense inputs are required by the controller, thereby increasing pin count, complexity, and cost of the controller and system.

Methods such as parallel connection and use of phase multipliers or tripler/quadrupler increase the number of parallel power stages without increasing the phase count on the controller, which is typically limited to 8 or 16 total phases. The higher phase count controller is a niche device, which is expensive and uses non-standard placeholders.

In the case of parallel connection, where a single PWM input drives multiple power stages in parallel, current is not shared uniformly among the stages, thus causing current disruption to one or more of the power stages. Current disturbances can lead to over-current and over-temperature conditions.

In the case of phase multipliers and tripler/quadrupler, special driver circuits are required to independently drive the parallel power stages, alternating or modifying the PWM pulses so that the current is balanced between the parallel stages. However, the phase multiplier and tripler/quadrupler driver circuits are discrete devices, require the use of different layout schemes to support the use of parallel switches, and rely primarily on RDSon (transistor on-state resistance) sensing to provide current balancing.

Thus, there is a need for a low complexity solution that allows for parallel driving of power stages as one phase while reducing current disturbances between parallel power stages of the same phase.

Disclosure of Invention

According to one embodiment of a power stage of a multiphase power converter, the power stage comprises: a first switching device configured to connect an output node of the power stage to a supply voltage in a first switching state of the power stage; a second switching device configured to connect the output node to ground in a second switching state of the power stage; driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in a first switching state, a second switching state or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by switching control signals received by the power stage; current sensing circuitry configured to measure current flowing through at least one of the switching devices; and timing circuitry configured to adjust timed transitions between switching states so as to vary an effective duration of the first switching state and/or the second switching state relative to a reference duration defined by the switching control signal; wherein the adjustment of the timing transition is based on the current magnitude measured by the current sensing circuitry.

According to one embodiment of a multiphase power converter, the multiphase power converter comprises: a plurality of phases, each phase configured to transfer a portion of a total current of the multiphase power converter to a load connected with an output of the multiphase power converter and comprising at least two power stages coupled in parallel; and a controller configured to generate a separate switching control signal for each phase, wherein the same switching control signal is provided to each parallel coupled power stage of the same phase. Each power stage of each phase is coupled to an output of the multiphase power converter, and the controller comprises: a first switching device configured to connect the load to the supply voltage in a first switching state of the power stage; a second switching device configured to connect the load to ground in a second switching state of the power stage; an inductor configured to couple an output of the power stage to an output of the multiphase power converter; driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in a first switching state, a second switching state, or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by corresponding switching control signals generated by the controller; current sensing circuitry configured to measure current flowing through at least one of the switching devices; and timing circuitry configured to adjust timed transitions between switching states so as to change an effective duration of the first switching state and/or the second switching state relative to a reference duration defined by a switching control signal generated by the controller for a phase comprising the power stage, wherein the adjustment of the timed transitions is based on a current magnitude measured by the current sensing circuitry and is independent of currents measured for other power stages of the same phase.

According to one embodiment of an electronic system, the electronic system comprises: a circuit board and one or more electronic circuits attached to the board and presenting a load to a multiphase power converter or power supply attached to the circuit board. A multiphase power converter implements a power supply configured to provide power to a load and includes: a plurality of phases, each phase configured to deliver current to a load and comprising at least two power stages coupled in parallel; and a controller configured to provide a separate switching control signal to each phase. Each power stage of each phase comprises: a first switching device configured to connect the load to the supply voltage in a first switching state of the power stage; a second switching device configured to connect the load to ground in a second switching state of the power stage; driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in a first switching state, a second switching state, or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by corresponding switching control signals generated by the controller; current sensing circuitry configured to measure current flowing through at least one of the switching devices; and timing circuitry configured to adjust timed transitions between switching states so as to change an effective duration of the first switching state and/or the second switching state relative to a reference duration defined by a switching control signal generated by the controller for a phase comprising the power stage, wherein the adjustment of the timed transitions is based on a current magnitude measured by the current sensing circuitry and is independent of currents measured for other power stages of the same phase.

Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.

Drawings

The elements of the drawings are not necessarily to scale relative to each other. Like reference numerals designate corresponding similar parts. Features of the various illustrated embodiments may be combined unless they are mutually exclusive. Embodiments are depicted in the drawings and are described in detail in the following description.

FIG. 1 illustrates a block diagram of one embodiment of an electronic system including a load and a multiphase power converter configured to regulate an output voltage provided to the load.

Fig. 2 illustrates an example of a power stage included in a multiphase power converter in accordance with one embodiment.

Fig. 3 illustrates waveform diagrams of embodiments of adjusting timed transitions between switching states of power stages of a multiphase power converter.

Fig. 4 illustrates a waveform diagram of another embodiment of adjusting timed transitions between switching states of a power stage of a multiphase power converter.

Fig. 5 illustrates a block diagram of an embodiment of a timing circuit arrangement included in each power stage of a multiphase power converter for adjusting timed transitions between switching states of the power stages.

Fig. 6 illustrates a block diagram of another embodiment of a timing circuit arrangement included in each power stage of a multiphase power converter for adjusting timed transitions between switching states of the power stages.

FIG. 7 illustrates a block diagram of an embodiment of a timing circuit arrangement included in each power stage of a multiphase power converter for adjusting timed transitions between switching states of the power stages.

FIG. 8 illustrates a block diagram of an embodiment of a timing circuit arrangement included in each power stage of a multiphase power converter for adjusting timed transitions between switching states of the power stages.

Detailed Description

Embodiments described herein provide a power stage for a multiphase power converter having an anti-current disturbance scheme built into the power stage. Two or more of these power stages may be coupled in parallel to form one phase of a multiphase power converter without risking current disturbances by one or more power stages of the same phase. As the current in the power stage increases, each power stage uses its own current sensing circuit information to modify its effective duty cycle. When connected in parallel, each parallel group of power stages may share a common switching control input, such as a common PWM input, and the power stage outputs may be connected together via separate inductors. Such a system can increase current handling capability as long as current is shared evenly between power stages.

If the currents in the set of parallel coupled power stages are not uniform, the switching behavior is adjusted such that the currents will be reduced in each power stage carrying a disproportionately higher current, thereby reducing the current disturbance of one or more power stages of the same phase. The current sense pins of the power stages coupled together to form the same phase may be connected together so that the parallel power stages may then interface with components that the controller sees as a single phase, the current handling capability of which is equivalent to the sum of the capabilities of the parallel power stages. This effectively allows the number of parallel stages supported by the multi-phase controller to be increased proportionally to the number of parallel power stages in each bank. Thus, the techniques described herein allow for "high-phase" power converter systems where interleaving and current sharing still exists between groups of phases, and employ an anti-current-disturbance scheme implemented by parallel power stages of the same group/phase to mitigate current disturbance and allow higher currents to be achieved.

The term "power converter" as used herein broadly refers to any type of power converter or Voltage Regulator (VR) that provides one or more regulated voltages to one or more electronic loads, such as an ethernet switch, an ASIC (application specific integrated circuit), a memory device, a processor, such as a Central Processing Unit (CPU), a microprocessor, a Graphics Processing Unit (GPU), a Digital Signal Processor (DSP), an Artificial Intelligence (AI) accelerator, an image processor, a network or packet processor, a coprocessor, a multi-core processor, a front-end processor, a baseband processor, etc. For example, the power converter may be a buck converter, a boost converter, a buck-boost converter, a switched capacitor voltage regulator, a step-up converter, or the like. The power converter may be implemented as a power device module.

The term "power device module" as used herein refers to a packaged functional component comprising at least one power switch of a power stage, e.g. used to convert a voltage from one level to another, as is done in power conversion and voltage regulation. The power device module may further comprise a driver circuit for driving the at least one power switch. The power device module may additionally include a controller for controlling the driver circuit to implement the power converter. The controller and/or driver functionality may alternatively be implemented external to the power device module. The driver circuit of the at least one power switch comprised in the power device module may also be external to the power device module. Various passive components (such as capacitors and/or inductors) that make up the power converter may be included in the power device module, surface mounted to the power device module, located on a separate circuit board, and so forth.

Next, various embodiments of an anti-current-disturbance scheme for a power stage, a multiphase power converter including a set of parallel-coupled power stages each implementing an anti-current-disturbance scheme, and an electronic system including a multiphase power converter will be described in more detail.

Fig. 1 illustrates one embodiment of an electronic system 100, the electronic system 100 including one or more electronic circuits attached to a circuit board 103, such as a PCB (printed circuit board), and presenting a load 102 to a multiphase power converter 104 or power supply attached to the circuit board 103. The multiphase power converter 104 implements a power supply and provides power to the load 102 by regulating an output voltage (Vout) provided to the load 102. The load 102 may be any type of electronic load that requires a regulated supply voltage. For example, the load 102 may be an ethernet switch, an ASIC, a memory device, a processor, such as a CPU, microprocessor, GPU, DSP, AI accelerator, image processor, network or packet processor, co-processor, multi-core processor, front-end processor, baseband processor, or the like. For example only, multiphase power converter 104 is shown in fig. 1 as a buck converter. In this example, multi-phase power converter 104 includes two or more groups of power stages 106 coupled in parallel, each group of parallel-coupled power stages 106 forming one phase of multi-phase power converter 104.

In general, multi-phase power converter 104 may be any type of multi-phase power converter or voltage regulator that provides one or more regulated voltages (Vout) to load 102. For example, the multi-phase power converter 104 may be a buck converter, a boost converter, a buck-boost converter, a switched capacitor voltage regulator, a step-up converter, etc., as shown in fig. 1, and may be implemented as a power device module as previously described herein.

Fig. 1 shows two phases, each having two power stages 106 coupled in parallel. This is for ease of illustration only. The number of phases depends on the phase count of the controller 108 and the number of parallel coupled power stages 106 per phase depends on the current demand of the load 102. Thus, the number of phases and the number of parallel coupled power stages 106 per phase depends on the selection of the controller 108 and the load environment. Typically, the controller 108 is an N-phase controller and each phase has m power stages 106 coupled in parallel, where N is a positive integer ≧ 2 and m is a positive integer ≧ 2.

Each power stage 106 is configured to provide a current (ips) to the load 102 via a respective inductor (L). The output capacitor (Cout) of the multiphase power converter 104 may be implemented, for example, as a capacitor bank to reduce output voltage ripple. The controller 108 is configured to generate a separate switching control signal (PWM _ N) for each phase to regulate the output voltage Vout provided to the load 102. The power stages 106 included in the same phase receive the same switching control signal.

The power converter controller 108 includes a modulator 110 for generating a switching control signal 'PWM _ N' for each phase to regulate the output voltage Vout provided to the load 102. In one embodiment, modulator 110 implements Pulse Width Modulation (PWM).

The controller 108 may also include a current sensing and balancing circuit 112 for sensing each phase current delivered by its parallel-coupled power stage 106 at a corresponding current sensing terminal (ISEN _ N) of the controller 108 and converting the sensed current information into phase current information (iph _ info). The current sensing and balancing circuit 112 also converts the phase current information into an adjustment amount (Adj _ duty) of the duty cycle generated by the modulator 110 for each individual phase to adjust the phase currents so that the phase currents remain balanced in the case of multi-phase operation. The output current (ips) of each power stage 106 included in the same phase may be combined such that the controller 108 has a single current sense terminal "ISEN _ N" for each phase. In one embodiment, the current "ips" measured for the same phase of the power stage 106 is coupled to the same current sense input terminal "ISEN _ N" of the controller 108 via a respective resistor. The current sensing and balancing circuit 112 may also provide overcurrent protection and/or output current telemetry (analog voltage or current) on an output pin (not shown).

The controller 108 may also include a voltage position unit 114, the voltage position unit 114 generating a target voltage regulation signal (Vreg tgt) indicative of a target voltage regulation set point. The voltage position unit 114 may determine the target voltage regulation set point based on the phase current information "iph _ info" from the current sensing and balancing circuit 112 and, for example, voltage ID information (VID) provided by the load 102.

The controller 108 may also include a voltage sensing circuit 116, the voltage sensing circuit 116 providing voltage error information (Verr) to the modulator 110 to determine the duty cycle of the power stage 106 included in each phase. The voltage sensing circuit 116 may determine the voltage error information "Verr" based on the target voltage adjustment signal "Vreg _ tgt" from the voltage position unit 114 and the measured/sensed adjusted output voltage Vout.

The modulator 110 included in the controller 108 generates a separate switching control signal "PWM _ N" for each phase of the multiphase power converter based on the voltage error information "Verr" from the voltage sensing circuit 116 and the duty cycle adjustment amount "Adj _ duty" from the current sensing and balancing circuit 112 such that the output voltage Vout of the power converter 104 is regulated. Each power stage 106 included in each phase of the multi-phase power converter 104 has a corresponding driver circuit arrangement 118. The power stage 106 and corresponding driver circuitry 118, which may include the driver circuitry 118, a high-side switching device (HS), a low-side switching device (LS), and internal and interface circuitry (not shown), may be integrated on the same semiconductor die or in the same package to provide a single trivalent PWM input "PWM _ N" that controls when the high-side switching device "HS" is turned on, when the low-side switching device "LS" is turned on, or when none of the switching devices are turned on.

More specifically, the high-side switching device "HS" of each power stage 106 is configured to connect the output node 120 of the power stage 106 to the supply voltage (Vin) in a first switching state of the power stage 106. The low-side switching device "LS" of the same power stage 106 is configured to ground the output node 120 in the second switching state of the power stage 106. The high-side switching device "HS" and the low-side switching device "LS" may be power MOSFETs (metal oxide semiconductor field effect transistors), IGBTs (insulated gate bipolar transistors), HEMTs (high electron mobility transistors), or the like. The driver circuitry 118 associated with the corresponding power stage 106 generates gate drive signals ("HG", "LG" in fig. 2) for the gates of the high-side and low-side switching devices "HS", LS "for setting the power stage 106 in a first switching state, a second switching state, or a non-switching state in which both switching devices are in an off state. The duration of each state and the timing transitions between the states are indicated by a corresponding switching control signal "PWM _ N" provided by the modulator 110. The current sensing circuitry 122 included in each power stage 106 measures the current flowing through at least one of the switching devices of the power stage 106. The timing circuitry 124 included in each power stage 106 adjusts the timed transitions between switching states to vary the effective duration (e.g., duty cycle) of the first and/or second switching states relative to a reference duration defined by the corresponding switching control signal "PWM _ N" received by the modulator 110. The adjustment of the timing transitions by the timing circuitry 124 is based on the current magnitude measured by the current sensing circuitry 122 included in the power stage. In this way, each individual power stage 106 may limit its current disturbance based on its own internal current measurement information.

The anti-current perturbation scheme described herein is different from current balancing. As previously explained herein in connection with the operation of the current sensing and balancing circuit 112, current balancing is a scheme in which the controller 108 attempts to balance the current across the phases based on the difference between the phase currents so that each phase delivers approximately the same current to the load 102. The anti-current jamming scheme implemented by each power stage 106 instead adjusts the effective duration (e.g., duty cycle) of the first switching state and/or the second switching state based on its own absolute current measurement, independent of any other power stage current.

Fig. 2 illustrates an example of the power stage 106 according to one embodiment. The driver circuit arrangement 118 of the power stage 106 comprises: a high-side driver 200 for driving a gate of the high-side switching device "HS" using a high-side gate driving signal "HG"; and a low side driver 202 for driving the gate of the low side switching device "LS" using the low side gate drive signal "LG". The driver circuitry 118 further comprises level shifting circuitry 204 for level shifting the input signal of the high-side driver 200 based on the reference voltage "Vdrive", since the high-side switching device "HS" is referenced to the power stage input voltage Vin. The bootstrap power supply 206 of the driver circuit device 118 powers the level-shifting circuit device 204 and the high-side driver 200.

Each power stage 106 of the same phase receives a switching control signal "PWM _ N" for that phase from the controller 108. The first comparator 208, which references Vdrive, compares the incoming switching control signal "PWM _ N" to a first (High) threshold "Vih" to indicate when the switching control signal "PWM _ N" is at a logic High level "High". The second comparator 210, also referenced to Vdrive, compares the incoming switching control signal "PWM _ N" to a second (Low) threshold "Vil" to indicate when the switching control signal "PWM _ N" is at a logic Low level "Low". According to the embodiment shown in fig. 2, the power stage current sensing circuitry 122 is a current monitor. The current monitor 122 measures the output current "ips" of the power stage 106 before the current enters the corresponding output inductor L. The current monitor 122 provides the measured current information to the power stage timing circuitry 124 and also reports the measured current information to the controller 108. The current monitor 122 may measure the current flowing through only the high-side switching device "HS", the current flowing through only the low-side switching device "LS", or the current flowing through both the high-side switching device "HS" and the low-side switching device "LS".

The timing circuitry 124 included in the power stage 106 includes timing logic 212 for determining the gate signal "G _ H" of the high-side switching device "HS" and the gate signal "G _ L" of the low-side switching device "LS". Timing circuit arrangement 124 also includes dead-time logic 214, dead-time logic 214 ensuring that high-side switching device "HS" and low-side switching device "LS" are not simultaneously conductive by inserting a dead-time between gate signal "G _ H" of high-side switching device "HS" and gate signal "G _ L" of low-side switching device "LS".

The timing circuitry 124 adjusts the timing transitions between the switching states (HS on and LS off, or HS off and LS on) to vary the effective duration of the first switching state (HS on and LS off) and/or the second switching state (HS off and LS on) relative to a reference duration defined by the switching control signal "PWM _ N" received by the power stage 106, the adjustment of the timing transitions being based on the current magnitude measured by the current sensing circuitry 122. According to the embodiment shown in fig. 2, the timing circuitry 124 includes duty cycle adjustment logic 216 to adjust the timing transitions.

The high-side driver 200 of the driver circuitry 118 sets the power stage 106 in the first switching state by activating a high-side gate drive signal "HG" applied to the gate of the high-side switching device "HS". The low side driver 202 of the driver circuit device 118 places the power stage 106 in the second switching state by activating a low side gate drive signal "LG" applied to the gate of the low side switching device "LS". The power stage 106 is set in a non-switching state by the high-side driver 200 deactivating the high-side gate drive signal "HG" and the low-side driver 202 deactivating the low-side gate drive signal "LG". As explained previously herein, the duration of each state and the timed transitions between states are indicated by the switching control signal "PWM _ N" received by the power stage 106. The driver circuitry 118, sensing circuitry 122 and timing circuitry 124 may be integrated into a single unit as shown by the dashed box in fig. 2. The driver integration may include all components of the power stage 106, except for the high-side switching device "HS", the low-side switching device "LS", and the output inductor L.

Fig. 3 illustrates an embodiment in which the switching control signal "PWM _ N" received by the power stage 106 is a PWM signal. In fig. 3, the switching control signal "PWM _ N" input represents a target duty ratio of the power stage output. "Tdel _ HG" is a PWM low transition delay applied by timing logic 212 to high-side gate signal "G _ H" for delaying when high-side gate signal "G _ H" transitions from high to low. "Tdead _ HG" is a dead time delay added by dead time logic 214 to the high side gate signal "G _ H" generated by timing logic 212 for delaying when G _ H transitions from low to high. "Tdead _ LG" is a dead-time delay added by dead-time logic 214 to the low-side gate signal "G _ L" generated by timing logic 212 for delaying when G _ L transitions from low to high. "Tdead _ HG" and "Tdead _ LG" may be variable delays set by dead time logic 214, and may be based on digital or analog delays. "Tdead _ LG" may be different from "Tdead _ HG".

Further in fig. 3, "Tadj _ G _ H" is a variable low-to-high transition delay generated by the duty cycle adjustment logic 216 for the high side gate signal "G _ H". "Tadj _ G _ L" is a variable high-to-low transition delay generated by the duty cycle adjustment logic 216 for the low-side gate signal "G _ L". The ranges of "Tadj _ G _ H" and "Tadj _ G _ L" may be similar to the dead time adjustment amounts "Tdead _ HG" and "Tdead _ LG", e.g., about 5ns to 30 ns. Typically, "Tadj _ G _ H" and "Tadj _ G _ L" are implemented with variable delays (analog or digital) such that the delay increases with increasing power stage current, thereby reducing the effective on-time or duty cycle of the power stage 106, such that a wider PWM input is required to achieve the same effective duty cycle, thereby reducing current disturbances.

Timing logic 212 and dead time logic 214 of timing circuit arrangement 124 maintain PWM duty cycles in the G _ H and G _ L gate signals while optimizing delay and ensuring non-overlap in the G _ H and G _ L gate signals to avoid simultaneous conduction of the two switching devices "HS", "LS" and to avoid shoot-through current.

As the current measured by the current sensing circuitry 122 of the power stage 106 increases, the duty cycle adjustment logic 216 of the timing circuitry 124 adjusts the high-side timing transition "Tadj _ G _ H" and/or the low-side timing transition "Tadj _ G _ L" such that the duty cycle of the first switching state is decreased and/or the duty cycle of the second switching state is increased relative to the switching control signal "PWM _ N". For example, the duty cycle of the first switching state may be reduced relative to the switching control signal "PWM _ N" by increasing "Tadj _ G _ H" such that the high-side gate signal "G _ H" experiences a greater delay before transitioning from low to high. Therefore, the on-time of the high-side switching device "HS" is less than the time indicated by the duty ratio of the switching control signal "PWM _ N". In another example, the duty cycle of the second switching state may be increased relative to the switching control signal "PWM _ N" by increasing "Tadj _ G _ L" such that the low-side gate signal "G _ L" experiences more delay before transitioning from high to low. Therefore, the on-time of the low-side switching device "LS" is longer than the time indicated by the duty cycle of the switching control signal "PWM _ N".

As the current measured by the current sensing circuitry 122 of the power stage 106 decreases, the duty cycle adjustment logic 216 of the timing circuitry 124 adjusts the high-side timing transition "Tadj _ G _ H" and/or the low-side timing transition "Tadj _ G _ L" such that the duty cycle of the first switching state is increased and/or the duty cycle of the second switching state is decreased relative to the switching control signal "PWM _ N". For example, the duty cycle of the first switching state may be increased relative to the switching control signal "PWM _ N" by decreasing "Tadj _ G _ H" such that the high-side gate signal "G _ H" experiences less delay before transitioning from low to high. Therefore, the on-time of the high-side switching device "HS" is longer than the time indicated by the duty ratio of the switching control signal "PWM _ N". In another example, the duty cycle of the second switching state may be reduced relative to the switching control signal "PWM _ N" by reducing "Tadj _ G _ L" such that the low side gate signal "G _ L" experiences less delay before transitioning from high to low. Thus, the on-time of the low-side switching device "LS" is less than the time indicated by the duty cycle of the switching control signal "PWM _ N".

Duty cycle adjustment logic 216 of timing circuit arrangement 124 modifies the timing of the signal provided by timing logic 212 such that the current sense information of power stage 106 is used to adjust the effective duty cycle of the power stage switching such that as the power stage current increases, the effective duty cycle of the half-bridge ("HS" and "LS") switching is reduced relative to the PWM input duty cycle. That is, as the power stage current increases, the duty cycle adjustment logic 216 of the timing circuitry 124 narrows the effective duty cycle of the power stage 106. This provides protection against current disturbance when the power stages 106 are used in parallel mode. No increase in controller pin count or further modification of the power stage 106 is required and the anti-current disturb scheme is not related to the current of other power stages 106 coupled in parallel.

In one embodiment, the duty cycle adjustment logic 216 of the timing circuitry 124 adjusts the high-side timing transition "Tadj _ G _ H" and/or the low-side timing transition "Tadj _ G _ L" based on a ratio of the current amplitude measured by the current sensing circuitry 122 and the reference current level. For example, the reference current level may be a maximum current threshold of the power stage 106.

Fig. 4 illustrates an embodiment in which the duty cycle adjustment logic 216 of the timing circuitry 124 adjusts the high-side timing transitions "Tadj _ G _ H" and/or the low-side timing transitions "Tadj _ G _ L" in a manner that is monotonic and linearly proportional to the current magnitude measured by the current sensing circuitry 122. As the current measured by the current sensing circuitry 122 of the power stage 106 ("power stage current") increases, the duty cycle adjustment logic 216 adjusts the high-side timing transition "Tadj _ G _ H" and/or the low-side timing transition "Tadj _ G _ L" such that the duty cycle of the first switching state is decreased and/or the duty cycle of the second switching state is increased relative to the switching control signal "PWM _ N". Conversely, as the current measured by the current sensing circuitry 122 of the power stage 106 decreases, the duty cycle adjustment logic 216 adjusts the high-side timing transition "Tadj _ G _ H" and/or the low-side timing transition "Tadj _ G _ L" such that the duty cycle of the first switching state is increased and/or the duty cycle of the second switching state is decreased relative to the switching control signal "PWM _ N".

Fig. 5 illustrates another embodiment of the timing circuitry 124 included in each power stage 106. According to this embodiment, the timing logic 212 detects the incoming PWM signal "PWM _ N" and outputs the high-side and low-side PWM signals "PWM _ H", "PWM _ L", respectively, based on the signal levels "high", "low" detected by the comparators 208, 210. The PWM input detection determines when the PWM should be effectively set to high ("PWM _ H") or low ("PWM _ L"). The signals "PWM _ H" and "PWM _ L" may be both low, but not both high. In addition to the threshold and hysteresis, timing logic 212 may ensure a minimum pulse width for the two signals "PWM _ H", "PWM _ L" to avoid very narrow pulses changing the power switch state.

Dead time logic 214 includes a first duty cycle adjustment circuit including a first delay Δ₁The first logic gate 302 is used to extend the high side dead time "Tdead _ HG" by blocking the high side gate signal G _ H provided to the power stage driver circuitry 118 by the first buffer 304. Dead time logic 214 further includes a second duty cycle adjustment circuit including a second delay Δ₂And a second logic gate 308, the second logic gate 308 for extending the low side dead time "Tdead _ LG" by blocking the low side gate signal G _ L provided to the power stage driver circuit device 118 by the second buffer 310. The high-side and low-side gate signals G _ H, G _ L are delayed versions of the respective PWM signals "PWM _ H", "PWM _ L" detected by timing logic 212.

According to the embodiment shown in FIG. 5, duty cycle adjustment logic 216 includes logic having a third delay Δ₃A third delay block 312 and a third logic gate 314. The duty cycle adjustment logic 216 derives the PWM pulse "PWM _ L _ Adj" from the switching control signal "PWM _ L" for the low-side switching device "LS" and is based on the variable delay Δ of the third delay block 312₃The timing transitions are adjusted by extending the PWM pulses. Variable delay delta of third delay block 312₃Based on the current magnitude measured by the current sensing circuitry 122 for the power stage 106. The third logic gate 314 may be implemented as a logical OR gate such that a PWM pulse "PWM _ L _ Adj" derived from the switching control signal "PWM _ L" for the low-side switching device "LS" is activated whenever the switching control signal "PWM _ L" OR a delayed version of the switching control signal "PWM _ L" is activated. The duty cycle adjustment logic 216 may alternatively derive a PWM pulse (not shown) from the switching control signal "PWM _ H" for the high-side switching device "HS" and adjust the timing transitions by increasing or decreasing the PWM pulse based on a variable delay based on the magnitude of the current measured by the current sensing circuitry 122 for the power stage 106. The duty cycle adjustment logic 216 may alternatively derive the PWM pulses of the two switching control signals "PWM _ H", "PWM _ L" based on a variable delay based on the current magnitude measured by the current sensing circuitry 122 for the power stage 106. In fig. 5, the PWM _ H block path is deleted or modified to allow for pulse width adjustment at the beginning of the PWM _ H period.

Fig. 6 illustrates another embodiment of the duty cycle adjustment logic 216 included in the timing circuitry 124 of each power stage 106. According to this embodiment, the duty cycle adjustment logic 216 includes a first edge sensing circuit 400 to detect a rising or falling edge of the low side gate signal "G _ L". The duty cycle adjustment logic 216 also includes a second edge sensing circuit 402 to detect a rising or falling edge of the high-side gate signal "G _ H" or the output voltage Vout. The respective edge adjustment circuits 404, 406 apply corresponding variable adjustment amounts "I _ adj _ H"/"I _ adj _ L" based on the current magnitude measured by the current sensing circuitry 122 for the power stage 106. Edge comparison logic 408 compares the edges of the adjusted high-side PWM pulses to the edges of the adjusted low-side PWM pulses to determine an amount of dead-time adjustment between the first switching state and the second switching state. Dead time logic 214 adjusts the timing transitions between switching states by modifying the dead time based on the output of edge comparison logic 408, which in turn is based on the current magnitude measured by current sensing circuitry 122 of power stage 106.

Fig. 7 illustrates another embodiment of the duty cycle adjustment logic 216 included in the timing circuitry 124 of each power stage 106. According to this embodiment, the duty cycle adjustment logic 216 includes a flow limiting buffer 500 for implementing a variable delay. The current limit buffer 500 has different adjustment amounts for the ON delay and the OFF delay. The corresponding switching control signals "PWM _ H", "PWM _ L" generated by the timing logic 212 of the timing circuitry 124 are delayed by the inverter 502. A non-delayed version of the switching control signal "PWM _ H"/"PWM _ L" actuates the first switch 504, and a delayed version of the switching control signal "PWM _ H"/"PWM _ L" actuates the second switch 506. The first switch 504 connects the first current source k1 to the voltage ramp node "V_RAMP". The second switch 506 ramps the voltage to the node "V_RAMP"is connected to a second current source k 2. Voltage ramp node "V_RAMPAlso connected to the output buffer 508 and capacitor C1.

The lower half of FIG. 7 shows the voltage ramp node "V_RAMP"voltage at" varies according to the switching control signal "PWM _ H"/"PWM _ L". The lower half of fig. 7 also shows the output "OUT" of the current limiting buffer 500, which corresponds to the adjusted PWM pulse "PWM _ L _ Adj"/"PWM _ H _ Adj". Voltage ramp node "V_RAMPThe ramp-up curve of the voltage at "is determined by the first current source k1 and the ramp-down curve of the voltage is determined by the second current source k 1. Thus, the values of the current sources k1, k2 determine the amount of timing transition adjustment implemented by the duty cycle adjustment logic 216. The values of the current sources k1, k2 are based on the current magnitude measured by the current sensing circuitry 122 of the power stage 106. Since two current sources k1, k2 are used, both ON delay and OFF delay can be performedThe adjustment is performed.

Fig. 8 illustrates another embodiment of the duty cycle adjustment logic 216 included in the timing circuitry 124 of each power stage 106. According to this embodiment, the duty cycle adjustment logic 216 includes a pulse widening circuit 600 for implementing a variable delay. The embodiment shown in fig. 8 is similar to the embodiment shown in fig. 7. However, the difference is that the first switch 504 ramps the voltage to the node "V_RAMP"connected to the voltage source VDD instead of a current source to form the pulse widening circuit 600. As shown in the lower half of fig. 8, the pulse widening circuit 600 adjusts the width of the corresponding switching control signal "PWM _ H"/"PWM _ L" based on the variable delay realized by the current source k 2.

As explained previously herein, each power stage 106 of the multi-phase power converter 104 uses an absolute current measurement of that power stage 106, regardless of any other power stage current, in adjusting the timed transitions between switching states. The anti-current perturbation scheme described herein does not perform current balancing, but rather ensures that no runaway conditions exist. The anti-current perturbation scheme utilizes a relationship between the effective duty cycle and the input duty cycle, which has the following characteristics: as the current increases, the resulting effective duty cycle becomes smaller, thereby reducing the current delivered by the power stage 106. The nominal duty cycle may be in the range of 12% -15%, and the adjustment achieved by the anti-current perturbation scheme may be in the range of 5% -8% of the nominal duty cycle.

For example, the power stage current range may be 60A to 100A at maximum. Where four power stages 106 are coupled in parallel to form a phase of multiphase power converter 104, two power stages 106 may attempt to provide 50A, where the nominal duty cycle is 14% at 50A. The controller 108 adjusts the duty cycle based on the total output current and the current balance between the phases. If the third power stage 106 in the phase output 60A and the fourth power stage 106 in the same phase output 40A, a 0.3% duty cycle difference is generated between the power stages 106. A duty cycle difference of 0.3% constitutes a significant current difference over time. The power stage 106 delivering 60A instead of 50A begins to lose current because the anti-current scrambling scheme described herein produces a narrower duty cycle for that power stage 106, while the power stage 106 outputting 40A begins to draw current because the anti-current scrambling scheme described herein produces a wider duty cycle for the power stage 106. Although the controller 108 attempts to balance all power stages 106 across all phases, each individual power stage 106 within the same phase implements the described anti-current-disturb scheme.

The anti-current jamming scheme may be open-loop, where the internal signal is generated based on individual power stage current sensing information. The internal signal may be used to vary the internal power stage delay to achieve an effective reduction in duty cycle. Returning to the four power stage example, where one power stage 106 is at 60A, two power stages 106 are at 50A, and the fourth power stage 106 is at 40A, the variable delay may be implemented on the rising edge of the corresponding PWM signal. The delay of the power stage 106 at 60A can be implemented as a function of the absolute current of the power stage 106, which effectively narrows the PWM pulse width. Each power stage 106 of the same phase implements an anti-current-disturb scheme in the same manner, but based on its own absolute current measurement.

While various embodiments of the timing circuit arrangement 124 for implementing an anti-current jamming scheme have been described, other implementations are contemplated. For example, the timing circuitry 124 typically has a mix of fast and slow buffers (delay circuits), timing logic, and current sensing circuits. If the current output by a particular power stage 106 exceeds expectations, the timing circuitry 124 may use more slow buffers to increase the internal power stage delay. If the current output by the other power stage 106 is less than expected, the timing circuitry 124 may use more fast buffers to reduce internal power stage delay. In either case, the delay is proportional to the absolute current of the individual power stage 106. The anti-current scrambling scheme may be implemented in the analog domain if implemented in the power stage driver circuitry 118, but may alternatively be implemented in the digital domain. Many different types of techniques may be used to implement the variable delay associated with the anti-current disturbance scheme, including but not limited to voltage control, current control, varactors, and the like.

Although the present disclosure is not so limited, the following numbered examples illustrate one or more aspects of the present disclosure.

Example 1: a power stage of a multiphase power converter, the power stage comprising: a first switching device configured to connect an output node of the power stage to a supply voltage in a first switching state of the power stage; a second switching device configured to connect the output node to ground in a second switching state of the power stage; driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in a first switching state, a second switching state or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by control signals received by the power stage; current sensing circuitry configured to measure current flowing through at least one of the switching devices; and timing circuitry configured to adjust a timing transition between the switching states so as to change an effective duration of the first switching state and/or the second switching state relative to a reference duration defined by the control signal, wherein the adjustment of the timing transition is related to the current amplitude measured by the current sensing circuit.

Example 2. the power stage of example 1, wherein the timing circuitry is configured to adjust the timing transitions such that an active duration of the first switching state is reduced and/or an active duration of the second switching state is increased relative to the switching control signal as the current measured by the current sensing circuit increases.

Example 3. the power stage of examples 1 or 2, wherein the timing circuitry is configured to adjust the timing transition based on a ratio of a current magnitude measured by the current sensing circuitry to a reference current level.

Example 4. the power stage of example 3, wherein the reference current level is a maximum current threshold for the power stage.

Example 5. the power stage of any of examples 1 to 4, wherein the timing circuitry is configured to adjust the timing transitions in a manner that is monotonic and linearly proportional to a current magnitude measured by the current sensing circuitry.

Example 6. the power stage of any of examples 1 to 5, wherein the timing circuitry is configured to derive the PWM pulse from a control signal for the first switching device and/or the second switching device, and wherein the timing circuitry is configured to adjust the timing transition by spreading the PWM pulse based on a variable delay based on a current magnitude measured by the current sensing circuitry.

Example 7. the power stage according to example 6, wherein the variable delay is implemented as a flow limit buffer that makes different adjustments to the ON delay and the OFF delay.

Example 8. the power stage of example 6, wherein the variable delay is implemented as a pulse widening circuit.

Example 9. the power stage of any of examples 1 to 8, wherein the timing circuitry is configured to derive the first PWM pulse from the control signal for the first switching device and to derive the second PWM pulse from the control signal for the second switching device, wherein the timing circuitry is configured to compare an edge of the first PWM pulse to an edge of the second PWM pulse to determine a dead time between the first switching state and the second switching state, and wherein the timing circuitry is configured to adjust the timing transitions by modifying the dead time based on a current magnitude measured by the current sensing circuitry.

Example 10 a multiphase power converter, comprising: a plurality of phases, each phase configured to transfer a portion of a total current of the multiphase power converter to a load connected with an output of the multiphase power converter and comprising at least two power stages coupled in parallel; and a controller configured to generate a separate switching control signal for each phase, wherein the same switching control signal is provided to each parallel coupled power stage of the same phase. Each power stage of each phase is coupled to an output of the multiphase power converter and includes: a first switching device configured to connect the load to the supply voltage in a first switching state of the power stage; a second switching device configured to connect the load to ground in a second switching state of the power stage; an inductor configured to couple an output of the power stage to an output of the multiphase power converter; driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in a first switching state, a second switching state, or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by corresponding switching control signals generated by the controller; current sensing circuitry configured to measure current flowing through at least one of the switching devices; and timing circuitry configured to adjust timed transitions between switching states so as to change an effective duration of the first switching state and/or the second switching state relative to a reference duration defined by a switching control signal generated by the controller for a phase comprising the power stage, wherein the adjustment of the timed transitions is based on a current magnitude measured by the current sensing circuitry and is independent of currents measured for other power stages of the same phase.

Example 11 the multiphase power converter of example 10, wherein the currents measured for the power stages of the same phase are coupled to the same current sense input terminal of the controller.

Example 12. the multiphase power converter of example 11, wherein the currents measured for the power stages of the same phase are coupled to the same current sense input terminal of the controller via respective resistors.

Example 13 the multiphase power converter of any of examples 10 to 12, wherein for each power stage of each phase, as the current measured by the current sensing circuitry of the power stage increases, the timing circuit is configured to adjust the timing transitions such that an effective duration of the first switching state is reduced and/or an effective duration of the second switching state is increased relative to a switching control signal generated by the controller for the phase comprising the power stage.

Example 14 the multiphase power converter of any of examples 10 to 13, wherein for each power stage of each phase, the timing circuitry is configured to adjust the timing transition based on a ratio of a current amplitude measured by the current sensing circuitry of the power stage to a reference current level.

Example 15. the multiphase power converter of example 14, wherein for each power stage of each phase, the reference current level is a maximum current threshold for the power stage.

Example 16 the multiphase power converter of any of examples 10 to 15, wherein for each power stage of each phase, the timing circuit is configured to adjust the timing transitions in a manner that is monotonic and linearly proportional to a current magnitude measured by a current sensing circuit of the power stage.

Example 17. an electronic system, comprising: a circuit board and one or more electronic circuits attached to the board and presenting a load to a multiphase power converter or power supply attached to the circuit board. A multiphase power converter implements a power supply configured to provide power to a load and includes: a plurality of phases, each phase configured to deliver current to a load and comprising at least two power stages coupled in parallel; and a controller configured to provide a separate switching control signal to each phase, wherein each power stage of each phase comprises: a first switching device configured to connect the load to the supply voltage in a first switching state of the power stage; a second switching device configured to connect the load to ground in a second switching state of the power stage; driver circuitry configured to generate gate drive signals for the gates of the first and second switching devices to set the power stage in a first switching state, a second switching state, or a non-switching state in which both switching devices are open, wherein the duration of each state and the timing transitions between the states are indicated by corresponding switching control signals generated by the controller; current sensing circuitry configured to measure current flowing through at least one of the switching devices; and timing circuitry configured to adjust timed transitions between switching states so as to change an effective duration of the first switching state and/or the second switching state relative to a reference duration defined by a switching control signal generated by the controller for a phase comprising the power stage, wherein the adjustment of the timed transitions is based on a current magnitude measured by the current sensing circuitry and is independent of currents measured for other power stages of the same phase.

Example 18 the electronic system of example 17, wherein for each power stage of each phase of the multiphase power converter, as the current measured by the current sensing circuit of the power stage increases, the timing circuit is configured to adjust the timing transitions such that an active duration of the first switching state is reduced and/or an active duration of the second switching state is increased relative to a switching control signal generated by the controller for the phase including the power stage.

Example 19 the electronic system of examples 17 or 18, wherein, for each power stage of each phase of the multiphase power converter, the timing circuitry is configured to adjust the timing conversion based on a ratio of a current amplitude measured by the current sensing circuitry of the power stage to a reference current level.

Example 20 the electronic system of any of examples 17 to 19, wherein, for each power stage of each phase of the multiphase power converter, the timing circuitry is configured to adjust the timing conversion in a manner that is monotonic and linearly proportional to a current magnitude measured by current sensing circuitry of the power stage.

Terms such as "first," "second," and the like, are used to describe various elements, regions, sections, etc. and are also intended to be limiting. Like terms refer to like elements throughout the specification.

As used herein, the terms "having," "including," "comprising," and the like are open-ended terms that indicate the presence of stated elements or features, but do not exclude other elements or features. The articles "a," "an," and "the" are intended to include the plural as well as the singular, unless the context clearly indicates otherwise.

It is to be understood that features of the various embodiments described herein may be combined with each other, unless specifically noted otherwise.

Although specific embodiments have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments shown and described without departing from the scope of the present invention. This application is intended to cover any adaptations or variations of the specific embodiments discussed herein. Therefore, it is intended that this invention be limited only by the claims and the equivalents thereof.