阅读说明：本技术 上电复位信号产生器以及相关的电子装置 (Power-on reset signal generator and related electronic device ) 是由 王维铁 郝报田 李超 于 2018-09-03 设计创作，主要内容包括：本发明公开了上电复位信号产生器以及相关的电子装置。上电复位信号产生器包含检测电路与比较器。检测电路对电源电压进行检测操作以产生一组检测信号,且包含：多组晶体管,堆迭且耦接于电源电压与接地电压之间,其中每一组晶体管包含第一晶体管与第二晶体管,分别位于第一电流路径与第二电流路径；以及第一电阻器与第二电阻器,耦接于两组晶体管之间,分别位于第一电流路径与第二电流路径；以及第三电阻器,耦接于电源电压与多组晶体管之间。比较器从检测电路接收该组检测信号,且比较该组检测信号以产生上电复位信号。本发明的好处例如：上电复位信号产生器具备高精度控制,尤其,产生上电复位信号时所需要的电压检测点VPOR与温度和制造工艺无关。(The invention discloses a power-on reset signal generator and a related electronic device. The power-on reset signal generator comprises a detection circuit and a comparator. The detection circuit performs a detection operation on the power supply voltage to generate a set of detection signals, and includes: a plurality of sets of transistors stacked and coupled between a power voltage and a ground voltage, wherein each set of transistors comprises a first transistor and a second transistor respectively located in a first current path and a second current path; the first resistor and the second resistor are coupled between the two groups of transistors and are respectively positioned on the first current path and the second current path; and a third resistor coupled between the power voltage and the plurality of sets of transistors. The comparator receives the set of detection signals from the detection circuit and compares the set of detection signals to generate a power-on reset signal. The benefits of the invention are for example: the power-on reset signal generator has high-precision control, and particularly, a voltage detection point VPOR required when generating the power-on reset signal is independent of temperature and manufacturing process.)

1. A power-on-reset signal generator, comprising:

a detection circuit, coupled between a power voltage and a ground voltage, for performing a detection operation on the power voltage to generate a set of detection signals, wherein the detection circuit comprises:

a plurality of sets of transistors stacked and coupled between the power voltage and the ground voltage, wherein each of the plurality of sets of transistors comprises:

a first transistor and a second transistor respectively located in a first current path and a second current path of the detection circuit; and

a first resistor and a second resistor coupled between two of the transistors in the plurality of sets of transistors and respectively located in the first current path and the second current path; and

at least one third resistor coupled between the power voltage and the plurality of sets of transistors, wherein the first current path and the second current path pass through the at least one third resistor; and

a comparator coupled to the first resistor and the second resistor for receiving the set of detection signals from the detection circuit and comparing the set of detection signals to generate a power-on reset signal.

2. The power-on reset signal generator of claim 1, wherein the first current path passes through the first resistor and the first transistor in each of the sets of transistors, and the second current path passes through the second resistor and the second transistor in each of the sets of transistors.

3. The power-on reset signal generator of claim 1, wherein each transistor of each group of transistors is configured as a two-terminal element, and two terminals of the plurality of terminals of each transistor are coupled to each other.

4. A power-on-reset signal generator as claimed in claim 3, wherein the two-terminal element represents a diode-connected transistor.

5. The power-on-reset signal generator of claim 3, wherein the plurality of terminals of each transistor includes an emitter terminal, a base terminal, and a collector terminal, and the base terminal and the collector terminal are coupled to each other.

6. The power-on reset signal generator of claim 1, wherein the two sets of transistors comprise a 1 st set of transistors and a 2 nd set of transistors, and wherein a first ratio of a particular parameter of each of the first and second transistors in the 1 st set of transistors is equal to a reciprocal of a second ratio of the particular parameter of each of the first and second transistors in the 2 nd set of transistors.

7. The power-on reset signal generator of claim 6, wherein the first ratio represents a ratio of the particular parameter of the first transistor in the 1 st set of transistors to the particular parameter of the second transistor in the 1 st set of transistors, and the second ratio represents a ratio of the particular parameter of the first transistor in the 2 nd set of transistors to the particular parameter of the second transistor in the 2 nd set of transistors.

8. The power-on-reset signal generator of claim 1, further comprising:

an output delay circuit, coupled to the comparator, for delaying the power-on reset signal to generate a delayed version of the power-on reset signal for use as another power-on reset signal, and an electronic device equipped with the power-on reset signal generator performing reset control according to the another power-on reset signal.

9. The power-on reset signal generator of claim 8, wherein the output delay circuit controls the amount of delay of the further power-on reset signal relative to the power-on reset signal to be equal to a predetermined value.

10. The power-on reset signal generator of claim 1, wherein the plurality of sets of transistors comprises N sets of transistors, and N is a positive integer greater than 1.

11. The power-on reset signal generator of claim 10, wherein the power-on reset signal generator utilizes a voltage detection point of the power voltage detected by the detection circuit as a threshold to control whether to change the logic state of the power-on reset signal, and the voltage detection point is equal to N times a bandgap voltage parameter.

12. The power-on-reset signal generator of claim 10, wherein the voltage detection point is equal to N times the bandgap voltage parameter by configuring the first resistor and the at least one third resistor.

13. The power-on-reset signal generator of claim 12, wherein configuring the first resistor and the at least one third resistor comprises controlling a resistance value of the first resistor and a resistance value of the at least one third resistor to meet a predetermined condition.

14. The power-on-reset signal generator of claim 10, wherein N equals 2.

15. The power-on-reset signal generator of claim 10, wherein N is greater than 2.

16. The power-on-reset signal generator of claim 1, wherein the comparator comprises a positive input terminal and a negative input terminal; a first terminal and a second terminal of the first resistor are coupled to the power supply voltage and the ground voltage through a plurality of local paths of the first current path, respectively, and a first terminal and a second terminal of the second resistor are coupled to the power supply voltage and the ground voltage through a plurality of local paths of the second current path, respectively; and the positive input terminal of the comparator is coupled to the first terminal of the first resistor, and the negative input terminal of the comparator is coupled to the second terminal of the second resistor.

17. An electronic device equipped with the power-on reset signal generator according to claim 1, comprising:

a processing circuit for controlling the operation of the electronic device;

a power supply circuit, coupled to the processing circuit, for providing power to the processing circuit; and

and the reset control circuit is coupled to the processing circuit and the power supply circuit and is used for carrying out reset control on the processing circuit according to the power-on reset signal, wherein the reset control circuit comprises the power-on reset signal generator.

Technical Field

The present invention relates to power-on control, and more particularly, to a power-on reset (POR) signal generator and related electronic device.

Background

When powering up an electronic system, the power supply needs a certain length of time for the voltage to stabilize and change to its steady-state value. During such a transition, the initial state of the storage elements cannot generally be defined if no reset command is provided, and therefore the circuit behavior of the entire electronic system cannot be determined either. According to the related art, a command signal for circuit initialization, such as a power-on reset signal, is generally required during or after power-on. The power-on-reset signal should keep the circuit in a reset state until the power supply reaches a steady state voltage level, such as a voltage level at which all circuits can function properly.

There are certain problems with such architectures. For example, the voltage level at a certain voltage detection point required for generating the power-on reset signal is usually affected by the temperature and the manufacturing process, especially in the advanced manufacturing process. Therefore, a novel architecture is needed to improve the overall performance without side effects or with less likelihood of side effects.

Disclosure of Invention

An objective of the present invention is to disclose a power-on reset signal generator and related electronic device to solve the above problems.

It is another object of the present invention to disclose a power-on reset signal generator and related electronic device, so as to achieve an optimal (optimal) performance of the electronic device without side effects or with less possibility of side effects.

At least one embodiment of the present invention discloses a power-on reset signal generator, wherein the power-on reset signal generator may include a detection circuit and a comparator. The detection circuit is coupled between a power voltage and a ground voltage and is used for detecting the power voltage to generate a group of detection signals, wherein the detection circuit comprises: a plurality of sets of transistors stacked and coupled between the power voltage and the ground voltage, wherein each set of transistors in the plurality of sets of transistors includes a first transistor and a second transistor, and the first transistor and the second transistor are respectively located in a first current path and a second current path of the detection circuit; and a first resistor and a second resistor coupled between two of the plurality of transistors, the first resistor and the second resistor being respectively located in the first current path and the second current path; and at least one third resistor coupled between the power voltage and the plurality of sets of transistors, wherein the first current path and the second current path pass through the at least one third resistor. In addition, the comparator is coupled to the first resistor and the second resistor. The comparator is used for receiving the group of detection signals from the detection circuit and comparing the group of detection signals to generate a power-on reset signal.

At least one embodiment of the present invention discloses an electronic device equipped with the above power-on reset signal generator, the electronic device may include: the power supply circuit is coupled to the processing circuit, and the reset control circuit is coupled to the processing circuit and the power supply circuit. The processing circuit can be used for controlling the operation of the electronic device, and the power supply circuit can be used for supplying power to the processing circuit. In addition, the reset control circuit can be used for carrying out reset control on the processing circuit according to the power-on reset signal, wherein the reset control circuit comprises the power-on reset signal generator.

The benefits of the invention are for example: the power-on reset signal generator is provided with high-precision control, and particularly, a voltage detection point VPOR required when generating a power-on reset signal is independent of temperature and manufacturing process, and the precision of the voltage detection point VPOR may correspond to that of a band-gap reference voltage. Therefore, the power-on reset signal generator and the electronic device can be properly controlled to achieve the optimal efficiency of the electronic device. In addition, the power-on reset signal generator of the present invention can be configured to utilize any one of various different magnitude predetermined voltage levels as the voltage detection point VPOR to supply voltages for various different electronic systems.

Drawings

Fig. 1 is a schematic diagram of a power-on reset signal generator according to an embodiment of the invention.

Fig. 2 shows an example of the variation of the detection signal with the supply voltage in the architecture shown in fig. 1.

Fig. 3 shows an example of a power-on reset signal in the architecture shown in fig. 1.

Fig. 4 is a schematic diagram of an electronic device according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a power-on reset signal generator according to another embodiment of the invention.

Wherein the reference numerals are as follows:

10 electronic device

11 power supply circuit

12 reset control circuit

13 processing circuit

100,200 power-on reset signal generator

110,210 detection circuit

120 comparator

121 output delay circuit

I1, I2, I3 Current

Q1, Q2, Q3, Q4, Q5, Q6, …, transistors

Q(2N-1),Q(2N)

R1, R2, R3 resistor

Stack (1), Stack (2), Stack

Stack(3),…,Stack(N)

VCCA supply voltage

GNDA ground voltage

VPOS, VNEG detection signals

POR (0), POR (1) power-on reset signal

VPOR voltage detection point

TD delay amount

Detailed Description

Fig. 1 is a schematic diagram of a power-on reset signal generator 100 according to an embodiment of the invention. The power-on reset signal generator 100 may include a detection circuit 110, a comparator (labeled "CMP") 120, and an output delay circuit 121, wherein the detection circuit 110 is coupled between a power voltage VCCA and a ground voltage GNDA, the comparator 120 is coupled to the detection circuit 110, and the output delay circuit 121 is coupled to the comparator 120, but the invention is not limited thereto. In some embodiments, the output delay circuit 121 may be disposed outside the power-on reset signal generator 100 as a next stage circuit.

According to the present embodiment, the detection circuit 110 may include a plurality of sets of transistors stacked and coupled between the power voltage VCCA and the ground voltage GNDA, such as N sets of transistors (N is a positive integer greater than 1), and each of the transistors { Q (2N-1), Q (2N) } in the plurality of sets of transistors (such as N sets of transistors) may include a first transistor Q (2N-1) and a second transistor Q (2N) respectively located in a first current path and a second current path (such as current paths of the currents I1 and I2), where N may represent a positive integer in the interval [1, N ], and N is taken as an example in the present embodiment, but the present invention is not limited thereto. As shown in fig. 1, group 1 transistors (such as { Q (2n-1), Q (2n) }, where n ═ 1) may include transistors Q1 and Q2, and group 2 transistors (such as { Q (2n-1), Q (2n) }, where n ═ 2) may include transistors Q3 and Q4. In addition, the detection circuit 110 may include resistors R1 and R2 respectively located in the first current path and the second current path and coupled between two transistors of the plurality of transistors, and more particularly, the two transistors may include transistors Q1 and Q2 of group 1 and transistors Q3 and Q4 of group 2. In addition, the detection circuit 110 may include at least one resistor (e.g., one or more resistors) coupled between the power voltage VCCA and the plurality of sets of transistors, such as the resistor R3, wherein the current I3 is equal to the sum of the currents I1 and I2, and the first current path and the second current path pass through the at least one resistor, such as the resistor R3, but the invention is not limited thereto. In some embodiments, the at least one resistor may include two resistors respectively located in the first current path and the second current path, and the resistance values of the two resistors may be equal to each other. It is noted that implementing the at least one resistor as a single resistor, such as resistor R3, may save circuit area.

As shown in fig. 1, the firstA current path (such as that of current I1) passes through resistor R1 and a first transistor Q (2n-1) (e.g., transistor Q1 or Q3) in each set of transistors { Q (2n-1), Q (2n) }, while the second current path (such as that of current I2) passes through resistor R2 and a second transistor Q (2n) (e.g., transistor Q2 or Q4) in each set of transistors { Q (2n-1), Q (2n) }. Each transistor of each of the transistors { Q (2n-1), Q (2n) } is configured as a two-terminal element, and two terminals of the plurality of terminals of each of the transistors are coupled to each other. In particular, the two-terminal element may represent a diode-connected (diode-connected) transistor. For example, each of the transistors may be an NPN transistor, the plurality of terminals may include an emitter (emitter) terminal, a base (base) terminal and a collector (collector) terminal, and the base terminal and the collector terminal are coupled to each other. Thus, the detection circuit 110 can use the voltage VBE between the base and the emitter as the basis of the reference voltage, and can use each set of transistors { Q (2n-1), Q (2n) } as a band-gap core. With N bandgap cores stacked (e.g., N ═ 2), the detection circuit 110 can obtain a reference voltage such as the voltage detection point VPOR, which is N · VBG, where VBG represents a bandgap voltage parameter (to be described later). In this embodiment, a first RATIO (1) of a specific parameter of each of the first transistor and the second transistor (e.g., the transistor Q1 or Q2) in the 1 st group of transistors is equal to an inverse of a second RATIO (2) of the specific parameter of each of the first transistor and the second transistor (e.g., the transistor Q3 or Q4) in the 2 nd group of transistors. A first RATIO (1) may represent a RATIO m:1 of the particular parameter of the first transistor (e.g., transistor Q1) in the 1 st set of transistors to the particular parameter of the second transistor (e.g., transistor Q2) in the 1 st set of transistors, and a second RATIO (2) may represent a RATIO 1: m of the particular parameter of the first transistor (e.g., transistor Q3) in the 2 nd set of transistors to the particular parameter of the second transistor (e.g., transistor Q4) in the 2 nd set of transistors, where m is not equal to 1, in particular greater than 1, while RATIO (1) is (m/1) m and RATIO (2) is (1/m) 1/m. For example, the specific parameter can represent the emitter current I_EHowever, the present invention is not limited thereto.

In addition, the comparator 120 is coupled to the resistors R1 and R2. For example, the comparator 120 includes a positive input terminal and a negative input terminal (labeled "+" and "-", respectively). A first terminal and a second terminal (such as upper terminal and lower terminal) of resistor R1 are coupled to supply voltage VCCA and ground voltage GNDA through local paths (such as upper path and lower path of resistor R1) of the first current path, respectively, and a first terminal and a second terminal (such as upper terminal and lower terminal) of resistor R2 are coupled to supply voltage VCCA and ground voltage GNDA through local paths (such as upper path and lower path of resistor R2) of the second current path, respectively. The positive input terminal of comparator 120 is coupled to the first terminal (such as an upper terminal) of resistor R1, and the negative input terminal of comparator 120 is coupled to the second terminal (such as a lower terminal) of resistor R2.

Based on the architecture shown in fig. 1, the detection circuit 110 can perform a detection operation on the power supply voltage VCCA to generate a set of detection signals VPOS and VNEG. The comparator 120 may receive the set of detection signals VPOS and VNEG from the detection circuit and compare the set of detection signals VPOS and VNEG to generate a power-on reset signal POR (0). The output delay circuit 121 may delay the power-on reset signal POR (0) to generate a delayed version of the power-on reset signal POR (0) for use as another power-on reset signal, such as the power-on reset signal POR (1). For example, the output delay circuit 121 may control a delay amount of the power-on reset signal POR (1) with respect to the power-on reset signal POR (0) to be equal to a predetermined value TD. Thus, an electronic device equipped with the power-on reset signal generator 100 can perform reset control in accordance with the power-on reset signal POR (0) (in particular, a delayed version thereof, such as the power-on reset signal POR (1)).

For ease of understanding, the parameters of certain elements (e.g., R1) in the following description may be represented by the same symbols (e.g., R1) in italics. Some implementation details of the architecture shown in FIG. 1 may be described below, in accordance with certain embodiments. At the beginning of power-up of the electronic device, the power voltage VCCA may rise from 0 volts (Volt, V) and be applied to the detection circuit 110. When the voltage level of the detection signal VPOS is equal to the voltage level of the detection signal VNEG, it indicates that the power supply voltage VCCA has been boosted to the voltage detection point VPOR. If the voltage detection point VPOR is to be obtained with high accuracy, it is necessary that the resistance values R1 and R2 of the respective resistors R1 and R2 be equal to each other (R1 ═ R2), and an appropriate resistance value R3 thereof is selected for the resistor R3 to obtain VPOR ═ 2 · VBG ≈ 2.42 (V). In the following, the equation is derived from the premise of VPOS ═ VNEG and m is assumed to be 8. The first current path is known to include resistor R1 and transistors Q1 and Q3, and the second current path includes resistor R2 and transistors Q2 and Q4; in order to pass the currents I1 and I2 through the same path, the elements in the detection circuit 110 are configured to control the resistors R1 and R2 to be equal to each other (e.g., R1 — R2), the transistors Q1 and Q4 to be equal to each other (e.g., the characteristic parameters are equal), and the transistors Q2 and Q3 to be equal to each other (e.g., the characteristic parameters are equal). Since the currents I1 and I2 pass through the same path, the currents I1 and I2 are equal to each other (I1 — I2). The correlation equation can be expressed as follows:

I1＝I2＝(ΔV_BE/R1)；

ΔV_BE＝V_BE2-V_BE1＝V_T·ln(m)＝V_T·ln(8)；

VPOR＝V_BE1+V_BE3+I1·R1+(I1+I2)·R3

＝2·V_BE+(ΔV_BEr1) · (R1+2 · R3); and

VPOR＝2·(V_BE+((R1+2·R3)/(2·R1))·ΔV_BE)；

wherein V_BE1、V_BE2And V_BE3Respectively represent the base-emitter voltages of transistors Q1, Q2, and Q3, respectively, and V_TRepresents a Thermal Voltage (Thermal Voltage), and V_BERepresents V_BE1And V_BE3Average value of (a). Thus, R1 and R3 may be selected to obtain:

(V_BE+((R1+2·R3)/(2·R1))·ΔV_BE)＝VBG，

so that

VPOR＝2·VBG；

Wherein the bandgap voltage parameter VBG may be equal to a predetermined value, such as 1.2(V), 1.21(V), 1.22(V) or a value in the vicinity thereof (such as a value in the interval [1.1,1.3 ]), but the invention is not limited thereto.

Please note that when the related parameters of the circuit 110 are detected (e.g. R1, R3, V)_BE、ΔV_BEEtc.) has been determined, the bandgap voltage parameter VBG is equal to the predetermined value and is not affected by temperature and manufacturing process. Therefore, the voltage detection point VPOR is surely independent of temperature and manufacturing process, and its accuracy can correspond to that of the bandgap reference voltage.

Fig. 2 shows an example of the detection signals VPOS and VNEG varying with the power supply voltage VCCA in the architecture shown in fig. 1, but the invention is not limited thereto. The relationship between the detection signals VPOS and VNEG may indicate whether the power supply voltage VCCA reaches the voltage detection point VPOR. For example, when the voltage levels of the detection signals VPOS and VNEG are equal to each other, the power supply voltage VCCA reaches the voltage detection point VPOR. In the present embodiment, VBG is 1.22(V), and VPOR is 2 · VBG is 2.44 (V).

Fig. 3 shows examples of the power-on reset signals POR (0) and POR (1) in the architecture shown in fig. 1, but the invention is not limited thereto. The power-on reset signal POR (0) may be regarded as a non-delayed power-on reset signal, and the power-on reset signal POR (1) may be regarded as a delayed power-on reset signal. Based on the architecture shown in fig. 1, a rising edge (rising edge) of the power-on reset signal POR (0) corresponds to a time when the power supply voltage VCCA reaches the voltage detection point VPOR.

Fig. 4 is a schematic diagram of an electronic device 10 according to an embodiment of the invention, wherein the electronic device 10 can be taken as an example of the electronic device. The electronic device 10 may include a power supply circuit 11, a reset control circuit 12 and a processing circuit 13, which are coupled to each other. For example, the reset control circuit 12 may include a power-on reset signal generator 100, while the processing circuit 13 may include a processor, a microprocessor, and/or a microcontroller, and may particularly include related circuits such as storage elements, e.g., a memory, a digital register (digital register), and an analog integrator (analog integrator), although the invention is not limited thereto. The processing circuit 13 may control the operation of the electronic device 10, and the power supply circuit 11 may provide power to the processing circuit 13, and may output at least one power voltage (one or more power voltages), including the power voltage VCCA. In addition, the reset control circuit 12 can reset-control the processing circuit 13 in accordance with the power-on reset signal POR (0) (in particular, a delayed version thereof, such as the power-on reset signal POR (1)).

According to some embodiments, the reset control circuit 12 may monitor whether the power supply voltage VCCA is higher than the lowest operating voltage of the processing circuit 13. For example, the voltage detection point VPOR may be equal to (or approximately equal to) the lowest operating voltage. After power-up of the electronic device 10, the reset control circuit 12 may control the processing circuit 13 to enter a reset state, so that initialization of relevant circuits such as storage elements (e.g., digital registers and analog integrators) is completed to determine the initial state of the storage elements.

According to some embodiments, after the electronic device 10 is powered on, the reset control circuit 12 may utilize the power-on reset signal POR (0) and/or POR (1) to maintain the processing circuit 13 in the reset state until the power supply voltage VCCA exceeds a power-on reset threshold, such as the voltage detection point VPOR, and a certain delay time elapses.

Fig. 5 is a schematic diagram of a power-on reset signal generator 200 according to another embodiment of the invention. Compared to the structure shown in fig. 1, the detection circuit 110 is replaced with the detection circuit 210. In the case of N >2, the 1 st set of transistors (such as { Q (2N-1), Q (2N) }, where N ═ 1) may include transistors Q1 and Q2 and may be referred to as Stack (1), the 2 nd set of transistors (such as { Q (2N-1), Q (2N) }, where N ═ 2) may include transistors Q3 and Q4 and may be referred to as Stack (2), the 3 rd set of transistors (such as { Q (2N-1), Q (2N) }, where N ═ 3) may include transistors Q5 and Q6 and may be referred to as Stack (3), and so on. Similarly, an nth set of transistors, such as { Q (2N-1), Q (2N) }, where N ═ N may include transistors Q (2N-1) and Q (2N), and may be referred to as a stack (N). Additionally, a third RATIO (3) of the particular parameter of each of the first transistor and the second transistor in the set 3 (e.g., transistor Q5 or Q6) is equal to 1, wherein the third RATIO (3) may represent a RATIO of 1:1 of the particular parameter of the first transistor in the set 3 (e.g., transistor Q5) to the particular parameter of the second transistor in the set 3 (e.g., transistor Q6); and so on. Similarly, the nth ratio (N) of the specific parameter of each of the first transistor and the second transistor in the nth set of transistors (e.g., transistors Q (2N-1) and Q (2N)) is equal to 1, wherein the nth ratio (N) may represent a ratio of 1:1 of the specific parameter of the first transistor in the nth set of transistors (e.g., transistor Q (2N-1)) to the specific parameter of the second transistor in the 3 rd set of transistors (e.g., transistor Q (2N)).

Whichever embodiment is shown in fig. 1 and 5, VPOR — N · VBG always holds. For example, the power-on reset signal generator 100 may utilize a voltage detection point VPOR of the detection circuit 110 for the power supply voltage VCCA as a threshold to control whether to change the logic state of the power-on reset signal POR (0), where VPOR ═ N · VBG and N ═ 2. For another example, the power-on reset signal generator 200 may utilize a voltage detection point VPOR of the power supply voltage VCCA by the detection circuit 210 as a threshold to control whether to change the logic state of the power-on reset signal POR (0), where VPOR is N · VBG, and N is>2. In addition, by arranging the resistor R1 with the above-described at least one resistor such as R3, the voltage detection point VPOR is equal to N times the bandgap voltage parameter VBG (VPOR — N · VBG). Configuring the resistor R1 and the at least one resistor such as R3 may include controlling resistance values of the resistors (e.g., resistance values R1 and R3) to meet a predetermined condition (e.g., (VBE + ((R1+ 2. R3)/(2. R1)). DELTA.V)_BE)＝VBG)。

The present invention discloses high precision power-on-reset signal generators (such as 100 and 200) whose voltage detection point VPOR is independent of temperature and manufacturing process, and the precision of the voltage detection point VPOR may correspond to that of the bandgap reference voltage. In particular, the high-precision power-on reset signal generator may be applied to power management of various circuits (e.g., System-on-Chip (SOC), Micro Control Unit (MCU), Intellectual property module (IP module), etc.). For example, in the case where the bandgap voltage parameter VBG is 1.2(V), the above-described high-precision power-on reset signal generator can provide the power-on reset signal POR (such as POR (1) and POR (2)) corresponding to the voltage detection points VPOR such as 2.4V, 3.6V, 4.8V, …, and the like, by configuring the detection circuits to N2, N3, N4, …, and the like, respectively. Compared with the related art, the invention has wider application range, and the voltage detection point VPOR is not influenced by temperature and a manufacturing process.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention, and various modifications and changes may be made by those skilled in the art. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.