阅读说明：本技术 用于混合激光划刻和等离子体蚀刻晶片切割工艺的光吸收掩模 (Light absorbing mask for hybrid laser scribing and plasma etch wafer dicing process ) 是由 李文广 詹姆斯·S·帕帕努 雷伟圣 普拉巴特·库马尔 布拉德·伊顿 阿杰伊·库马尔 亚历 于 2018-05-11 设计创作，主要内容包括：描述了光吸收掩模和对半导体晶片进行切片的方法。在一示例中,一种对包括多个集成电路的半导体晶片进行切片的方法包含在所述半导体晶片上方形成掩模。所述掩模包括基于固体组分和水的水溶性基质、以及遍布所述水溶性基质中的光吸收剂物种。用激光刻划工艺来将所述掩模、以及所述半导体晶片的一部分图案化以提供在所述集成电路之间的区域中具有间隙的图案化掩模以及在所述半导体晶片中在所述集成电路之间的区域中提供对应的沟槽。穿过所述图案化掩模中的所述间隙对所述半导体晶片进行等离子体蚀刻以延伸所述沟槽并切割所述集成电路。所述图案化掩模在所述等离子体蚀刻期间保护所述集成电路。(A light absorbing mask and method of dicing a semiconductor wafer are described. In an example, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a mask over the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light absorber species distributed throughout the water-soluble matrix. The mask, and a portion of the semiconductor wafer, are patterned with a laser scribing process to provide a patterned mask having gaps in regions between the integrated circuits and to provide corresponding trenches in the semiconductor wafer in regions between the integrated circuits. Plasma etching the semiconductor wafer through the gaps in the patterned mask to extend the trenches and cut the integrated circuits. The patterned mask protects the integrated circuit during the plasma etch.)

1. A method of dicing a semiconductor wafer comprising a plurality of integrated circuits, the method comprising:

forming a mask over the semiconductor wafer, the mask comprising a water-soluble matrix based on a solid component and water, and the mask comprising a light absorber species throughout the water-soluble matrix;

patterning the mask, and a portion of the semiconductor wafer, with a laser scribing process to provide a patterned mask having gaps in regions between the integrated circuits and to provide corresponding trenches in the semiconductor wafer in the regions between the integrated circuits; and

plasma etching the semiconductor wafer through the gaps in the patterned mask to extend the trenches and cut the integrated circuits, wherein the patterned mask protects the integrated circuits during the plasma etching.

2. The method of claim 1, wherein patterning the mask with a laser scribing process comprises patterning with a gaussian beam, wherein during the patterning, the light absorber species of the mask substantially confines a trailing portion of the gaussian beam to the mask, and wherein during the patterning, a leading portion of the gaussian beam is substantially confined to the semiconductor wafer.

3. The method of claim 1, wherein the light absorber species is a water-soluble dye dissolved in the water-soluble matrix.

4. The method of claim 1, wherein the light absorber species is a nanodispersion of a pigment throughout the water soluble matrix.

5. The method of claim 1, wherein the mask further comprises a plurality of particles dispersed throughout the water-soluble matrix, wherein a ratio of the weight% of the solid component to the weight% of the plurality of particles is approximately in the range of 1:0.1-1: 4.

6. The method of claim 5, wherein the plurality of particles have an average diameter approximately in the range of 5-100 nanometers.

7. The method of claim 6, wherein the plurality of particles of the mask do not substantially interfere with a laser scribing process during patterning of the mask with the laser scribing process.

8. The method of claim 5, wherein plasma etching the semiconductor wafer comprises plasma etching a single crystal silicon wafer, and wherein a ratio of an etch rate of the single crystal silicon wafer to an etch rate of the mask during the plasma etching is approximately in the range of 15:1-170: 1.

9. The method of claim 1, wherein forming the mask over the semiconductor wafer comprises spin coating the mask on the semiconductor wafer.

10. The method of claim 1, further comprising:

after plasma etching the semiconductor wafer, the patterned mask is removed using an aqueous solution.

11. The method of claim 1, further comprising:

cleaning the trenches in the semiconductor wafer with a plasma cleaning process after patterning the mask and before plasma etching the semiconductor wafer through the gaps in the patterned mask to cut the integrated circuits.

12. A mask for a wafer dicing process, the mask comprising:

a water-soluble matrix based on a solid component and water;

a light absorber species distributed throughout the water-soluble matrix; and

a plurality of particles dispersed throughout the water-soluble matrix, the plurality of particles being different from the light absorber species.

13. The mask of claim 12, wherein the light absorber species is selected from the group consisting of: a water-soluble dye dissolved in the water-soluble matrix and a nanodispersion of a pigment dispersed throughout the water-soluble matrix.

14. The mask of claim 12, wherein the plurality of particles have an average diameter approximately in the range of 5-100 nanometers.

15. The mask of claim 12, wherein a ratio of the weight% of the solid component to the weight% of the plurality of particles is approximately in the range of 1:0.1-1: 4.

Technical Field

Embodiments of the invention relate to the field of semiconductor processing, and in particular to methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon.

Background

In semiconductor wafer processing, integrated circuits are formed on a wafer (also referred to as a substrate) composed of silicon or other semiconductor material. Generally, integrated circuits are formed using layers of various materials that are semiconducting, conducting, or insulating. These materials are doped, deposited, and etched using various well-known processes to form integrated circuits. Each wafer is processed to form a large number of individual areas containing integrated circuits called dies.

After the integrated circuit formation process, the wafer is "diced" to separate the individual dies from each other for packaging or for use within larger circuits in an unpackaged form. The two main techniques used for wafer dicing are scribing and sawing. During scribing, a tip-mounted diamond scribe machine is moved over the wafer surface along preformed scribe lines. The scribe lines extend along the spaces between the dies. These spaces are commonly referred to as "streets". A diamond scribe creates shallow scratches in the wafer surface along scribe lanes. Upon application of pressure, such as with a roller, the wafer is separated along the scribe lines. The fractures in the wafer follow the lattice structure of the wafer substrate. Scribing can be used for wafers having a thickness of about 10 mils (thousandths of an inch) or less. For thicker wafers, sawing is currently the preferred method of slicing.

During sawing, a diamond tipped saw rotating at high revolutions per minute contacts the wafer surface and saws the wafer along a saw street. The wafer is mounted on a support member (such as an adhesive film stretched across a film frame) and a saw is repeatedly applied to both the vertical and horizontal streets. One problem with scribing or sawing is that chips and gouges may form along the cut edge of the die. Additionally, cracks may form and propagate from the edges of the die into the substrate and render the integrated circuit inoperable. Scribing causes problems of chipping and cracking in particular, since only one side of a square or rectangular die can be scribed in the <1l0> direction of the crystal structure. Thus, dicing the other side of the die creates a jagged parting line. Due to chipping and cracking, additional spacing between the dies on the wafer is required to prevent damage to the integrated circuits, e.g., to maintain debris and cracks at a distance from the actual integrated circuits. Due to the pitch requirements, not as many dies can be formed on a standard size wafer and the wafer space that would otherwise be available for circuitry is wasted. The use of saws exacerbates the waste of space on the semiconductor wafer. The blade of the saw is approximately 15 microns thick. Thus, to ensure that cracking and other damage around the cuts made by the saw does not damage the integrated circuit, the circuits of each die must typically be separated by three to five hundred microns. Furthermore, after dicing, each die requires extensive cleaning to remove particles and other contaminants generated in the sawing process.

Plasma dicing has also been used, but there may be limitations. For example, one limitation that prevents plasma dicing from being implemented may be cost. Standard lithographic operations for patterning the resist can be cost prohibitive to implement. Another limitation that may prevent plasma dicing from being performed is that plasma etching of metals (e.g., copper) commonly encountered when dicing along streets may create production problems or yield limitations.

Disclosure of Invention

Embodiments of the invention include methods and apparatus for dicing semiconductor wafers.

In an embodiment, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a mask over the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light absorber species distributed throughout the water-soluble matrix. Patterning the mask, and a portion of the semiconductor wafer, with a laser scribing process to provide a patterned mask having gaps in regions between the integrated circuits and to provide corresponding trenches in the semiconductor wafer in the regions between the integrated circuits. Plasma etching the semiconductor wafer through the gaps in the patterned mask to extend the trenches and cut the integrated circuits. The patterned mask protects the integrated circuit during the plasma etch.

In another embodiment, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a mask over the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light absorber species distributed throughout the water-soluble matrix. Patterning the mask and dicing the integrated circuits of the semiconductor wafer with a laser scribing process.

In another embodiment, a mask for a wafer dicing process includes a water soluble matrix based on a solid component and water. A light absorber species is dispersed throughout the water-soluble matrix. A plurality of particles are dispersed throughout the water soluble matrix. The plurality of particles is different from the light absorber species.

Drawings

Fig. 1 is a flow chart representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits according to an embodiment of the present invention.

Fig. 2A illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performance of a method of dicing the semiconductor wafer, according to an embodiment of the invention, which corresponds to operation 102 of the flowchart of fig. 1.

Fig. 2B illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performance of a method of dicing the semiconductor wafer, in accordance with an embodiment of the invention, which corresponds to operation 104 of the flowchart of fig. 1.

Fig. 2C illustrates a cross-sectional view of a semiconductor wafer including a plurality of integrated circuits during performance of a method of dicing the semiconductor wafer, according to an embodiment of the invention, which corresponds to operation 106 of the flowchart of fig. 1.

Fig. 3A shows Scanning Electron Microscope (SEM) images of 0%, 0.25%, and 0.5% dye concentration taken from a trench profile perspective after laser scribing but before mask removal according to an embodiment of the present invention.

Fig. 3B shows Scanning Electron Microscope (SEM) and optical microscope images of the trench surface after laser scribe mask removal for dye concentrations of 0%, 0.25%, and 0.5%, according to an embodiment of the present invention.

Fig. 4 shows a cross-sectional view of a material stack that may be used in a scribe lane region of a semiconductor wafer or substrate according to an embodiment of the present invention.

Fig. 5A-5D illustrate cross-sectional views of various operations in a method of dicing a semiconductor wafer, according to an embodiment of the invention.

FIG. 6 shows a block diagram of a tool layout for laser and plasma dicing a wafer or substrate according to an embodiment of the invention.

FIG. 7 shows a block diagram of an exemplary computer system, according to an embodiment of the invention.

Detailed Description

Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits thereon, are described. In the following description, numerous specific details are set forth, such as light-absorbing mask materials and processes, laser scribing conditions, and plasma etching conditions and material regimes, in order to provide a thorough understanding of embodiments of the present invention. It will be apparent to one skilled in the art that embodiments of the present invention may be practiced without these specific details. In other instances, well-known aspects of integrated circuit fabrication have not been described in detail so as not to unnecessarily obscure embodiments of the present invention. Further, it will be understood that the various embodiments shown in the figures are illustrative representations and are not necessarily drawn to scale.

One or more embodiments are particularly directed to the use of light absorbers to reduce laser damage in etch masks. Embodiments may be applicable to laser and etch wafer dicing methods and tools for cutting or dicing electronic device wafers. To provide context, during dicing of the wafer into individual dies, the wafer is cut or diced along dicing streets between the dies. Traditionally, slicing is performed using a mechanical saw. Mobile devices and other technical drives may require more advanced cutting methods to reduce cracking, delamination, and chipping defects. Laser and etch wafer dicing methods may include applying a water-soluble protective coating to a substrate, removing any device test layer in the scribe lane areas of the coating removed by laser scribing to expose the underlying substrate material, which is typically silicon (Si). The plasma then etches through the entire thickness of the exposed silicon to dice the wafer into individual dies. The protective coating is removed in a Deionized (DI) water based cleaning operation. Water-soluble protective coatings may be desirable for environmental considerations and for ease of handling. Such a water-soluble coating may be used primarily as an etch mask during the plasma etching step, and may also be used as a layer to collect any debris generated during laser scribing. To provide further context, a femtosecond laser may be preferred in the laser scribing portion of the process. Unlike nanosecond and other long pulse lasers, femtosecond lasers have little thermal effect due to the associated ultrashort pulses. Another advantage of femtosecond lasers may be the ability to remove most materials, including absorptive, reflective, and transparent materials. On a typical wafer, there are reflective and absorptive metals, transparent dielectrics, and silicon substrates that are absorptive to most lasers. The water-soluble protective coating is completely or mostly transparent. These listed materials can be ablated with a femtosecond laser.

A typical femtosecond laser has a so-called "gaussian beam" with high intensity near the center of the beam and low intensity towards the edges of the beam. A gaussian beam can be a problem when a femtosecond laser is used to process a wafer having a transparent layer on an absorbing substrate, e.g., a transparent protective coating (e.g., a water-soluble mask) on silicon or on a dielectric layer on silicon. To remove the transparent layer, the laser process requires a suitably high intensity (e.g., the leading portion of the gaussian beam) to produce nonlinear absorption. However, since the low-intensity portion (trailing edge) of the gaussian beam does not have sufficient intensity to produce non-linear absorption, the low-intensity portion of the gaussian beam passes through the transparent layer with little attenuation. However, the low intensity portion of the gaussian beam is absorbed by the silicon. This condition may lead to heating of the transparent layer/silicon interface, which may lead to delamination between the transparent layer and the silicon and to cracking or even breaking of both the transparent layer and the silicon. Thus, a gaussian beam typically produces a laser damage region that is much wider than the intended scribe region. However, in another embodiment, the laser is not a gaussian beam, but a non-gaussian beam having a high intensity portion and a low intensity portion. According to one or more embodiments of the present invention, light absorbers are used in protective coatings, such as in water-soluble masks, to prevent low intensity portions of the gaussian beam from reaching the transparent layer/silicon interface. In one such embodiment, the laser damage region is significantly reduced or completely removed. In an embodiment, the inclusion of a light absorber species in the otherwise transparent mask material enables a scribing process to be performed in which the trailing edge of the gaussian beam is held or confined within the mask during laser scribing, while only the leading portion of the gaussian beam is allowed to penetrate into the substrate.

It should be understood that although many of the embodiments described below are associated with femtosecond laser scribing, in other embodiments, laser scribing using other laser beam types may also be compatible with the mask materials described herein. It should also be understood that while many of the embodiments described below are associated with scribes having metallization features, in other embodiments, metal-free scribes are also contemplated. Accordingly, in one aspect of the present invention, a light absorbing mask is used in a dicing process based on a combination of a laser scribing process and a plasma etching process to dice a semiconductor wafer into individual integrated circuits. Fig. 1 is a flow chart 100 representing operations in a method of dicing a semiconductor wafer including a plurality of integrated circuits, in accordance with an embodiment of the present invention. Fig. 2A-2C illustrate cross-sectional views of a semiconductor wafer including a plurality of integrated circuits during performance of a method of dicing the semiconductor wafer, which correspond to the operations of flowchart 100, in accordance with an embodiment of the invention. Referring to operation 102 of flowchart 100, and corresponding FIG. 2A, a mask 202 is formed over a semiconductor wafer or substrate 204. Mask 202 covers and protects integrated circuits 206 formed on the surface of semiconductor wafer 204. The mask 202 also covers the intervening streets 207 formed between each of the integrated circuits 206. In one embodiment, mask 202 includes a water-soluble matrix based on a solid component and water, and a light absorber species dispersed throughout the water-soluble matrix.

In one embodiment, the water soluble matrix is a polyvinyl alcohol (PVA) -based water soluble matrix, wherein the PVA is a solid component. In another embodiment, the solid component for the water-soluble matrix is selected from the group consisting of polyethylene oxide, polyethylene glycol, polyacrylic acid, polyacrylamide, polystyrene-maleic acid copolymer, hydroxyethyl cellulose, and hydroxyethyl starch. In one embodiment, the water-soluble matrix comprises about 10% to 40% by weight of the solid component, with the remainder being water. In one embodiment, forming the mask 202 over the semiconductor wafer 204 includes spin coating the mask 202 on the semiconductor wafer 204. In a particular embodiment, prior to coating, a plasma or chemical pre-treatment is performed to enable better wetting and coating of the wafer.

In one embodiment, mask 202 is a water-soluble mask because it readily dissolves in aqueous media. For example, in one embodiment, the deposited water soluble mask 202 is composed of a material that is soluble in one or more of an alkaline solution, an acidic solution, or deionized water. In a particular embodiment, the etch or removal rate of the deposited water soluble mask 202 in an aqueous solution is approximately in the range of 1-15 microns per minute, and more particularly approximately 1.3 microns per minute.

In one embodiment, the light absorber species in the water-soluble matrix throughout the mask 202 is a species such as, but not limited to, the following: a water-soluble dye dissolved in a water-soluble matrix, a nanodispersion of a pigment throughout the water-soluble matrix, or a combination of a water-soluble dye dissolved in a water-soluble matrix and a nanodispersion of a pigment throughout the water-soluble matrix.

In one embodiment, for a 530nm green laser, the light absorber species is selected from the group consisting of: rhodamine B, rhodamine G and D&C red 27. In one embodiment, for a green laser at 530 nanometers, the light absorber species is selected from the group of: dyes or pigments which absorb light at 530nm, examples of dyes being rhodamine B, rhodamine G, betanin and D&C red 27. It will be appreciated that water-soluble dyes may be a preferred light absorber because relatively large pigment dispersions can scatter light and have a negative impact on wafer alignment. However, in one embodiment, a nano-dispersion of the pigment (a dispersion of pigment particles having a nano-scale size) is used and exhibits relatively low light scattering. In one embodiment, the dispersion of pigment particles consists of carbon black, iron oxide or gold colloids. In one embodiment, CeO₂Dispersion of the particlesThe body serves as a UV absorbing species.

On the other hand, typical water-soluble polymers do not have high resistance to plasma etching, whereas polymers with good etch resistance are generally insoluble in water. Etch selectivity may be defined as the ratio of the amount of substrate material (e.g., Si) removed during an etch process to the amount of mask loss. Water-soluble polymers generally have relatively low selectivity, and it may be advantageous to enhance the selectivity of the mask without sacrificing water solubility.

According to an embodiment of the present invention, there are additional particles in the light absorbing water soluble mask that are provided with etch selectivity for laser scribing and plasma etching wafer dicing. Embodiments may address the potential need for improved etch resistance in water-soluble dicing masks. In a particular example, a polyvinyl alcohol (PVA) matrix having silica particles dispersed therein is provided as an etch mask. More generally, in one embodiment, the particle dispersion is mixed with a water-soluble polymer to form a composite mask. Water-insoluble materials, such as oxides and polymers, can be mixed as a dispersion into the water-soluble polymer mixture. Suitable particle dispersions may be colloidal dispersions of inorganic particles and polymers. Suitable inorganic particles may include oxides such as silica, alumina, titania, and ceria, as well as other particles such as calcium carbonate, barium sulfate, and the like. Suitable polymer particles may include polystyrene and PTFE. It should be understood that a mask typically requires low haze because the mask is laser scribed. To minimize haze, in an embodiment, particles smaller than 100 nanometers may be included in the matrix.

Thus, in an embodiment, a plurality of particles are dispersed throughout the water soluble matrix of the mask comprising the light absorber species. The plurality of particles is different from the light absorber species. In one embodiment, the plurality of particles have an average diameter approximately in the range of 5 nanometers to 100 nanometers. In one embodiment, the ratio of the weight percent of the solid component of the water-soluble matrix to the weight percent of the plurality of particles is approximately in the range of 1:0.1 to 1: 4. In one implementationIn this manner, the plurality of particles have an average diameter approximately in the range of 5 nanometers to 100 nanometers, and the ratio of the weight percent of the solid component of the water-soluble matrix to the weight percent of the plurality of particles is approximately in the range of 1:0.1 to 1: 4. In one embodiment, the plurality of particles have an average diameter approximately in the range of 5 nanometers to 50 nanometers. It should be understood that a smaller diameter may be preferred in order to reduce or eliminate any potential laser light scattering or haze. In one embodiment, the ratio of the weight% of the solid component to the weight% of the plurality of particles is approximately in the range of 1:0.5 to 1: 2. In one embodiment, the plurality of particles is a plurality of particles selected from the group consisting of: silicon dioxide (SiO)₂) Particles, alumina (Al)₂O₃) Particles, alumina coated silicon particles, Polytetrafluoroethylene (PTFE) particles, and combinations thereof. It is understood that other oxides (such as titanium oxide, cerium oxide, zinc oxide, indium tin oxide, zirconium oxide) and other inorganic particles (such as calcium carbonate, barium sulfate, etc.) may also be used as particle additives. Suitable polymer particles also include polystyrene, epoxy resins, and the like. In one embodiment, the plurality of particles is a plurality of absorbent species.

In one embodiment, the semiconductor wafer or substrate 204 is comprised of a material suitable to withstand the fabrication process and upon which the semiconductor handle layer may be suitably disposed. For example, in one embodiment, semiconductor wafer or substrate 204 is composed of a group IV based material, such as, but not limited to, crystalline silicon, germanium, or silicon/germanium. In a particular embodiment, providing the semiconductor wafer 204 includes providing a monocrystalline silicon substrate. In a particular embodiment, the monocrystalline silicon substrate is doped with impurity atoms. In another embodiment, the semiconductor wafer or substrate 204 is composed of a group III-V material, such as, for example, a group III-V material substrate used to fabricate Light Emitting Diodes (LEDs).

In one embodiment, the semiconductor wafer or substrate 204 has an array of semiconductor devices disposed thereon or therein as part of an integrated circuit 206. Examples of such semiconductor devices include, but are not limited to, memory devices or Complementary Metal Oxide Semiconductor (CMOS) transistors fabricated in a silicon substrate and encapsulated in a dielectric layer. A plurality of metal interconnects may be formed over the devices or transistors and in the surrounding dielectric layer, and may be used to electrically couple the devices or transistors to form the integrated circuit 206. The material from which the scribe lane 207 is made may be similar to or the same as the material used to form the integrated circuit 206. For example, the scribe lane 207 may be comprised of a layer of dielectric material, a layer of semiconductor material, and a metallization layer. In one embodiment, one or more of the streets 207 includes test devices similar to the actual devices of the integrated circuit 206.

In an optional embodiment, mask 202 is baked prior to laser patterning of the mask. In one embodiment, the mask 202 is baked to increase the etch resistance of the mask 202. In a particular embodiment, the mask 202 is baked at a higher temperature approximately in the range of 50 degrees Celsius to 130 degrees Celsius. Such higher temperature baking may cause cross-linking of the mask 202 to significantly increase etch resistance. For example, when the mask 202 mask is baked at 130 degrees celsius or around 130 degrees celsius for about 3 minutes, the resulting enhanced light absorption and etch resistant mask is robust with respect to silicon etch processes. In one embodiment, the baking is performed using a hot plate technique or thermal (light) radiation applied from the front side of the wafer (e.g., a non-tape mounting surface in the case of a substrate carrier) or other suitable technique.

Referring to operation 104 of flowchart 100, and corresponding FIG. 2B, mask 202 is patterned with a laser scribing process to provide a patterned mask 208 having gaps 210, thereby exposing regions of semiconductor wafer or substrate 204 between integrated circuits 206. Thus, a laser scribing process is used to remove the material of the streets 207 originally formed between the integrated circuits 206. In accordance with an embodiment of the present invention, patterning the mask 202 with a laser scribing process further comprises forming trenches 212 partially in regions of the semiconductor wafer 204 between the integrated circuits 206, as also shown in fig. 2B.

In one embodiment, mask 202 is patterned with a gaussian laser beam. During patterning, the light absorber species of the mask substantially confine the trailing edge of the gaussian beam to the mask 202. During patterning, the leading portion of the gaussian beam is substantially confined to the semiconductor wafer or substrate 204. In an embodiment, where the mask 202 further includes a plurality of particles for increasing etch resistance, the plurality of particles of the mask 202 do not substantially interfere with the laser scribing process during the patterning of the mask 202 with the laser scribing process.

In one embodiment, a femtosecond-based laser is used as the source of the laser scribing process. For example, in one embodiment, a laser having a wavelength in the visible spectrum plus the Ultraviolet (UV) and Infrared (IR) ranges (combined as a broadband spectrum) is used to provide a femtosecond-based laser, i.e., having femtoseconds (10)^-15Seconds) of pulse width. In one embodiment, ablation is wavelength independent, or substantially wavelength independent, and is therefore suitable for composite films, such as films of the mask 202, scribe 207, and possibly a portion of the semiconductor wafer or substrate 204.

To determine the effect of light absorbers on the laser scribing process, for example, as relative amounts of light absorbers, liquid coatings with and without light absorber species were prepared and then tested in a scribing environment. Fig. 3A shows Scanning Electron Microscope (SEM) images taken from a trench profile perspective after laser scribing but before mask removal for dye concentrations of 0%, 0.25%, and 0.5%, according to an embodiment of the invention. Fig. 3B shows Scanning Electron Microscope (SEM) and optical microscope images of the trench surface after laser scribe mask removal for dye concentrations of 0%, 0.25%, and 0.5%, according to an embodiment of the present invention.

Referring to fig. 3A and 3B, transparent water-soluble mask samples were prepared to include no light absorber, to include 0.25 wt% of the light absorber, and to include 0.5 wt% of the light absorber. The light absorber used was D & C red 27. A water-soluble mask material is coated on a bare silicon (Si) wafer with the coating material. The coating is baked to dryness. A laser scribing process is used to open the mask material. A plasma etch is performed to achieve a desired trench etch depth in the Si. The wafer was cleaved/split into samples to obtain SEM images and a measurement of the width of the laser affected zone. As shown in fig. 3A and 3B, a 0.5% D & C red 27 significantly reduces the width of the laser damage region. It should be appreciated that by using a laser beam profile with a composition in the femtosecond range (coherence), thermal damage issues are reduced or eliminated in comparison to longer pulse widths (e.g., nanosecond processing). The elimination or reduction of damage during laser scribing may be due to the lack of low energy recoupling or thermal balancing. It should also be appreciated that laser parameter selection, such as beam profile, may be critical to developing a successful laser scribing and cutting process that minimizes chipping, micro-cracking, and delamination in order to achieve a clean laser scribing cut. The cleaner the laser scribe cuts, the smoother the etching process can be performed for the final die cut. In a semiconductor device wafer, functional layers of many different material types (e.g., conductor, insulator, semiconductor) and thicknesses are typically provided thereon. Such materials may include, but are not limited to, organic materials (such as polymers, metals) or inorganic dielectrics (such as silicon dioxide and silicon nitride).

Streets between individual integrated circuits disposed on a wafer or substrate may include similar or identical layers to the integrated circuits themselves. For example, fig. 4 illustrates a cross-sectional view of a material stack that may be used in a scribe lane region of a semiconductor wafer or substrate according to an embodiment of the present invention. Referring to fig. 4, scribe lane area 400 includes a top portion 402 of a silicon substrate, a first silicon dioxide layer 404, a first etch stop layer 406, a first low K dielectric layer 408 (e.g., having a dielectric constant of 4.0 less than silicon dioxide), a second etch stop layer 410, a second low K dielectric layer 412, a third etch stop layer 414, an undoped silicon dioxide glass (USG) layer 416, a second silicon dioxide layer 418, and a scribe and/or etch mask 420 (such as the masks described above in connection with mask 202). Copper metallization 422 is disposed between the first etch stop layer 406 and the third etch stop layer 414 and through the second etch stop layer 410. In a specific embodiment, the first etch stop layer 406, the second etch stop layer 410, and the third etch stop layer 414 are comprised of silicon nitride, while the low-K dielectric layers 408 and 412 are comprised of carbon-doped silicon oxide material.

Under conventional laser irradiation (e.g., nanosecond-based irradiation), the material of the scribe 400 exhibits a large difference in light absorption and ablation mechanisms. For example, under normal conditions, a dielectric layer such as silicon dioxide is substantially transparent to all commercially available laser wavelengths. In contrast, metals, organics (e.g., low-K materials), and silicon can couple photons very easily, particularly in response to nanosecond-based irradiation. In an embodiment, a femtosecond-based laser scribing process is used to pattern the silicon dioxide layer, the low K material layer, and the copper layer by ablating the silicon dioxide layer prior to ablating the low K material layer and the copper layer.

Where the laser beam is femtosecond-based, in one embodiment, a suitable femtosecond-based laser process is characterized by a high peak intensity (irradiance), which typically causes nonlinear interactions in various materials. In one such embodiment, the femtosecond laser source has a pulse width approximately in the range of 10 to 500 femtoseconds, but preferably in the range of 100 to 400 femtoseconds. In one embodiment, the femtosecond laser source has a wavelength approximately in the range of 1570 to 200 nanometers, but preferably in the range of 540 to 250 nanometers. In one embodiment, the laser and corresponding optical system provide a focal point at the working surface approximately in the range of 3 to 15 microns, but preferably approximately in the range of 5 to 10 microns or between 10-15 microns.

In one embodiment, the laser source has a pulse repetition rate approximately in the range of 200kHz to 10MHz, but preferably approximately in the range of 500kHz to 5 MHz. In one embodiment, the laser source delivers a pulse energy at the working surface approximately in the range of 0.5uJ to 100uJ, but preferably approximately in the range of luJ to 5 uJ. In one embodiment, the laser scribing process is run at a speed in the range of approximately 500mm/sec to 5m/sec along the surface of the workpiece, but preferably in the range of approximately 600mm/sec to 2 m/sec.

The scribing process may be performed in only a single pass, or may be performed in multiple passes, however, in one embodiment, preferably 1-2 passes are performed. In one embodiment, the scribe depth in the workpiece is in the range of about 5 to 50 microns deep, preferably about 10 to 20 microns deep. In one embodiment, the kerf width of the generated laser beam is approximately in the range of 2 microns to 15 microns, but preferably approximately in the range of 6 microns to 10 microns in silicon wafer scribing/dicing, as measured at the device/silicon interface.

Laser parameters may be selected that have benefits and advantages, such as providing a sufficiently high laser intensity to achieve ionization of the inorganic dielectric (e.g., silicon dioxide) and minimize delamination and fracture caused by underlying damage prior to direct ablation of the inorganic dielectric. Moreover, the parameters can be selected to provide meaningful process throughput for industrial applications with precisely controlled ablation width (e.g., kerf width) and depth.

It should be appreciated that after the above-described laser scribing, the dicing or cutting process may be stopped where the laser scribing is used to pattern and completely scribe the mask through the wafer or substrate in order to cut the die. In accordance with such an approach, in one embodiment, a method of dicing a semiconductor wafer including a plurality of integrated circuits includes forming a mask over the semiconductor wafer. The mask includes a water-soluble matrix based on a solid component and water, and a light absorber species dispersed throughout the water-soluble matrix. A laser scribing process is used to pattern the mask and to dice the integrated circuits of the semiconductor wafer. In this particular embodiment, a gaussian beam is used to pattern the mask. The light absorber species of the mask substantially confines the trailing edge portion of the gaussian beam to the mask during patterning. During patterning, the leading portion of the gaussian beam is substantially confined to the semiconductor wafer. Laser scribing completes the cut. Thus, in an embodiment, no additional dicing process, such as plasma etching, is required to achieve dicing. However, in the case where only laser scribing is not performed to perform complete cutting, the following embodiments may be considered.

In an optional embodiment, a post reticle opening clean operation is performed after the laser scribing process and before the plasma etch dicing process. In one embodiment, the post mask opening cleaning operation is a plasma-based cleaning process. In an example, as described below, the plasma-based cleaning process is non-reactive to the trenches 212 of the substrate 204 exposed by the gap 210.

According to one embodiment, the plasma-based cleaning process is non-reactive to the exposed areas of the substrate 204 because the exposed areas are not etched or are only negligibly etched during the cleaning process. In one such embodiment, only a non-reactive gas plasma clean is used. For example, a highly biased plasma treatment using Ar or another non-reactive gas (or mixture thereof) is performed to perform mask condensation and scribe opening cleaning. The method may be adapted to a water-soluble mask, such as mask 202. In another such embodiment, separate mask condensation (densifying the surface layer) and scribe trench cleaning operations are used, e.g., first performing a highly biased plasma treatment of Ar or non-reactive gas (or mixture thereof) for mask condensation, and then Ar + SF on the laser scribed trenches₆And (4) plasma cleaning. This embodiment may be suitable for situations where the Ar cleaning is insufficient for trench cleaning due to too thick mask material. Referring to operation 106 of flowchart 100, and corresponding FIG. 2C, semiconductor wafer 204 is etched through gaps 210 in patterned mask 208 to dice integrated circuits 206. In accordance with an embodiment of the present invention, etching semiconductor wafer 204 includes finally etching completely through semiconductor wafer 204 by etching trenches 212 initially formed by a laser scribing process, as shown in fig. 2C. The patterned mask 208 protects the integrated circuit during plasma etching. According to an embodiment of the present invention, plasma etching the semiconductor wafer through the gap includes plasma etching a single crystal silicon wafer. In one such embodiment, the ratio of the etch rate of the single crystal silicon wafer to the etch rate of the mask 202 during plasma etching is approximately in the range of 15:1-170: 1.

In an embodiment, patterning the mask 202 with a laser scribing process includes forming trenches in regions of the semiconductor wafer between the integrated circuits, and plasma etching the semiconductor wafer includes extending the trenches to form corresponding trench extensions. In one such embodiment, each trench has a width, and each corresponding trench extension has the width.

In one embodiment, etching the semiconductor wafer 204 includes using a plasma etch process. In one embodiment, a through silicon via type etch process is used. For example, in a particular embodiment, the etch rate of the material of the semiconductor wafer 204 is greater than 25 microns per minute. The ultra-high density plasma source may be used in a plasma etch portion of a die sawing process. An example of a processing chamber suitable for performing such a plasma etch process is an Applied material available from Applied Materials of Sunnyvale, CA, USA, of Santalum, Calif

Silvia^TMAn etching system. Applied

Silvia^TMThe etching system incorporates capacitive and inductive RF coupling, which provides more independent control of ion density and ion energy than with capacitive coupling alone, even with the improvements provided by magnetic enhancement. This combination enables an effective decoupling of ion density from ion energy to achieve a relatively high density plasma even at very low pressures without generating high DC bias levels that could cause damage. This results in an unusually wide process window. However, any plasma etch chamber capable of etching silicon may be used. In an exemplary embodiment, a deep silicon etch is used to etch a single crystal silicon substrate or wafer 204 at an etch rate that is greater than about 40% of conventional silicon etch rates, while maintaining substantially precise profile control and virtually scallopless sidewalls. In a specific embodiment, a through silicon via type etch process is used. The etch process is based on a plasma generated from a reactive gas, typically a fluorine-based gas, such as SF₆、C₄F₈、CHF₃、XeF₂Or any other reactant gas capable of etching silicon at a relatively fast etch rate. In an embodiment, the light absorbing, water soluble patterned mask 208 is removed after the dicing process, as shown in fig. 2C, and as described in more detail below. In another embodiment, the plasma etch operation described in conjunction with fig. 2C employs a conventional Bosch-type deposition/etch/deposition process to etch through the substrate 204. Generally, the Bosch type process consists of three sub-operations: deposition, directional bombardment etching, and isotropic chemical etching, which are repeated (cycled) many times until the silicon is etched through.

In one embodiment, the patterned mask 208 is removed after the dicing process. In one embodiment, the patterned mask 208 is removed using an aqueous solution. In one such embodiment, the patterned mask 208 is removed by a thermal hydro-thermal process, such as a hot hydro-thermal process. In a particular embodiment, the patterned mask 208 is removed in a hot water process at a temperature approximately in the range of 40 degrees Celsius to 100 degrees Celsius. In a particular embodiment, the patterned mask 208 is removed in a hot water process at a temperature approximately in the range of 80-90 degrees Celsius. It should be understood that the higher the temperature of the water, the less time is required for hot water treatment. A plasma cleaning process may also be performed after etching to aid in removing patterned mask 208, in accordance with embodiments of the present invention.

It should be understood that other situations may benefit from lower water treatment temperatures. For example, where the wafer for slicing is supported on a dicing tape that may be affected by higher temperature water treatment (e.g., through loss of adhesion), a relatively lower water treatment temperature may be employed, even if for a longer duration than the relatively higher water treatment temperature. In one such embodiment, the water treatment is performed at a temperature between room temperature (i.e., the water is not heated) but below about 40 degrees celsius. In this particular embodiment, patterned mask 208 is removed in a warm water process at a temperature approximately in the range of 35-40 degrees Celsius.

Thus, referring again to flowchart 100 and fig. 2A-2C, wafer dicing may be performed by initial ablation to ablate through mask 202, through wafer streets (including metallization), and partially into the silicon substrate. The die cut may then be completed by a subsequent through-silicon deep plasma etch. A specific example of a material stack for slicing is described below in conjunction with fig. 5A-5D, according to an embodiment of the present invention.

Referring to fig. 5A, a material stack for hybrid laser ablation and plasma etch dicing includes a mask 502, a device layer 504, and a substrate 506. The mask layer 502, the device layer 504, and the substrate 506 are disposed over a die attach film 508, which die attach film 508 is secured to a backing tape 510. In other embodiments, direct coupling to standard chipper strips is used. In an embodiment, mask 502 is a mask such as described above in connection with mask 202. The device layer 504 includes an inorganic dielectric layer (such as silicon dioxide) disposed over one or more metal layers (such as copper layers) and one or more low-K dielectric layers (such as carbon-doped oxide layers). The device layer 504 also includes scribes disposed between integrated circuits that include the same or similar layers as the integrated circuits. Substrate 506 is a bulk monocrystalline silicon substrate. In one embodiment, the mask 502 is fabricated using a heat treatment or bake 599, such as described above.

In an embodiment, bulk single crystal silicon substrate 506 is thinned from the backside before being affixed to die attach film 508. Thinning may be performed by a backgrinding process. In one embodiment, bulk single crystal silicon substrate 506 is thinned to a thickness approximately in the range of 50-100 microns. It is important to note that in one embodiment, thinning is performed prior to the laser ablation and plasma etch dicing processes.

In one embodiment, mask 502 has a thickness approximately in the range of 1 micron to 5 microns, and device layer 504 has a thickness approximately in the range of 2 microns to 3 microns. In an embodiment, die attach film 508 (or any suitable alternative capable of bonding a thinned or thin wafer or substrate to backing tape 510, such as a dicing tape comprised of an upper adhesive layer and a base film) has a thickness approximately in the range of 10-200 microns. Referring to fig. 5B, a laser scribing process 512 is used to pattern the mask 502, the device layer 504, and a portion of the substrate 506 to form a trench 514 in the substrate 506. Referring to fig. 5C, a through-silicon deep plasma etch process 516 is used to extend the trench 514 down to the die attach film 508, thereby exposing a top portion of the die attach film 508 and cutting the silicon substrate 506. During the through-silicon deep plasma etch process 516, the device layer 504 is protected by the mask 502.

Referring to fig. 5D, the dicing process may further include patterning the die attach film 508, exposing a top portion of the backing tape 510, and dicing the die attach film 508. In one embodiment, the die attach film is cut by a laser process or by an etching process. Further embodiments may include later removing the diced portions of the substrate 506 from the backing tape 510 (e.g., as individual integrated circuits). In one embodiment, the diced die attach film 508 remains on the back side of the diced portion of the substrate 506. In an alternative embodiment, where substrate 506 is thinner than about 50 microns, laser scribing process 512 is used to completely cut substrate 506 without using an additional plasma process. Embodiments may also include removing the mask 502 from the device layer 504. The removal of mask 502 may be as described above with respect to removing patterned mask 208.

A single process tool may be configured to perform many or all of the operations of the hybrid laser ablation and plasma etch cutting processes using a light-absorbing, water-soluble mask. For example, FIG. 6 shows a block diagram of a tool layout for laser and plasma dicing a wafer or substrate according to an embodiment of the invention.

Referring to FIG. 6, a process tool 600 includes a factory interface 602(FI) having a plurality of load locks 604 coupled thereto. The cluster tool 606 is coupled to the factory interface 602. Cluster tool 606 includes one or more plasma etch chambers, such as plasma etch chamber 608. A laser scribing apparatus 610 is also coupled to the factory interface 602. In one embodiment, the total footprint of the process tool 600 may be approximately 3500 millimeters (3.5 meters) by approximately 3800 millimeters (3.8 meters), as shown in FIG. 6.

In an embodiment, laser scribing device 610 houses a laser assembly configured to provide a femtosecond-based laser beam. In an embodiment, the laser is adapted to perform a laser ablation portion of a hybrid laser and etch cutting process, such as the laser ablation process described above. In one embodiment, a movable stage is also included in the laser scribing apparatus 610, the movable stage being configured for moving the wafer or substrate (or its carrier) relative to the laser. In a particular embodiment, the laser is also movable. In one embodiment, the total footprint of the laser scribing apparatus 610 may be about 2240 millimeters by about 1270 millimeters, as shown in fig. 6.

In an embodiment, one or more plasma etch chambers 608 are configured for etching a wafer or substrate through gaps in a patterned mask to cut a plurality of integrated circuits. In one such embodiment, the one or more plasma etch chambers 608 are configured to perform a deep silicon etch process. In a particular embodiment, the one or more plasma etch chambers 608 are Applied available from Applied materials, sonervier, california, usaSilvia^TMAn etching system. The etch chamber may be specifically designed for deep silicon etching for producing monolithically integrated circuits housed on or in a monocrystalline silicon substrate or wafer. In one embodiment, a high density plasma source is included in plasma etch chamber 608 to facilitate a high silicon etch rate. In an embodiment, more than one etch chamber is included in the cluster tool 606 portion of the process tool 600 to enable high manufacturing throughput of the cutting or dicing process.

Factory interface 602 can be a suitable atmosphere port to interface between an external manufacturing facility and laser scribing apparatus 610 and cluster tool 606. The factory interface 602 may include a robot with an arm or blade for transferring wafers (or carriers thereof) from a storage unit (such as a front opening unified pod) into the cluster tool 606 or the laser scribing apparatus 610, or both.

The cluster tool 606 may include other chambers adapted to perform functions in the cutting method. For example, in one embodiment, a deposition and/or baking chamber 612 is included. Deposition and/or baking chamber 612 may be configured for mask deposition on or over a device layer of a wafer or substrate prior to laser scribing the wafer or substrate. Such a mask material may be baked prior to the dicing process, as described above. Such mask materials may be water soluble, as also described above.

In an embodiment, referring again to FIG. 6, a rinse station 614 is included. After the substrate or wafer is subjected to the laser scribing and plasma etch dicing process, or after the laser scribing only dicing process, the rinse station may be adapted to be cleaned to perform a room temperature or hot aqueous treatment to remove the light absorbing water soluble mask, as described above. In an embodiment, although not shown, a metrology station is also included as a component of the process tool 600. The cleaning chamber may include an atomized mist and/or supersonic (megasonics) nozzle hardware that adds physical components to the cleaning process to enhance the dissolution rate of the mask.

Embodiments of the present invention may be provided as a computer program product or software which may include a machine-readable medium having stored thereon instructions which may be used to program a computer system (or other electronic devices) to perform a process according to embodiments of the present invention. In one embodiment, a computer system is coupled to the process tool 600 described in conjunction with FIG. 6. A machine-readable medium includes any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium (e.g., read only memory ("ROM"), random access memory ("RAM"), magnetic disk storage media, optical storage media, flash memory devices, etc.), a machine (e.g., computer) readable transmission medium (e.g., electrical, optical, acoustical or other form of propagated signals (e.g., infrared signals, digital signals, etc.)), and the like.

Fig. 7 shows a schematic representation of a machine in the exemplary form of a computer system 700 within which a set of instructions, for causing the machine to perform any one or more of the methodologies described herein, may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a Local Area Network (LAN), an intranet, an extranet, or the internet. The machine may operate in the capacity of a server or a client machine in client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment. The machine may be a Personal Computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine. Additionally, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines (e.g., computers) that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

The exemplary computer system 700 includes a processor 702, a main memory 704 (e.g., Read Only Memory (ROM), flash memory, Dynamic Random Access Memory (DRAM), such as synchronous DRAM (sdram) or Rambus DRAM (RDRAM)), etc.), a static memory 706 (e.g., flash memory, Static Random Access Memory (SRAM), etc.), and a secondary memory 718 (e.g., data storage devices) that communicate with each other via a bus 730.

Processor 702 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 702 may be a Complex Instruction Set Computing (CISC) microprocessor, Reduced Instruction Set Computing (RISC) microprocessor, Very Long Instruction Word (VLIW) microprocessor, processor implementing other instruction sets, or processors implementing a combination of instruction sets. The processor 702 may also be one or more special-purpose processing devices such as an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), network processor, or the like. The processor 702 is configured to execute the processing logic 726 for performing the operations described herein.

The computer system 700 may also include a network interface device 708. The computer system 700 may also include a video display unit 710 (e.g., a Liquid Crystal Display (LCD), a light emitting diode display (LED), or a Cathode Ray Tube (CRT)), an alphanumeric input device 712 (e.g., a keyboard), a cursor control device 714 (e.g., a mouse), and a signal generation device 716 (e.g., a speaker).

The secondary memory 718 may include a machine-accessible storage medium (or more particularly, a computer-readable storage medium) 732 having stored thereon one or more sets of instructions (e.g., software 722) embodying any one or more of the methodologies or functions described herein. The software 722 may also reside, completely or at least partially, within the main memory 704 and/or within the processor 702 during execution thereof by the computer system 700, the main memory 704 and the processor 702 also constituting machine-readable storage media. The software 722 may further be transmitted or received over a network 720 via the network interface device 708.

While the machine-accessible storage medium 732 is shown in an exemplary embodiment to be a single medium, the term "machine-readable storage medium" should also be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions. The term "machine-readable storage medium" shall also be taken to include any medium that is capable of storing or encoding a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present invention. The term "machine-readable storage medium" shall accordingly be taken to include, but not be limited to, solid-state memories, and optical and magnetic media.

In accordance with an embodiment of the present invention, a machine-accessible storage medium has instructions stored thereon that cause a data processing system to perform a method of dicing a semiconductor wafer having a plurality of integrated circuits, such as one or more of the methods described herein.

Therefore, a hybrid wafer dicing method using a laser scribing process and a plasma etching process that realize a light absorption mask has been disclosed.