阅读说明：本技术 用于无线通信系统的并行序列噪声消除（PSiC）接收器架构 (Parallel sequence noise cancellation (PSiC) receiver architecture for wireless communication systems ) 是由 赛·莫翰·开拉姆比 胡兰 戴维·尼尔·威斯尔 于 2020-02-27 设计创作，主要内容包括：所公开的系统、结构和方法涉及一种无线接收器。本文所述的配置采用：信号编码模块,用于通过正交码集对多个接收的模拟信号进行编码,并将所述编码模拟信号组合成单个编码模拟复合信号；模数转换单元,用于将所述单个编码模拟复合信号转换为包含生成的数字信号的单个编码数字复合信号。本文所述的配置还包括：一组多个连续干扰消除(successive interference cancellation,SiC)模块,用于顺序地从所述单个编码数字复合信号中去除所述生成的数字信号,直到剩余单个组成的数字信号；以及解码模块,用于从所述单个编码数字复合信号中解码所述剩余的组成的数字信号。(The disclosed systems, structures, and methods relate to a wireless receiver. The configurations described herein employ: a signal encoding module for encoding a plurality of received analog signals by an orthogonal code set and combining the encoded analog signals into a single encoded analog composite signal; an analog-to-digital conversion unit for converting the single coded analog composite signal into a single coded digital composite signal comprising the generated digital signal. The configurations described herein also include: a set of a plurality of Successive Interference Cancellation (SiC) modules for sequentially removing the generated digital signals from the single encoded digital composite signal until a single constituent digital signal remains; and a decoding module for decoding said remaining constituent digital signals from said single encoded digital composite signal.)

1. A wireless receiver, comprising:

a signal encoding module for encoding a plurality of received analog signals by an orthogonal code set and combining the encoded analog signals into a single encoded analog composite signal;

an analog-to-digital conversion unit for converting the single coded analog composite signal into a single coded digital composite signal comprising the constituent digital signals;

a plurality of sets of Successive Interference Cancellation (SiC) modules, each of the SiC sets comprising a plurality of SiC modules for sequentially removing the constituent digital signals from the single encoded digital composite signal until a single constituent digital signal remains,wherein each member in each SiC group Each of the plurality of SiC modules is for removing the constituent digital signals from the single encoded digital composite signal Corresponding one of the numbers；

A plurality of decoding modules, each of said decoding modules for receiving said single encoded digital composite signal from a respective SiC group and for decoding said remaining constituent digital signals from said single encoded digital composite signal.

2. The wireless receiver of claim 1, further comprising a filter for minimizing aliasing effects of the single encoded analog composite signal.

3. The wireless receiver of claim 1 or 2, wherein each of the plurality of SiC modules within each SiC group comprises:

a first mixing element for mixing the single encoded digital composite signal with an orthogonal code corresponding to a digital signal of a particular composition;

an integrator unit for integrating the mixed coded digital composite signal;

an up-sampling unit, configured to up-sample the integrated hybrid coded digital composite signal;

a second mixing element for mixing the up-sampled encoded digital composite signal with the corresponding orthogonal code to generate the digital signal of the particular composition;

a subtraction element for removing the digital signal of the particular composition from the single encoded digital composite signal.

4. The wireless receiver of claim 3, further comprising a delay element that applies to the single encoded digital composite signal forwarded to the subtraction element to compensate for processing delays.

5. The wireless receiver of any of claims 1-4, wherein each of the decoding modules comprises:

a mixing element for mixing the remaining single constituent digital signals with respective orthogonal codes to generate coherent digital signals;

an integrator unit for integrating the coherent signal to generate a decoded composed digital signal.

6. The wireless receiver of any of claims 1-5, wherein for each of the SiC groups, the plurality of SiC modules are implemented in a serial arrangement to sequentially remove the constituent digital signals from the single encoded digital composite signal until a corresponding single constituent digital signal remains.

7. The wireless receiver of any one or more of claims 1 to 6, wherein the plurality of SiC sets are implemented in a parallel arrangement.

8. The receiver of any of claims 1-7, wherein the set of orthogonal codes comprises Hadamard (Hadamard) orthogonal codes.

9. The receiver according to any of claims 1 to 8, characterized in that the code rate of the orthogonal code set is at least an order of magnitude larger than the sampling rate of the received analog signal.

10. A method for processing a wireless signal, comprising:

encoding a plurality of received analog signals by an orthogonal code set and combining the encoded analog signals into a single encoded analog composite signal;

converting the single encoded analog composite signal into a single encoded digital composite signal comprising constituent digital signals;

sequentially removing the constituent digital signals from the single encoded digital composite signal through a plurality of sets of consecutive interference cancellation (SiC) modules until a single constituent digital signal remains, wherein the plurality of sets of SiC modulesEach of which comprises a plurality of SiC modules,wherein each of the SiC groups Each of the plurality of SiC modules removes the constituent digital signal from the single encoded digital composite signal Corresponding one of the numbers；

A plurality of decoding modules decode the remaining constituent digital signals from the single encoded digital composite signal, wherein each of the decoding modules receives the single encoded digital composite signal from a respective set of SiC.

11. The wireless processing method of claim 10, further comprising filtering the single encoded analog composite signal to minimize aliasing effects.

12. The wireless processing method according to claim 10 or 11, wherein each of the plurality of SiC modules within the SiC group includes:

first mixing the single encoded digital composite signal with an orthogonal code corresponding to a digital signal of a particular composition;

integrating the mixed encoded digital composite signal;

up-sampling the integrated mixed coded digital composite signal;

mixing the up-sampled encoded digital composite signal with the corresponding orthogonal code a second time to generate the digital signal of the particular composition;

removing the digital signal of the particular component from the single encoded digital composite signal.

13. The wireless processing method of claim 13, further comprising delaying the single encoded digital composite signal prior to removing to compensate for processing delays.

14. The wireless processing method of any of claims 10 to 13, wherein said decoding the digital signal of the residual component comprises:

mixing the remaining single constituent digital signals with respective orthogonal codes to generate coherent digital signals;

the coherent signal is integrated to generate a decoded composed digital signal.

15. The wireless processing method of any of claims 10 to 14, wherein for each of the SiC groups, the plurality of SiC modules are implemented in a serial arrangement to sequentially remove the constituent digital signals from the single encoded digital composite signal until a corresponding single constituent digital signal remains.

16. The wireless processing method of any of claims 10 to 15, further comprising implementing the plurality of SiC groups in a parallel arrangement.

17. The wireless processing method of claim 11, wherein the encoding of the received analog signal comprises a hadamard orthogonal code.

18. The wireless processing method of any of claims 10 to 17, wherein the code rate of the set of orthogonal codes used to encode the received analog signal is at least an order of magnitude greater than the sampling rate of the received analog signal.

Technical Field

The present invention generally relates to the field of wireless communications, and in particular, to a wireless communication receiver architecture for optimizing Code Division Multiplexed (CDM) signal decoding by using a parallel sequence noise cancellation (PSiC) technique.

Background

Generally, a wireless communication receiver system receives a plurality of analog data signals that have been encoded and modulated. These analog data signals may be combined in the receiver using Code Division Multiplexing (CDM) techniques that employ a set of codes having a higher frequency than the modulated analog data signals. The output signal produced by this combination is distributed over a wide bandwidth. The data signal is spread using a high code rate, which enables multiple input signals to be combined into a single signal before being sampled by an analog-to-digital converter (ADC), thereby sharing receiver hardware resources.

It should be appreciated, however, that the operation of decoding these high rate signals can present challenges to the wireless receiver system. That is, the receiver system needs to employ hardware, software and firmware elements capable of operating at higher speeds to properly process the high rate signal. Furthermore, such decoding operations may affect vector magnitude Error (EVM) performance.

Certain enhancements to existing wireless communication systems and next generation wireless communication designs may exacerbate these challenges. Such enhancements and designs include deploying high sample rate ADCs to sample the high code rate wideband signal. Such enhancements and designs may lead to a strain on receiver hardware and software processing resources.

Disclosure of Invention

It is an object of the present invention to provide a wireless receiver architecture for processing wireless analog signals. The disclosed wireless receiver architecture includes: a signal encoding module for encoding a plurality of received analog signals by an orthogonal code set and combining the encoded analog signals into a single encoded analog composite signal; an analog-to-digital conversion unit for converting the single coded analog composite signal into a single coded digital composite signal comprising the composed digital signals. The architecture disclosed by the present invention further comprises: a set of multiple Successive Interference Cancellation (SiC) modules for sequentially removing the constituent digital signals from the single encoded digital composite signal until a single constituent digital signal remains; and a decoding module for decoding said remaining constituent digital signals from said single encoded digital composite signal.

According to other aspects of the invention, a method for processing a wireless signal is provided. The wireless signal processing method disclosed by the invention comprises the following steps: encoding a plurality of received analog signals by an orthogonal code set and combining the encoded analog signals into a single encoded analog composite signal; and converting the single encoded analog composite signal to a single encoded digital composite signal comprising the constituent digital signals. The method disclosed by the invention further comprises the following steps: sequentially removing the constituent digital signals from the single encoded digital composite signal by a set of a plurality of Successive Interference Cancellation (SiC) modules until a single constituent digital signal remains; and decoding the remaining constituent digital signals in the single encoded digital composite signal.

Drawings

Further, the features and advantages of the present technology will be readily appreciated upon reading the following detailed description in conjunction with the accompanying drawings, in which:

fig. 1A shows a high-level functional block diagram of a conventional CDM receiver architecture;

fig. 1B shows a representative example of a conventional CDM encoding technique;

fig. 1C shows a representative example of a conventional CDM decoding technique;

FIG. 2A is a functional block diagram of a parallel sequence noise cancellation (PSiC) receiver decoding architecture according to various embodiments of the present invention;

fig. 2B illustrates the basic decoding and interference cancellation modules included in the PSiC receiver decoding architecture provided by various embodiments of the present invention;

fig. 3 illustrates a functional flow diagram of a PSiC-based receiver decoding process provided by various embodiments of the present invention;

FIG. 4A shows representative simulation test performance results of conventional CDM decoder processing at a standard code rate;

FIG. 4B shows a representative simulation test performance result of the PSiC decoder processing at the standard code rate provided by various embodiments of the present invention;

fig. 4C shows representative performance of simulation test performance results of the PSiC decoder process at reduced code rates provided by various embodiments of the present invention.

It should be understood that throughout the drawings and the accompanying description, like features are identified with like reference numerals. Furthermore, it is to be understood that the drawings and the following description are for illustration purposes only and that the present disclosure is not intended to limit the scope of the appended claims.

Detailed Description

The term "about" or "approximately" as used herein refers to a variation of +/-10% from the nominal value. It is to be understood that such a variation is always included in a given value provided herein, whether or not it is specifically referred to.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs.

Fig. 1A shows a functional block diagram of the architecture of a conventional receiver 100 for processing a received analog signal. The conventional receiver 100 includes a code division multiplexer encoder module 110, an anti-aliasing filter 116, an analog-to-digital converter (ADC) 118, and a CDM decoder module 120. CDM encoder module 110, in turn, comprises analog mixing elements 112-1 … … 112-M and combiner unit 114. CDM decoder module 120 comprises a coherence element 122-1 … … 122-M and an integrator element 124-1 … … 124-M. Other elements may be present but are not shown for simplicity.

As shown in FIG. 1A, a conventional receiver 100 receives M analog signals x₁(t)、x₂(t)……x_M(t), which may be received by one or more suitable structures, such as Multiple-Input-Multiple-Output (MIMO)/Massive MIMO (M-MIMO) antennas (not shown). Furthermore, each of the received M analog signals may have different modulation/coding characteristics.

As shown, CDM encoder module 110 is used to receive and encode M received analog signals x₁(t)、x₂(t)……x_M(t) and converting it into a single composite encoded analog signal y (t). In particular, the signal x₁(t)、x₂(t)……x_M(t) respectively passing through corresponding analog mixing elements 112-1 … … 112-M and including code c₁、c₂……c_MCode set mixing of (2). The encoded M analog signals are then combined by combiner unit 114 to generate a single encoded analog signal y (t).

It should be appreciated that the code set c₁、c₂……c_MMay be based on any orthogonal or pseudo-random noise (PN) code such as Walsh, hadamard, Gold, Barker codes, etc. These codes have the required coding properties and can be significantly higher than the received analog signal x₁(t)、x₂(t)……x_M(t) sampling rate F_sCoding rate of F_cThe following is implemented. In various implementations, the code rate F_cAt least than the signal sampling rate F_sOne order of magnitude larger. Thus, the CDM encoder block 110 outputsA single high-rate encoded analog signal y (t) that is effectively distributed over a wide bandwidth.

As a non-limiting illustrative example, two received analog signal streams may be considered: x is the number of_a(t) comprising data symbols a1, a2, a 3; x is the number of_b(t) comprising data symbols b1, b2, b3, and two orthogonal codes: c. C_aComprising [1, -1, 1, -1]；c_bComprising [1, -1, -1, 1]As shown in fig. 1B. As described above, CDM encoder module 110 separately encodes the analog symbols x_a(t)、x_b(t) and orthogonal code c_a、c_bMixing to generate the encoded streams shown in fig. 1B. The encoded streams are then provided to combiner unit 114 to output a single encoded wideband analog signal y (t), as shown below.

As shown in fig. 1A, the single encoded analog signal y (t) may then be provided to an anti-aliasing filter (AAF) 116. The AAF 116 serves to limit the bandwidth of interest and mitigate signal components that may cause aliasing effects. The filtered encoded analog signal (output of AAF 116) may then be provided to analog-to-digital converter ADC 118. ADC 118 converts the filtered encoded analog signal y (t) to an encoded wideband digital composite signal y_i(t)。

After digital conversion, the encoded wideband digital signal y may be_i(t) transmitted downstream for further processing, such as decoding operations performed by CDM decoder module 120. CDM decoder module 120 processes the encoded digital composite signal y_i(t) to convert y_i(t) signal is decoded and separated into digital signal x'₁、x'₂……x'_MThe digital signals comprise received M analog signals x₁(t)、x₂(t)……x_M(t) information content.

In the particular embodiment shown in FIG. 1A, the digital composite signal y will be encoded_i(t) forward to respective coherence element 122-1 … of CDM decoder module 120… 122-M. Providing each of the coherence elements 122-1 … … 122-M with a code from the set of codes c₁、c₂……c_MWith a corresponding code of the signal y_i(t) mixing to generate coherent mixed digital samples. The coherently mixed digital samples are then processed by respective integrating elements 124-1 … … 124-M to integrate (i.e., average) the digital samples to generate M analog signals x that are received in the presentation₁(t)、x₂(t)……x_M(t) signal x 'of information content'₁、x'₂……x'_M。

Fig. 1C illustrates an example of a CDM decoding operation that may be used in conjunction with the CDM encoding example of fig. 1B. FIG. 1C shows that_i(t) decomposition into a representation of the received analog signal x_a(t) digital signal x 'of information content'_a. As shown, CDM decoder module 120 will encode the digital composite signal y_i(t) and orthogonal code c_aMixing and coherent processing is performed to generate coherent digital symbols as shown in fig. 1C. The coherent digital symbols are then combined and integrated to output a digital signal x ' comprising digital symbols a '1, a '2, a '3 '_aAs shown in fig. 1C. In this manner, the combining and integrating process may cancel out the other constituent signals when modulated by other orthogonal codes to generate digital symbols a '1, a '2, a '3 that represent the information content of the received analog data symbols a1, a2, a 3.

It will be appreciated that the coherent operation described above, which in theory effectively cancels the incoherent signal components during the decoding operation, is difficult to achieve in practice. One contributing factor is that the encoding operation occurs in the analog domain, while the decoding operation occurs in the digital domain. It is also desirable to assume that the analog symbols do not change during the code length period. However, in practice, the analog symbols may change over the code length period, which introduces residue from other symbols during the digital code coherence and integration process, resulting in interference errors.

These interference errors can be reduced by increasing the code rate to increase the symbol variation over the code length period. However, this increase in code rate may result in excessive cost from a hardware and implementation perspective. Furthermore, the increase in code rate may further increase the burden on the constituent modules and components (e.g., analog mixers, ADCs, etc.) of the conventional receiver 100.

Fig. 2A shows a functional block diagram of a parallel sequence noise cancellation (PSiC) receiver 200 according to various embodiments of the present invention. The PSiC receiver 200 removes the embedded wideband digital signal y by a parallel serial manner_i(t) interference of other digital signals to digitally encode the wideband digital signal y_i(t) extracting and decoding the digital signal of interest.

In other words, each parallel path of the PSiC receiver 200 will treat all but one of the digital signals of interest as interference signals. In operation, this results in the successive removal of each interfering signal until only the digital signal of interest remains. Thus, as each interfering signal is sequentially decoded and removed, the vector magnitude Error (EVM) of the last digital signal to be decoded (i.e., the digital signal of interest) will exhibit minimal interference from other previously decoded signals.

As shown in fig. 2A, the PSiC receiver 200 has multiple parallel paths, each of which includes multiple Successive Interference Cancellation (SiC) modules 220. Each of the SiC modules 220 removes interference from other digital signals based on the applied orthogonal code. By implementing SiC block 220 sequentially along each parallel path, PSiC receiver 200 continues processing during the decoding operation to cancel each interfering signal until the digital signal of interest remains.

Fig. 2B illustrates a basic SiC module 220 provided by various embodiments of the present invention. In the depicted embodiment, SiC module 220 derives a wideband digital signal y_iThe signal RX2 is removed in (t). SiC module 220 includes a first mixing element 222, an integrator unit 224, an upsampling unit 226, a second mixing element 228, a subtracting element 230, and a delay element 232.

As shown, the first mixing element 222 receives the encoded wideband digital signal y_i(t) for converting the signal y_i(t) is mixed with the same orthogonal code (in this example orthogonal code 2) that was originally used to encode the signal RX 2. In this way, first mixing element 222 may remove all signals except for signal RX 2. The mixed signal y_i(t) is provided to an integrator unit 224 which effectively averages a mixed signal of a plurality of samples. The output of integrator unit 224 is therefore an effectively downsampled decoded version of signal RX 2. The averaged signal is then up-sampled by a factor equal to the number of average samples by up-sampling unit 226 to compensate for the down-sampling effect of integrator unit 224.

The up-sampled signal is then mixed again with the orthogonal code 2 by the second mixing element 228 to generate the encoded signal RX 2. The encoded signal RX2 is then forwarded to a subtraction element 230.

The SiC module 220 further provides the broadband digital signal y to the delay element 232_i(t) copies. The delay introduced by the delay element 232 is comparable to the processing time required by the first mixing element 222, the integrator unit 224, the upsampling unit 226, the second mixing element 228. Wideband digital signal y_iThe delayed version of (t) is used as an input to a subtraction element 230, which subtracts the signal y from the wideband digital signal y_i(t) minus the code signal RX 2. Thus, the output of the SiC module 220 is y_i(t), signal RX2 is substantially removed, i.e. y_i(t)–RX 2。

Assuming the basic SiC block 220 described above, for the M encoded signals, the PSiC receiver 200 sequentially combines the M-1 SiC blocks 220 along each of the M parallel paths to successively remove the interference of the M-1 signals until the last digital signal to decode (i.e., the digital signal of interest) remains. This systematization process is performed in parallel through the M paths of the PSiC receiver 200 to decode the entire M digital signals.

In view of this, FIG. 2A provides an exemplary scenario for a PSiC receiver 200 incorporating SiC blocks 220-1 through 220-4 to decode a signal from an encoded wideband digital signal y_i(t) four signals x'₁(RX1)、x'₂(RX2)、x'₃(RX3) and x'₄(RX 4). In particular, for the first parallel path, the PSiC receiver 200 employs a first set 250-1 of sequentially implemented SiC blocks 220-2, 220-3, and 220-4 that separately and successively remove the signal from the encoded wideband digital signal y_i(t) signal x'₂(RX2)、x'₃(RX3) and x'₄(RX 4). This effectively results from a wideband digital signal y_i(t) extracting/decoding the first signal of interest x'₁(RX1)。

In particular, SiC modules 220-2 of first group 250-1 receive and process wideband digital signal y_i(t) to effectively remove x 'from the signal'₂(RX 2). The signal generated by SiC block 220-2, i.e., [ y ]_i(t)–x'₂(RX2)]Is provided to SiC module 220-3, which removes signal x 'in a similar manner'₃(RX3) to generate a resultant signal [ y_i(t)–x'₂(RX2)–x'₃(RX3)]. In turn, the signal generated by SiC module 220-3 is provided to SiC module 220-4, which also removes signal x 'in a similar manner'₄(RX4) to generate a resultant signal [ y_i(t)–x'₂(RX2)–x'₃(RX3)–x'₄(RX4)]. At this stage, signal x 'is removed'₂(RX2)、x'₃(RX3) and x'₄After interference of (RX4), there is only the signal of interest, i.e. x'₁(RX1) remaining on signal y_i(t) in (a).

PSiC receiver 200 would then only contain the remaining x'₁(RX1) signal y_i(t) to decoder module 255-1, which decodes and extracts x'₁(RX 1). In particular, decoder module 255-1 converts signal y_i(t) with the code x originally used to encode₁(t) the same orthogonal codes of the signal (i.e., orthogonal code 1) are mixed to generate a coherent digital signal. The coherent digital signal is then integrated to generate x'₁Presents a received analog signal x₁(t) desired digital information content.

In a similar manner, as shown in FIG. 2A, the PSiC receiver 200 implements the second, third, and fourth sets 250-2, 250-3, 250-4 in a parallel manner to systematically remove the corresponding sums for eachThe row path is not a signal disturbance of the signal of interest. Left on the signal y after processing by the respective groups 250-2, 250-3, 250-4_iThe signal of interest in (t) is then decoded and extracted by the corresponding decoder modules 255-2, 255-3, 255-4.

In this manner, the PSiC receiver 200 effectively extracts and decodes a particular digital signal of interest in a parallel serial manner by removing interference from other digital signals embedded in the wideband digital signal. It should be appreciated that the PSiC receiver 200 may be implemented by software constructs to facilitate integration with existing receiver architectures (e.g., the architecture of the legacy receiver 100). It should also be understood that, although the modules and components of the PSiC receiver 200 are described and depicted herein as discrete elements for the sake of brevity, these modules and components may be shared, combined, and/or integrated without departing from the disclosed embodiments.

Fig. 3 illustrates a functional flow diagram of a process 300 for operation of a PSiC-based receiver provided by various embodiments of the present invention. As shown, process 300 begins with task block 310, where PSiC receiver 200 receives a plurality of analog signals containing desired information content. As described above, each of the received wireless analog signals may have different modulation/coding properties.

Process 300 continues with task block 312 where the plurality of received signals are encoded by mixing the received signals with an orthogonal code via analog mixing elements. The encoded analog signals are then combined by a combiner unit to generate a single analog composite signal.

At task block 314, process 300 filters the single analog composite signal and generates a single digital composite signal. As described above, the anti-aliasing filter performs filtering operations to limit the bandwidth of interest and mitigate signal components that may cause aliasing. The filtered coded analog signal is then supplied to an analog-to-digital converter ADC which converts the filtered coded analog signal y (t) into a coded wideband digital composite signal y_i(t)。

Process 300 advances to task block 316 where the PSiC receiver200 successively decode and remove the digital composite signal y in a sequential manner_iDigital signal in (t) up to a digital composite signal y_i(t) leaving only the signal of interest. That is, as shown in fig. 2A, the PSiC receiver 200 sequentially merges a set of multiple SiC modules 220 along a path, wherein each of the SiC modules 220 removes interference from the digital signal based on the applied orthogonal code until only the digital signal of interest remains. Then, in task block 318, the PSiC receiver 200 derives the composite signal y from the composite signal_i(t) decoding the remaining digital signal of interest.

At decision block 320, the process 300 determines whether all M digital signals of interest have been derived from the composite signal y_iAnd (t) decoding. If so, the process 300 ends; if not, process 300 proceeds to task block 322, where the successive removal/decoding operations of task block 316 for all PSiC receiver 200 paths are repeated in parallel until the composite digital signal y is embedded_iAnd (t) completing the analysis and decoding of all digital signals. As shown in fig. 2A, sequential groups of SiC blocks 220 are implemented for each parallel path of the PSiC receiver 200 until the composite digital signal y is derived_i(t) all signals are done (e.g., x'₁(RX1)、x'₂(RX2)、x'₃(RX3) and x'₄(RX 4)).

Fig. 4A shows representative simulation test results of conventional CDM decoder processing (i.e., without PSiC decoding). The simulation applies a non-limiting exemplary scenario, including four 20MHz LTE OFDM signals, with a code rate F_cIs the signal sampling rate F_s32 times (i.e., F)_c＝32x F_s). For this scenario, the average vector magnitude Error (EVM) performance handled by a conventional CDM decoder is 4.1%, and the peak EVM performance is 16.8%.

FIG. 4B illustrates the standard code rate (i.e., F) provided by various embodiments of the invention_c＝32x F_s) Representative simulation test results of the following PSiC decoder process. With a similar simulation scenario, the average EVM performance processed by the PSiC decoder is 0.3%, and the peak EVM performance is 1.7%.

FIG. 4CIllustrating the reduced code rate (i.e., F) provided by various embodiments of the present invention_c＝16x F_s) Representative simulation test performance results for the lower PSiC decoder process. Even though the code rate is reduced by half, the PSiC decoder processing is still significantly improved compared to the conventional CDM decoder processing, with an average EVM performance of 1.2% and a peak EVM performance of 6.7%.

It should be understood that the operations and functions of the described wireless receiver architecture, constituent components, and associated processes may be implemented by hardware-based, software-based, firmware-based elements, and/or combinations thereof. Such operational alternatives do not limit the scope of the invention in any way.

It will also be understood that while the principles of the invention have been described herein with reference to specific features, structures and embodiments, it will be apparent that various modifications and combinations can be made without departing from the disclosure. The specification and figures are to be regarded only as illustrative of the invention as defined in the appended claims and any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention are contemplated.