阅读说明：本技术 电动汽车及其电机控制系统 (Electric automobile and motor control system thereof ) 是由 蒋元广 史洋洋 李国庆 张贺 李占江 高超 任钢 于 2019-10-15 设计创作，主要内容包括：本发明公开了一种电动汽车及其电机控制系统,其中,该电机控制系统包括：驱动模块,所述驱动模块与所述电动汽车的电机相连,以驱动所述电机；主控模块,所述主控模块包括控制芯片和可编程逻辑器件,所述可编程逻辑器件与所述驱动模块相连,所述控制芯片与所述可编程逻辑器件相连。由此,通过设置独立于控制芯片的硬件保护电路,能够实时、快速地对电机控制系统进行故障检测和保护,提高电机控制系统的安全性和可靠性。(The invention discloses an electric automobile and a motor control system thereof, wherein the motor control system comprises: the driving module is connected with a motor of the electric automobile so as to drive the motor; the main control module comprises a control chip and a programmable logic device, the programmable logic device is connected with the driving module, and the control chip is connected with the programmable logic device. Therefore, the fault detection and protection can be carried out on the motor control system in real time and rapidly by arranging the hardware protection circuit independent of the control chip, and the safety and reliability of the motor control system are improved.)

1. A motor control system of an electric vehicle, comprising:

the driving module is connected with a motor of the electric automobile so as to drive the motor;

the main control module comprises a control chip and a programmable logic device, the programmable logic device is connected with the driving module, the control chip is connected with the programmable logic device, the control chip is used for outputting a motor control signal to the driving module through the programmable logic device so that the driving module drives the motor to operate, and the programmable logic device is used for carrying out fault detection on the motor control system and outputting a driving closing signal to the driving module when a fault is detected so as to close the driving module.

2. The motor control system of an electric vehicle according to claim 1, wherein the main control module further comprises:

the sampling circuit is respectively connected with the motor and the driving module and is used for collecting three-phase current of the motor, direct-current bus voltage of the driving module and temperature of the driving module;

the comparison circuit is used for comparing the three-phase current of the motor, the direct-current bus voltage of the driving module and the temperature of the driving module so as to correspondingly generate a three-phase overcurrent fault signal, a bus voltage fault signal and a driving module over-temperature fault signal, and sending the three-phase overcurrent fault signal, the bus voltage fault signal and the driving module over-temperature fault signal to the programmable logic device;

and the programmable logic device carries out fault detection on the motor control system according to the three-phase overcurrent fault signal, the bus voltage fault signal, the over-temperature fault signal of the driving module and the fault feedback signal of the driving module.

3. The motor control system of an electric vehicle according to claim 1, wherein the main control module further comprises:

the rotary transformer decoding circuit is connected with the control chip and used for decoding a position signal of the motor and sending the position signal of the motor to the control chip;

the control chip is used for acquiring the three-phase current of the motor, and generating and outputting the motor control signal according to the three-phase current of the motor and the position signal of the motor.

4. The motor control system of an electric vehicle according to claim 1, wherein the programmable logic device is designed using Verilog HDL hardware description language.

5. The motor control system of the electric vehicle according to claim 2 or 4, wherein the programmable logic device comprises a logic protection submodule for performing logic judgment on the received fault signal and determining whether a fault is detected according to a judgment result.

6. The motor control system of an electric vehicle according to claim 5, wherein the fault signals include the three-phase overcurrent fault signal, the bus voltage fault signal, the drive module over-temperature fault signal, and the fault feedback signal of the drive module, and a main control power supply and a reset signal input to the main control module.

7. The motor control system of an electric vehicle of claim 5, wherein the logic protection submodule comprises:

the first logic unit is used for carrying out logical OR operation on the received fault signals and setting a fault mark when judging that a fault is detected according to any fault signal;

the second logic unit is used for performing logic and operation on the fault mark, the main control power supply input to the main control module and a reset signal so as to determine the working state of the motor control system, wherein the working state of the motor control system comprises a fault state, an idle state and a normal operation state;

a third logic unit, configured to generate the motor control signal or the driving shutdown signal according to a working state in which the motor control system is located, where the motor control signal is generated in the normal operation state, and the driving shutdown signal is generated in the fault state and the idle state.

8. The motor control system of claim 1, wherein the programmable logic device further comprises a communication sub-module, wherein the communication sub-module is in SPI full duplex serial communication with the control chip.

9. The motor control system of claim 8, wherein the communication submodule comprises a chip select terminal for receiving a chip select signal, a clock terminal for receiving a clock signal, an output terminal for outputting an output signal, and an input terminal for receiving an input signal, wherein the input terminal and the output terminal of the communication submodule receive and transmit signals under the control of the clock signal when the chip select signal is active.

10. The motor control system of an electric vehicle according to claim 1, wherein the programmable logic device is further configured to output a fault detection signal to the control chip when a fault is detected, so that the control chip performs secondary protection.

11. The motor control system of claim 1, wherein the driving module comprises a driving and protection circuit and a power module, the driving and protection circuit is connected to the programmable logic device, the power module is respectively connected to the driving and protection circuit and the motor, and the power module is further connected to a power supply.

12. An electric vehicle characterized by comprising the motor control system of the electric vehicle according to any one of claims 1 to 11.

Technical Field

The invention relates to the technical field of automobiles, in particular to an electric automobile and a motor control system thereof.

Background

In the related art, the fault detection and protection functions of the motor control system of the electric vehicle are handled by the control chip of the motor control system, which increases the load of the control chip, so that under the condition that the driving conditions of the electric vehicle are various and complicated, the speed and the accuracy of the fault detection and protection of the motor control system by the control chip will become low, which reduces the safety and the reliability of the motor control system.

Disclosure of Invention

The present invention is directed to solving, at least to some extent, one of the technical problems in the related art.

Therefore, a first object of the present invention is to provide a motor control system of an electric vehicle, which can detect and protect faults of the motor control system in real time and rapidly by providing a hardware protection circuit independent of a control chip, so as to improve the safety and reliability of the motor control system.

The second purpose of the invention is to provide an electric automobile.

In order to achieve the above object, a first aspect of the present invention provides a motor control system of an electric vehicle, including: the driving module is connected with a motor of the electric automobile so as to drive the motor; the main control module comprises a control chip and a programmable logic device, the programmable logic device is connected with the driving module, the control chip is connected with the programmable logic device, the control chip is used for outputting a motor control signal to the driving module through the programmable logic device so that the driving module drives the motor to operate, and the programmable logic device is used for carrying out fault detection on the motor control system and outputting a driving closing signal to the driving module when a fault is detected so as to close the driving module.

According to the motor control system of the electric automobile, the fault detection is carried out on the motor control system through the programmable logic device, and the driving closing signal is output to the driving module when the fault is detected so as to close the driving module.

In addition, the motor control system of the electric automobile provided by the embodiment of the invention can also have the following additional technical characteristics:

according to an embodiment of the present invention, the main control module further includes: the sampling circuit is respectively connected with the motor and the driving module and is used for collecting three-phase current of the motor, direct-current bus voltage of the driving module and temperature of the driving module; the comparison circuit is used for comparing the three-phase current of the motor, the direct-current bus voltage of the driving module and the temperature of the driving module so as to correspondingly generate a three-phase overcurrent fault signal, a bus voltage fault signal and a driving module over-temperature fault signal, and sending the three-phase overcurrent fault signal, the bus voltage fault signal and the driving module over-temperature fault signal to the programmable logic device; and the programmable logic device carries out fault detection on the motor control system according to the three-phase overcurrent fault signal, the bus voltage fault signal, the over-temperature fault signal of the driving module and the fault feedback signal of the driving module.

According to an embodiment of the present invention, the main control module further includes: the rotary transformer decoding circuit is connected with the control chip and used for decoding a position signal of the motor and sending the position signal of the motor to the control chip; the control chip is used for acquiring the three-phase current of the motor, and generating and outputting the motor control signal according to the three-phase current of the motor and the position signal of the motor.

According to one embodiment of the invention, the programmable logic device is designed using the Verilog HDL hardware description language.

According to one embodiment of the present invention, the programmable logic device includes a logic protection submodule configured to perform a logic determination on a received fault signal, and determine whether a fault is detected according to a determination result.

According to one embodiment of the present invention, the fault signals include the three-phase overcurrent fault signal, the bus voltage fault signal, the driving module over-temperature fault signal, and the fault feedback signal of the driving module, and a main control power supply and a reset signal input to the main control module.

According to one embodiment of the invention, the logic protection submodule comprises: the first logic unit is used for carrying out logical OR operation on the received fault signals and setting a fault mark when judging that a fault is detected according to any fault signal; the second logic unit is used for performing logic and operation on the fault mark, the main control power supply input to the main control module and a reset signal so as to determine the working state of the motor control system, wherein the working state of the motor control system comprises a fault state, an idle state and a normal operation state; a third logic unit, configured to generate the motor control signal or the driving shutdown signal according to a working state in which the motor control system is located, where the motor control signal is generated in the normal operation state, and the driving shutdown signal is generated in the fault state and the idle state.

According to an embodiment of the present invention, the programmable logic device further includes a communication submodule, wherein the communication submodule performs SPI full-duplex serial communication with the control chip.

According to an embodiment of the present invention, the communication submodule includes a chip select terminal, a clock terminal, an output terminal and an input terminal, the chip select terminal is configured to receive a chip select signal, the clock terminal is configured to receive a clock signal, the output terminal is configured to output an output signal, and the input terminal is configured to receive an input signal, wherein when the chip select signal is valid, the input terminal and the output terminal of the communication submodule perform signal receiving and sending under control of the clock signal.

According to an embodiment of the present invention, the programmable logic device is further configured to output a fault detection signal to the control chip when a fault is detected, so that the control chip performs secondary protection.

According to one embodiment of the invention, the driving module comprises a driving and protecting circuit and a power module, the driving and protecting circuit is connected with the programmable logic device, the power module is respectively connected with the driving and protecting circuit and the motor, and the power module is also connected with a power supply.

In order to achieve the above object, an embodiment of the second aspect of the present invention provides an electric vehicle, which includes a motor control system of the electric vehicle provided in the embodiment of the first aspect of the present invention.

According to the electric automobile provided by the embodiment of the invention, the motor control system of the electric automobile can detect and protect the fault of the motor control system in real time and rapidly, and the safety and reliability of the motor control system are improved.

Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.

Drawings

The foregoing and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:

FIG. 1 is a block schematic diagram of a motor control system of an electric vehicle according to an embodiment of the present invention;

FIG. 2 is a block schematic diagram of a motor control system of an electric vehicle according to one embodiment of the present invention;

FIG. 3 is a block diagram of a three-stage state machine of a motor control system of an electric vehicle according to one embodiment of the present invention;

FIG. 4 is a flow chart of a communication sub-module of a motor control system of an electric vehicle according to one embodiment of the invention;

FIG. 5 is a block schematic diagram of an electric vehicle according to an embodiment of the present invention; and

fig. 6 is a hardware architecture diagram of a motor control system of an electric vehicle according to an embodiment of the present invention.

Detailed Description

Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative and intended to be illustrative of the invention and are not to be construed as limiting the invention.

A motor control system of an electric vehicle according to an embodiment of the present invention is described in detail below with reference to the accompanying drawings.

Fig. 1 is a block diagram illustrating a motor control system of an electric vehicle according to an embodiment of the present invention. As shown in fig. 1 and 6, the motor control system 101 includes a drive module 102 and a main control module 104.

The driving module 102 is connected with a motor 103 of the electric automobile to drive the motor 103; the main control module 104 includes a control chip 105 and a programmable logic device 106, the programmable logic device 106 is connected to the driving module 102, the control chip 105 is connected to the programmable logic device 106, the control chip 105 is configured to output a motor control signal to the driving module 102 through the programmable logic device 106 so that the driving module 102 drives the motor 103 to operate, and the programmable logic device 106 is configured to perform fault detection on the motor control system 101 and output a driving shutdown signal to the driving module 102 when a fault is detected so as to shut down the driving module 102.

It should be noted that the motor 103 may be controlled by a current loop-speed loop double closed loop speed regulation manner, so that the electric vehicle may still achieve precise control of the motor 103 under various and complicated conditions.

It is understood that the programmable logic device 106 transmits the motor control signal or the driving shutdown signal to the driving module 102 according to the fault detection result, so as to control the motor 103 through the driving module 102.

Specifically, the control chip 105 may generate 6 paths of PWM (Pulse width modulation) driving signals according to internal control logic and an algorithm, the programmable logic device 106 performs real-time fault detection on the motor control system 101, when a detection result is normal, the programmable logic device 106 transmits the 6 paths of PWM driving signals output by the control chip 105 to the driving module 102, and a power module in the driving module 102 is turned on and off according to the 6 paths of PWM driving signals, that is, the 6 paths of PWM driving signals are switching control signals of the power module, so that the motor 103 controls, for example, a permanent magnet synchronous motor to operate; when the detection result is a fault, the programmable logic device 106 sets all the 6 channels of PWM driving signals output by the control chip 105 to low level, and outputs the low level to the driving module 102, the power module in the driving module 102 is turned off, and the motor 103 stops running.

Therefore, the programmable logic device 106 in the main control module 104 is arranged independently of the control chip 105, and shares the functions of real-time fault detection and protection of the motor control system 101 originally belonging to the control chip 105, so that the load of the control chip is shared, the IO port of the main control chip is indirectly expanded, the functions to be added in the future can be expanded in the programmable logic device, and the functions are easy to expand. In addition, the use number of electronic components can be reduced, and the space is saved.

In addition, the programmable logic device 106 is further configured to output a fault detection signal to the control chip 105 when a fault is detected, so that the control chip 105 performs secondary protection. The secondary protection may be that the control chip 105 stops outputting the 6-channel PWM driving signal. Therefore, the load of the control chip can be reduced, the fault detection and protection efficiency of the motor control system is improved, the dual protection of hardware and software is achieved, and the safety and reliability of the motor control system are improved.

In the embodiment of the present invention, the programmable logic device 106 may adopt a fast parallel operation mode, so that a fault can be determined more quickly according to the parallel processing mode, the driving module can be protected fast, and the service life of the motor controller can be prolonged. The programmable logic device 106 and the control chip 105 may communicate serially.

According to an embodiment of the present invention, as shown in fig. 2 and fig. 6, the main control module 104 further includes: a sampling circuit 201 and a comparison circuit 202.

The sampling circuit 201 is connected to the motor 103 and the driving module 102, and the sampling circuit 201 is configured to collect the U/V/W three-phase current of the motor 103, the dc bus voltage of the driving module 102, and the temperature of the driving module 102, and send the U/V/W three-phase current of the motor 103, the dc bus voltage of the driving module 102, and the temperature of the driving module 102, which are collected in real time, to the comparison circuit 202. As an example, as shown in fig. 6, the sampling circuit 201 may include a current sampling circuit 602 and a bus voltage and temperature sampling circuit 603, where the current sampling circuit 602 is used to collect U/V/W three-phase current of the motor 103, and the bus voltage and temperature sampling circuit 603 is used to collect dc bus voltage of the driving module 102 and temperature of the driving module 102.

The comparison circuit 202 is respectively connected with the sampling circuit 201 and the programmable logic device 106, and the comparison circuit 202 is configured to compare the U/V/W three-phase current of the motor 103, the dc bus voltage of the driving module 102, and the temperature of the driving module 102 to generate a three-phase overcurrent fault signal, a bus voltage fault signal, and a driving module over-temperature fault signal, and send the three-phase overcurrent fault signal, the bus voltage fault signal, and the driving module over-temperature fault signal to the programmable logic device 106. The programmable logic device 106 detects the fault of the motor control system according to the three-phase overcurrent fault signal, the bus voltage fault signal, the over-temperature fault signal of the driving module and the fault feedback signal of the driving module 102.

It can be understood that the comparison circuit 202 may preset a three-phase current threshold, a dc bus voltage threshold, and a temperature threshold, when the U/V/W three-phase current of the motor 103 acquired in real time is greater than the three-phase current threshold, the comparison circuit 201 may generate a three-phase overcurrent fault signal correspondingly, and send the three-phase overcurrent fault signal to the programmable logic device 106, the programmable logic device 106 sets all 6 PWM driving signals output from the control chip 105 to low levels, and outputs the low levels to the driving module 102, the driving module 102 is turned off, and the motor 103 stops operating.

Similarly, when the dc bus voltage of the driving module 102 collected in real time is greater than the dc bus voltage threshold, the comparing circuit 201 generates a bus voltage fault signal correspondingly, and sends the bus voltage fault signal to the programmable logic device 106, the programmable logic device 106 sets all the 6 channels of PWM driving signals output by the control chip 105 to be low level, and outputs the low level to the driving module 102, the driving module 102 is turned off, and the motor 103 stops operating.

When the temperature of the driving module 102 acquired in real time is greater than the temperature threshold, the comparison circuit 201 generates a driving module over-temperature fault signal correspondingly, and sends the driving module over-temperature fault signal to the programmable logic device 106, the programmable logic device 106 sets all the 6 paths of PWM driving signals output by the control chip 105 to be low level, and outputs the low level to the driving module 102, the driving module 102 is turned off, and the motor 103 stops operating.

It can be understood that, in the operation process of the motor controller, the sampling circuit 201 samples three-phase overcurrent fault signals, bus voltage fault signals and driving module over-temperature fault signals in real time, the three signal samples are independently performed, the comparison circuit 202 compares the three-phase overcurrent fault signals, the bus voltage fault signals and the driving module over-temperature fault signals which are sampled in real time with three-phase current threshold values, direct-current bus voltage threshold values and temperature preset values respectively, generates corresponding fault signals and sends the fault signals to the programmable logic device 102, the three sampling signals are independently performed, the three fault signals are independently performed, and the three sampling signals correspond to the three fault signals one to one.

In addition, the programmable logic device 102 also detects a driving module fault feedback signal from the driving module 102, where the driving module fault feedback signal may include a UH (U-phase upper arm)/UL (U-phase lower arm) feedback fault signal of a U-phase, a VH (V-phase upper arm)/VL (V-phase lower arm) feedback fault signal of a V-phase, and a WH (W-phase upper arm)/WL (W-phase lower arm) feedback fault signal of a W-phase in the driving module. The UH/UL feedback fault signal indicates that a U-phase upper bridge arm or a U-phase lower bridge arm has a fault, the VH/VL feedback fault signal indicates that a V-phase upper bridge arm or a V-phase lower bridge arm in three-phase current has a fault, and the WH/WL feedback fault signal indicates that a W-phase upper bridge arm or a W-phase lower bridge arm in the three-phase current has a fault.

It can be understood that the UH/UL feedback fault signal, the VH/VL feedback fault signal, and the WH/WL feedback fault signal output by the driving module 102 are independent from each other, as well as the three-phase overcurrent fault signal, the bus voltage fault signal, and the driving module over-temperature fault signal, and as long as the programmable logic device 102 detects one of the fault signals, all of the 6 paths of PWM driving signals output by the control chip 105 are set to be at a low level, and the low level is output to the driving module 102, the driving module 102 is turned off, and the motor 103 stops operating.

Therefore, whether three-phase current overcurrent, bus voltage overvoltage and driving module faults occur in the motor control system or not can be detected rapidly in real time, and corresponding logic protection and the like can be carried out.

Further, according to an embodiment of the present invention, as shown in fig. 2 and fig. 6, the main control module 104 further includes: the rotation change decoding circuit 203, the rotation change decoding circuit 203 is connected with the control chip 105.

The resolver decoding circuit 203 is configured to decode the position signal of the motor 103, the decoding method may be a resolver detection technology, the resolver decoding circuit 203 decodes and then sends the position signal of the motor 103 to the control chip 105, and the control chip 105 may obtain the three-phase current of the motor 103 and generate and output a motor control signal, that is, a 6-way PWM driving signal according to the three-phase current of the motor 103 and the position signal of the motor 103.

That is, the resolver decoding circuit 203 decodes a position signal of the motor 103 and transmits the position signal to the control chip 105, and the control chip 105 generates a motor control signal, i.e., a 6-way PWM driving signal, by an internal control logic and algorithm according to the three-phase current of the motor 103 and the position signal of the motor 103 and outputs the motor control signal to the programmable logic device 106. The programmable logic device 106 determines whether to output a motor control signal sent by the control chip 105, i.e., a 6-way PWM drive signal, to the drive module 102 according to the received three-phase overcurrent fault signal, the bus voltage fault signal, the drive module overtemperature fault signal, the UH/UL feedback fault signal, the VH/VL feedback fault signal, and the WH/WL feedback fault signal.

According to an embodiment of the present invention, as shown in fig. 2 and fig. 6, the driving module 102 includes a driving and protecting circuit 204 and a power module 205, wherein the driving and protecting circuit 204 is connected to the programmable logic device 106, the power module 205 is respectively connected to the driving and protecting circuit 204 and the motor 103, and the power module 205 is further connected to a power source 601.

It is understood that the driver and protection circuit 204 may feed back a driver module failure feedback signal to the programmable logic device 106 when the driver module 102 fails. The drive module fault feedback signals may include UH/UL feedback fault signals, VH/VL feedback fault signals, and WH/WL feedback fault signals.

According to an embodiment of the present invention, the programmable logic device 106 includes a logic protection sub-module, and the logic protection sub-module is configured to perform a logic judgment on the received fault signal and determine whether a fault is detected according to a judgment result.

It should be noted that, in consideration of the fact that the electric vehicle has various and complicated driving conditions during the operation process, the logic protection sub-module may first perform debouncing processing on the fault signal, for example, debouncing processing for a duration of 0.2us may be performed on the fault signal, and perform logic judgment on the fault signal after the debouncing processing, so as to prevent misjudgment of the fault signal.

As an example, the fault signal may include a three-phase overcurrent fault signal, a bus voltage fault signal, a driving module over-temperature fault signal, and a fault feedback signal of the driving module, and a main control power supply and a reset signal input to the main control module.

More specifically, as shown in fig. 3, the logic protection submodule includes a first logic unit 303, a second logic unit 304, and a third logic unit 305.

The first logic unit 303 is configured to perform a logical or operation on the received fault signal, and set a fault flag when determining that a fault is detected according to any fault signal. Specifically, the fault signals may include a moving module over-temperature fault signal, a three-phase over-current fault signal, a bus voltage fault signal, a driving module over-temperature fault signal, a UH/UL feedback fault signal, a VH/VL feedback fault signal, and a WH/WL feedback fault signal, and the first logic unit 303 sets a fault flag when receiving one or more of the above fault signals.

The second logic unit 304 is configured to perform a logical and operation on the fault flag, the main control power supply input to the main control module 104, and the reset signal to determine a working state of the motor control system 101, where the working state of the motor control system includes a fault state, an idle state, and a normal operation state.

It should be noted that the master power supply and the reset signal input to the master control module 104 are subjected to a logical or operation before being subjected to a logical and operation with the fault flag, in other words, the master power supply and the reset signal are subjected to a logical or operation and then subjected to a logical and operation with the fault flag, so as to output the operating state of the motor control system 101.

The third logic unit 305 is configured to generate a motor control signal or a drive-off signal according to the operating state of the motor control system 101. Wherein in a normal operating state, a motor control signal is generated, and a drive shut-off signal is generated in a barrier state and an idle state.

Specifically, when the motor control system 101 is in a normal operation state, that is, the second logic unit 304 sends a signal indicating that the motor control system 101 is in a working state to the third logic unit 305, the third logic unit 305 generates a motor control signal, that is, a 6-way PWM driving signal output by the control chip 105 is directly output to the driving module 102, the driving module 102 is turned on, and the motor operates; when the motor control system 101 is in an idle state or a fault state, that is, when the second logic unit 304 sends a signal indicating that the motor control system 101 is in the idle state or the fault state to the third logic unit 305, the third logic unit 305 generates a drive shutdown signal, that is, outputs a low level to the drive module 102, and the drive module 102 is shut down, so that the motor stops operating.

It should be noted that, the programmable logic device 106 adopts Verilog HDL hardware description language for circuit design, and the third logic unit 305 may adopt case statement.

Further, the programmable logic device 106 also includes a communication sub-module. Wherein, the communication submodule performs SPI full duplex serial communication with the control chip 105. The communication sub-module and the control chip 105 adopt 16-bit effective data transmission, and the communication speed can be more than 1 Mbit/s.

Specifically, the communication submodule includes a chip selection terminal, a clock terminal, an output terminal and an input terminal, the chip selection terminal is used for receiving a chip selection signal SPI _ CS, the clock terminal is used for receiving a clock signal SPI _ CLK, the output terminal is used for sending an output signal SPI _ DO, and the input terminal is used for receiving an input signal SPI _ DI. Under the condition that the chip selection is effective, the input end and the output end of the communication submodule receive and send signals under the control of a clock signal SPI _ CLK at a clock end.

It is noted that, as shown in fig. 6, the programmable logic device 106 further includes a top event CPLD which declares references to various ports in the communication submodule through various buffers, including a transmit buffer (CPLD _ tbuff) and a receive buffer (CPLD _ rbuff).

Specifically, in order to prevent the chip select from misjudging the validity of the chip select signal SPI _ CS, the debounce process of 0.2us may be performed on the fault signal before the chip select. Under the condition that chip selection is effective, the input end and the output end of the communication submodule receive and transmit signals under the control of a clock signal SPI _ CLK at a clock end, namely when the rising edge of the clock signal SPI _ CLK comes, the numerical value in a transmitting buffer (CPLD _ tbuff) defined in the top event CPLD is assigned to the output end of the communication submodule, and the output end of the communication submodule starts to transmit data; when the falling edge of the clock signal SPI _ CLK comes, the signal received by the receiving end of the communication submodule is assigned to a receiving buffer (CPLD _ rbuff) defined in the CPLD, and the input end of the communication submodule begins to receive data.

As described above, with reference to fig. 4, the communication control method of the communication sub-module includes the steps of:

s401: and a chip selection end chip selection signal SPI _ CS.

S402: and under the condition that the chip selection is effective, the clock end controls the receiving and the sending of signals.

S403: when the rising edge of the clock signal SPI _ CLK comes, the value in the sending buffer (CPLD _ tbuff) defined inside the top event CPLD is assigned to the output of the communication submodule, i.e.: and the output end of the communication submodule starts to send data when the SPI _ DO < ═ CPLD _ Tbuff.

S404: when the falling edge of the clock signal SPI _ CLK comes, the signal received by the receiving end of the communication submodule is assigned to a receiving buffer (CPLD _ rbuff) defined inside the top event CPLD, that is: CPLD _ rbuff < ═ SPI _ DI, the input of the communication submodule starts accepting data.

According to the motor control system of the electric automobile, the fault detection is carried out on the motor control system through the programmable logic device, and the driving closing signal is output to the driving module when the fault is detected so as to close the driving module.

Based on the embodiment, the invention further provides an electric automobile.

Fig. 5 is a block diagram schematically illustrating an electric vehicle according to an embodiment of the present invention. As shown in fig. 5, the electric vehicle 501 includes a motor control system 101.

According to the electric automobile provided by the embodiment of the invention, the motor control system of the electric automobile can detect and protect the fault of the motor control system in real time and rapidly, and the safety and the reliability of the motor control system are improved.

In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above are not necessarily intended to refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.

Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing steps of a custom logic function or process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.

The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.

It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. If implemented in hardware, as in another embodiment, any one or combination of the following techniques, which are known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.

It will be understood by those skilled in the art that all or part of the steps carried by the method for implementing the above embodiments may be implemented by hardware related to instructions of a program, which may be stored in a computer readable storage medium, and when the program is executed, the program includes one or a combination of the steps of the method embodiments.

In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.

The storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.