阅读说明：本技术 一种应用于热电能量获取的多模式boost转换器 (Multi-mode BOOST converter applied to thermoelectric energy acquisition ) 是由 刘帘曦 邢奕赫 黄超进 田宇渊 朱樟明 于 2019-09-29 设计创作，主要内容包括：本发明公开了一种应用于热电能量获取的多模式BOOST转换器,包括：热电发电机TEG(1)；BOOST功率级子电路(2),电连接所述热电发电机TEG(1)；检测子电路(3),电连接所述BOOST功率级子电路(2)；采样及模式选择子电路(4),电连接所述BOOST功率级子电路(2)；最大功率点追踪子电路(5),电连接所述BOOST功率级子电路(2)；逻辑与栅极驱动子电路(6),电连接所述采样及模式选择子电路(4)、所述检测子电路(3)、所述最大功率点追踪子电路(5)以及所述BOOST功率级子电路(2)。本发明提供的多模式BOOST转换器,采用非连续导通模式、临界导通模式、连续导通模式三种工作模式混合的方式,根据不同的输入电压选择适合的工作模式,最大程度的减小了电路损耗,提升了转换效率。(The invention discloses a multi-mode BOOST converter applied to thermoelectric energy acquisition, which comprises: a thermoelectric generator TEG (1); a BOOST power stage sub-circuit (2) electrically connected to the thermoelectric generator TEG (1); a detection sub-circuit (3) electrically connected to the BOOST power stage sub-circuit (2); a sampling and mode selection sub-circuit (4) electrically connected to the BOOST power stage sub-circuit (2); a maximum power point tracking sub-circuit (5) electrically connected to the BOOST power stage sub-circuit (2); a logic and gate drive sub-circuit (6) electrically connecting the sampling and mode selection sub-circuit (4), the detection sub-circuit (3), the maximum power point tracking sub-circuit (5) and the BOOST power stage sub-circuit (2). The multi-mode BOOST converter provided by the invention adopts a mode of mixing three working modes of a discontinuous conduction mode, a critical conduction mode and a continuous conduction mode, and selects a proper working mode according to different input voltages, thereby reducing the circuit loss to the greatest extent and improving the conversion efficiency.)

1. A multi-mode BOOST converter for thermoelectric energy harvesting, comprising:

a thermoelectric generator TEG (1) for converting thermal energy into a first electrical signal;

the BOOST power level sub-circuit (2) is electrically connected with the thermoelectric generator TEG (1) and is used for processing the first electric signal to obtain a second electric signal;

the detection sub-circuit (3) is electrically connected with the BOOST power level sub-circuit (2) and is used for detecting the second electric signal to obtain a third electric signal;

the sampling and mode selection sub-circuit (4) is electrically connected with the BOOST power level sub-circuit (2) and is used for generating a fourth electric signal according to the open-circuit voltage;

the maximum power point tracking sub-circuit (5) is electrically connected with the BOOST power level sub-circuit (2) and is used for generating a fifth electric signal according to the open-circuit voltage and the real-time voltage;

and the logic and grid electrode driving sub-circuit (6) is electrically connected with the sampling and mode selecting sub-circuit (4), the detecting sub-circuit (3), the maximum power point tracking sub-circuit (5) and the BOOST power level sub-circuit (2) and is used for selecting different modes according to the fourth electric signal and generating a first logic signal according to the third electric signal and the fifth electric signal so as to control the BOOST power level sub-circuit (2) to process the first electric signal.

2. According to the rightA multi-mode BOOST converter according to claim 1, characterized in that said BOOST power stage sub-circuit (2) comprises: input capacitance (C)_IN) An inductor (L), a first NMOS transistor (M)_N1) A first PMOS transistor (M)_P1) Load capacitance (C)_L) A first diode (D)₁) A second diode (D)₂) (ii) a Wherein the content of the first and second substances,

the first diode (D)₁) And the second diode (D)₂) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;

the load capacitance (C)_L) Is connected between a power supply end (VDD) and a ground end (GND) in series;

the first PMOS tube (M)_P1) The inductor (L) and the thermoelectric generator TEG (1) are sequentially connected in series between a power supply end (VDD) and a ground end (GND);

the input capacitance (C)_IN) A node (V) formed by the inductor (L) and the thermoelectric generator (TEG) in series connection_IN) And the ground terminal (GND);

the first NMOS transistor (M)_N1) Is connected in series with the first PMOS tube (M)_P1) A node (SW) end formed by connecting the inductor (L) in series is connected between a ground end (GND);

the first PMOS tube (M)_P1) The grid is electrically connected with the output end of the logic and grid driving sub-circuit;

the first NMOS transistor (M)_N1) The grid is electrically connected with the output end of the logic and grid driving sub-circuit (6).

3. A multi-mode BOOST converter according to claim 2, characterized in that said detection sub-circuit (4) comprises: a first switch (S1), a second switch (S2), a first resistor (R1), a first comparator (COMP 1); wherein the content of the first and second substances,

the first switch (S1) is connected in series between a node (SW) terminal of the BOOST power stage sub-circuit and a positive input terminal of the first comparator (COMP 1);

the second switch (S2) and the first resistor (R1) are sequentially connected in series between the SW end of the BOOST power stage sub-circuit and the positive input end of the first comparator (COMP 1);

the reverse input end of the first comparator (COMP1) is electrically connected with a power supply end (VDD), and the output end of the first comparator is electrically connected with the input end of the logic and gate drive sub-circuit (6).

4. A multi-mode BOOST converter according to claim 1, characterized in that said maximum power point tracking sub-circuit (5) comprises: discontinuous conduction mode conduction time control circuit (T)_{ON_DCM}Control), a voltage division circuit (51), a second Comparator (COMP)₂) 5BIT counter (5BIT), discontinuous conduction mode cycle length control circuit (T)_{SW_DCM}Control), critical conduction mode and continuous conduction mode conduction time Control circuit (T)_{ON_CRM&CCM}Control); wherein the content of the first and second substances,

the voltage dividing circuit (51) and the second Comparator (COMP)₂) Are sequentially connected in series with a node (V) formed by connecting the inductor (L) and the thermoelectric generator TEG (1) in series_IN) And said 5-BIT counter (5 BIT);

the 5-BIT counter (5BIT) is respectively electrically connected with the discontinuous conduction mode period length control circuit (T)_{SW_DCM}Control) and the critical conduction mode and continuous conduction mode conduction time Control circuit (T)_{ON_CRM&CCM}Control)；

The discontinuous conduction mode period length control circuit (T)_{SW_DCM}Control) and a critical conduction mode and continuous conduction mode conduction time Control circuit (T)_{ON_CRM&CCM}Control) output end is respectively and electrically connected with the input end of the logic and grid driving sub-circuit (6);

said discontinuous conduction mode conduction time control circuit (T)_{ON_DCM}Control) connected in series to the open-circuit voltage (V) of the thermoelectric generator_S) And the logic and gate drive sub-circuit input terminal.

5. Multi-mode BOOST converter according to claim 4, characterized in that said discontinuous conduction mode conduction time control circuit (T)_{ON_DCM}Control) includes: operational Amplifier (OA), third NMOS transistor (M)_N3) The first stepFour NMOS tubes (M)_N4) And the fifth NMOS transistor (M)_N5) And a second PMOS transistor (M)_P2) And the third PMOS tube (M)_P3) And the fourth PMOS tube (M)_P4) And the fifth PMOS tube (M)_P5) A second resistor (R)₂) A first capacitor (C)₁) A third Comparator (COMP)₃) (ii) a Wherein the content of the first and second substances,

the positive input of the Operational Amplifier (OA) is electrically connected to the open-circuit voltage (V) of the thermoelectric generator TEG (1)_S) And the reverse input end is electrically connected with the third NMOS tube (M)_N3) And the second resistance (R)₂) A node formed by series connection, and the output end is electrically connected with the third NMOS tube (M)_N3) A gate electrode of (1);

the fourth PMOS tube (M)_P4) The second PMOS tube (M)_P2) The third NMOS tube (M)_N3) And the second resistor (R)₂) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;

the fifth PMOS tube (M)_P5) The third PMOS tube (M)_P3) And the fourth NMOS transistor (M)_N4) And the fifth NMOS transistor (M)_N5) Are connected in series between a power supply terminal (VDD) and a ground terminal (GND) in sequence;

the first capacitor (C)₁) Is connected in series with the third PMOS tube (M)_P3) And the fifth NMOS transistor (M)_P5) Between the node formed by series connection and the grounding end (GND);

the third PMOS tube (M)_P3) And said first capacitance (C)₁) Nodes formed in series_c1) Electrically connecting the third Comparator (COMP)₃) The inverting input terminal of (1);

said third Comparator (COMP)₃) Is electrically connected to the reference voltage terminal (V)_REF) The output end of the logic and grid drive sub-circuit is electrically connected with the input end of the logic and grid drive sub-circuit;

the second PMOS tube (M)_P2) Is electrically connected with the third NMOS tube (M)_N3) A drain electrode of (1);

the fourth PMOS tube (M)_P4) Is electrically connected with the second PMOS tube (M)_P2) A source electrode of (a);

the second PMOS tube (M)_P2) Is electrically connected with the third PMOS tube (M)_P3) A gate electrode of (1);

the fourth PMOS tube (M)_P4) Is electrically connected with the fifth PMOS tube (M)_P5) A gate electrode of (1);

the fourth NMOS transistor (M)_N4) Is electrically connected with the enable terminal (VEN);

the fifth NMOS transistor (M)_N5) Is electrically connected to the output of the logic and gate drive sub-circuit (6).

6. A multi-mode BOOST converter as claimed in claim 4, characterized in that the voltage dividing circuit (51) comprises: third switch (S)₃) And a fourth switch (S)₄) And a fifth switch (S)₅) A second capacitor (C)₂) A third capacitor (C)₃) (ii) a Wherein the content of the first and second substances,

the third switch (S)₃) Connected in series to said second Comparator (COMP)₂) Between the forward input end and the reverse input end;

the second capacitance (C)₂) Connected in series to said second Comparator (COMP)₂) Between the inverting input terminal and the ground terminal (GND);

the fourth switch (S)₄) And said third capacitance (C)₃) Are sequentially connected in series to the second Comparator (COMP)₂) Between the inverting input terminal and the ground terminal (GND);

the fifth switch (S)₅) Is connected in series to the fourth switch (S)₄) And said third capacitance (C)₃) The nodes formed by the series connection are connected with a ground terminal (GND).

7. Multi-mode BOOST converter according to claim 4, characterized in that said discontinuous conduction mode period length control circuit (Tp)_{SW_DCM}Control) includes: sixth NMOS transistor (M)_N6) And the seventh NMOS transistor (M)_N7) And the eighth NMOS transistor (M)_N8) And the ninth NMOS tube (M)_N9) And the tenth NMOS transistor (M)_N10) And the eleventh NMOS tube (M)_N11) And the sixth PMOS tube (M)_P6) And the seventh PMOS tube (M)_P7) And the eighth PMOS tube (M)_P8) Ninth, ninthPMOS tube (M)_P9) Tenth PMOS tube (M)_P10) And a sixth switch group (S)_6i) And a seventh switch group (S)_7i) And the eighth switch group (S)_8i) And a ninth switch group (S)_9i) And a tenth switch group (S)_10i) And a fourth capacitor group (C)_4i) And a fifth capacitor group (C)_5i) And a sixth capacitor group (C)_6i) And a seventh capacitor bank (C)_7i) And an eighth capacitor bank (C)_8i) And a ninth capacitor bank (C)_9i) I is 1,2, 3; wherein the content of the first and second substances,

the sixth NMOS transistor (M)_N6) Connected in series to a bias current (I)_bias) And the ground terminal (GND);

the sixth PMOS tube (M)_P6) And the seventh NMOS transistor (M)_N7) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;

the seventh PMOS tube (M)_P7) And the eighth NMOS transistor (M)_N8) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;

the eighth PMOS tube (M)_P8) And the ninth NMOS transistor (M)_N9) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;

the ninth PMOS tube (M)_P9) And the tenth NMOS transistor (M)_N10) Are sequentially connected between a power supply end (VDD) and a ground end (GND) in series;

the tenth PMOS tube (M)_P10) And the eleventh NMOS transistor (M)_N11) Sequentially connected in series between a power supply terminal (VDD) and a ground terminal (GND), with a common terminal thereof as an output terminal V_TSWConnecting the logic and gate drive subcircuit (6);

the seventh NMOS transistor (M)_N7) Is electrically connected with the sixth NMOS tube (M)_N6) A gate and a drain;

the seventh PMOS tube (M)_P7) The eighth PMOS tube (M)_P8) The ninth PMOS tube (M)_P9) The tenth PMOS tube (M)_P10) The grid electrodes of the first and second PMOS tubes are respectively and electrically connected with the sixth PMOS tube (M)_P6) A gate and a drain;

the ninth NMOS transistor (M)_N9) Is electrically connected with the eighth NMOS tube (M)_N8) The drain electrode forms a node (V)_C1)；

The tenth NMOS transistor (M)_N10) Is electrically connected with the ninth NMOS tube (M)_N9) The drain electrode forms a node (V)_C2)；

The eighth NMOS transistor (M)_N8) Is electrically connected with the eleventh NMOS tube (M)_N11) Is electrically connected with the tenth NMOS tube (M)_N10) The drain electrode forms a node (V)_C3)；

The fourth capacitor bank (C)_4i) Connected in series to a node V_Ci(i ═ 1,2,3) and Ground (GND);

the sixth switch group (S)_6i) And the fifth capacitor bank (C)_5i) Are sequentially connected in series with a node V_Ci(i ═ 1,2,3) and Ground (GND);

the seventh switch group (S)_7i) And the sixth capacitor bank (C)_6i) Are sequentially connected in series with a node V_Ci(i ═ 1,2,3) and Ground (GND);

the eighth switch group (S)_8i) And the seventh capacitor bank (C)_7i) Are sequentially connected in series with a node V_Ci(i ═ 1,2,3) and Ground (GND);

the ninth switch group (S)_9i) And the eighth capacitor bank (C)_8i) Are sequentially connected in series with a node V_Ci(i ═ 1,2,3) and Ground (GND);

the tenth switch group (S)_10i) And the ninth capacitor bank (C)_9i) Are sequentially connected in series with a node V_Ci(i ═ 1,2,3) and Ground (GND).

8. A multi-mode BOOST converter according to claim 4, characterized in that said critical conduction mode and continuous conduction mode conduction time control circuit (T)_{ON_CRM&CCM}Control) includes: bias current source (I)_bias) Inverter (INV) and twelfth NMOS transistor (M)_N12) Thirteenth NMOS transistor (M)_N13) And an eleventh switch (S)₁₁) And a twelfth switch (S)₁₂) And a thirteenth switch (S)₁₃) And a fourteenth switch (S)₁₄) And a fifteenth switch (S)₁₅) A tenth capacitor (C)₁₀) The first stepEleven capacitors (C)₁₁) A twelfth capacitor (C)₁₂) A thirteenth capacitor (C)₁₃) A fourteenth capacitor (C)₁₄) A fifteenth capacitor (C)₁₅) A fourth Comparator (COMP)₄) (ii) a Wherein the content of the first and second substances,

the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) And the thirteenth NMOS tube (M)_N13) Are connected in series between a power supply terminal (VDD) and a ground terminal (GND) in sequence;

the tenth capacitance (C)₁₀) Is connected in series to the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) Between the node formed by series connection and the grounding end (GND);

the eleventh switch (S)₁₁) And the eleventh capacitance (C)₁₁) Are sequentially connected in series with the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) Between the node formed by series connection and the grounding end (GND);

the twelfth switch (S)₁₂) And the twelfth capacitance (C)₁₂) Are sequentially connected in series with the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) Between the node formed by series connection and the grounding end (GND);

the thirteenth switch (S)₁₃) And the thirteenth capacitor (C)₁₃) Are sequentially connected in series with the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) Between the node formed by series connection and the grounding end (GND);

the fourteenth switch (S)₁₄) And the fourteenth capacitance (C)₁₄) Are sequentially connected in series with the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) Between the node formed by series connection and the grounding end (GND);

the fifteenth switch (S)₁₅) And the fifteenth capacitance (C)₁₅) Are sequentially connected in series with the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) Between the node formed by series connection and the grounding end (GND);

said fourth Comparator (COMP)₄) The positive input end is electrically connected with a reference voltage end (V)_REF) Output in opposite phaseThe input end is electrically connected with the bias current source (I)_bias) And the twelfth NMOS tube (M)_N12) The output end of the node is electrically connected with the input end of the logic and grid electrode driving sub-circuit (6);

the Inverter (INV) is connected in series to an enable terminal (VEN) and the twelfth NMOS tube (M)_N12) Between the grids;

the thirteenth NMOS transistor (M)_N13) The grid is electrically connected with the output end of the logic and grid driving sub-circuit (5).

9. The multi-mode BOOST converter according to claim 1, wherein said sampling and mode selection sub-circuit comprises: fifth Comparator (COMP)₅) And a sixth Comparator (COMP)₆) (ii) a Wherein the content of the first and second substances,

said fifth Comparator (COMP)₅) The inverting input terminals are respectively electrically connected with the sixth Comparator (COMP)₆) A node (V) formed by connecting the positive input end with the inductor (L) and the thermoelectric generator TEG (1) in series_IN)；

Said fifth Comparator (COMP)₅) The positive input end is electrically connected with a first reference voltage end (V)_REF1)；

Said sixth Comparator (COMP)₆) The reverse input terminal is electrically connected with the second reference voltage terminal (V)_REF2)；

Said fifth Comparator (COMP)₅) And said sixth Comparator (COMP)₆) The output ends are respectively and electrically connected with the input ends of the logic and grid electrode driving sub-circuits (6).

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a multi-mode BOOST converter applied to thermoelectric energy acquisition.

Background

In the fields of ultra-low power wireless sensor networks (WBANs), portable devices, and the like, the environmental energy acquisition circuits are increasingly widely applied, and can provide power supply voltage to supply power to a subsequent load circuit. There are many types of environmental energy available, such as radio frequency energy, piezoelectric energy, photovoltaic energy, and thermal energy, among which the thermal energy density is relatively stable and large, and is well suited for wearable applications. Thermoelectric generators (TEG) are commonly used to convert thermal energy into electrical voltage in thermal energy collection. When the ambient temperature difference is low, the open circuit voltage taken by a thermoelectric generator (TEG) may be as low as tens of millivolts. Therefore, for thermoelectric energy harvesting, the key technology is the design of the TEG interface circuit, i.e. the BOOST (BOOST) converter, which needs to BOOST voltages as low as tens of millivolts above 1V.

Currently, the BOOST converter mainly has three predetermined operation modes, which are a discontinuous conduction mode, a critical conduction mode and a continuous conduction mode.

However, the conventional BOOST converter can only perform voltage conversion in a predetermined operation mode during operation, and cannot adjust the operation mode in good time when the input voltage range is large, so that the conversion efficiency is low and the circuit loss is large.

Disclosure of Invention

In order to solve the above problems in the prior art, the present invention provides a multi-mode BOOST converter applied to thermoelectric energy harvesting. The technical problem to be solved by the invention is realized by the following technical scheme:

a multi-mode BOOST converter for thermoelectric energy harvesting, comprising:

a thermoelectric generator TEG for converting thermal energy into a first electrical signal;

the BOOST power level sub-circuit is electrically connected with the thermoelectric generator TEG and is used for processing the first electric signal to obtain a second electric signal;

the detection sub-circuit is electrically connected with the BOOST power level sub-circuit and is used for detecting the second electric signal to obtain a third electric signal;

the sampling and mode selection sub-circuit is electrically connected with the BOOST power level sub-circuit and is used for generating a fourth electric signal according to the open-circuit voltage;

the maximum power point tracking sub-circuit is electrically connected with the BOOST power level sub-circuit and is used for generating a fifth electric signal according to the open-circuit voltage and the real-time voltage;

and the logic and grid electrode driving sub-circuit is electrically connected with the sampling and mode selecting sub-circuit, the detecting sub-circuit, the maximum power point tracking sub-circuit and the BOOST power level sub-circuit and is used for selecting different modes according to the fourth electric signal and generating a first logic signal according to the third electric signal and the fifth electric signal so as to control the BOOST power level sub-circuit to process the first electric signal.

In one embodiment of the present invention, the BOOST power stage sub-circuit includes: input capacitance C_INInductor L, first NMOS tube M_N1The first PMOS transistor M_P1A load capacitor C_LA first diode D₁A second diode D₂(ii) a Wherein the content of the first and second substances,

the first diode D₁And the second diode D₂Are sequentially connected between a power supply end VDD and a ground end GND in series;

the load capacitor C_LIs connected between a power supply end VDD and a ground end GND in series;

the first PMOS tube M_P1The inductor L and the thermoelectric generator TEG1 are sequentially connected in series between a power supply end VDD and a ground end GND;

the input capacitor C_INA node V formed by connecting the inductor L and the thermoelectric generator TEG in series_INAnd the ground end GND;

the first NMOS tube M_N1Is connected in series with the first PMOS tube M_P1A node SW end formed by connecting the inductor L in series is connected between the ground end GND;

the first PMOS tube M_P1The grid is electrically connected with the output end of the logic and grid driving sub-circuit;

the first NMOS tube M_N1The gate is electrically connected to the logic and gate drive sub-circuit 6.

In one embodiment of the invention, the detection sub-circuit 4 comprises: a first switch S1, a second switch S2, a first resistor R1, a first comparator COMP 1; wherein the content of the first and second substances,

the first switch S1 is connected in series between the node SW terminal of the BOOST power stage sub-circuit and the positive input terminal of the first comparator COMP 1;

the second switch S2 and the first resistor R1 are sequentially connected in series between the SW terminal of the BOOST power stage sub-circuit and the positive input terminal of the first comparator COMP 1;

the reverse input end of the first comparator COMP1 is electrically connected with a power supply end VDD, and the output end is electrically connected with the input end of the logic and gate driving sub-circuit.

In one embodiment of the present invention, the maximum power point tracking sub-circuit comprises: discontinuous conduction mode conduction time control circuit T_{ON_DCM}Control, voltage division circuit and second comparator COMP₂5BIT counter 5BIT, discontinuous conduction mode period length control circuit T_{SW_DCM}Control, critical conduction mode and continuous conduction mode conduction time Control circuit T_{ON_CRM&CCM}Control; wherein the voltage dividing circuit and the second comparator COMP₂Is sequentially connected in series with a node V formed by connecting the inductor L and the thermoelectric generator TEG1 in series_INAnd the 5-BIT counter 5 BIT;

the 5-BIT counter 5BIT is respectively and electrically connected with the discontinuous conduction mode period length control circuit T_{SW_DCM}Control and critical conduction mode and continuous conduction mode conduction time Control circuit T_{ON_CRM&CCM}Control；

The discontinuous conduction mode period length control circuit T_{SW_DCM}Control and critical conduction mode and continuous conduction mode conduction time Control circuit T_{ON_CRM&CCM}The output end of the Control is respectively and electrically connected with the input end of the logic and grid electrode driving sub-circuit;

the discontinuous conduction mode conduction time control circuit T_{ON_DCM}Control is connected in series with the open-circuit voltage V of the thermoelectric generator_SAnd the logicBetween the gate driver sub-circuit input.

In an embodiment of the present invention, the discontinuous conduction mode conduction time control circuit T_{ON_DCM}The Control includes: operational amplifier OA, third NMOS tube M_N3And the fourth NMOS tube M_N4The fifth NMOS transistor M_N5A second PMOS transistor M_P2And the third PMOS transistor M_P3And the fourth PMOS transistor M_P4The fifth PMOS transistor M_P5A second resistor R₂A first capacitor C₁A third comparator COMP₃(ii) a Wherein the content of the first and second substances,

the positive input of the operational amplifier OA is electrically connected to the open-circuit voltage V of the thermoelectric generator TEG1_SThe reverse input end is electrically connected with the third NMOS tube M_N3And the second resistor R₂The output end of the node formed by serial connection is electrically connected with the third NMOS tube M_N3A gate electrode of (1);

the fourth PMOS tube M_P4The second PMOS tube M_P2The third NMOS tube M_N3And the second resistor R₂Are sequentially connected between a power supply end VDD and a ground end GND in series;

the fifth PMOS tube M_P5The third PMOS tube M_P3And the fourth NMOS tube M_N4And the fifth NMOS tube M_N5Are connected in series between a power supply end VDD and a ground end GND in sequence;

the first capacitor C₁Is connected in series with the third PMOS tube M_P3And the fifth NMOS tube M_P5The nodes formed by the serial connection are connected with a ground end GND;

the third PMOS tube M_P3And the first capacitor C₁Node formed by concatenation _c1 electrically connecting said third comparator COMP₃The inverting input terminal of (1);

the third comparator COMP₃Is electrically connected with a reference voltage end V_REFThe output end of the logic and grid drive sub-circuit is electrically connected with the input end of the logic and grid drive sub-circuit;

the second PMOS tube M_P2The grid electrode of the NMOS transistor is electrically connected with the third NMOS transistor M_N3A drain electrode of (1);

the fourth PMOS tube M_P4The grid electrode of the second PMOS tube M is electrically connected with the second PMOS tube M_P2A source electrode of (a);

the second PMOS tube M_P2The grid electrode of the PMOS transistor is electrically connected with the third PMOS transistor M_P3A gate electrode of (1);

the fourth PMOS tube M_P4The grid electrode of the PMOS transistor is electrically connected with the fifth PMOS transistor M_P5A gate electrode of (1);

the fourth NMOS tube M_N4The grid of the grid is electrically connected with an enabling end VEN;

the fifth NMOS tube M_N5The gate of the logic and gate drive sub-circuit is electrically connected with the output end of the logic and gate drive sub-circuit.

In one embodiment of the present invention, the voltage dividing circuit 51 includes: third switch S₃And a fourth switch S₄The fifth switch S₅A second capacitor C₂A third capacitor C₃(ii) a Wherein the content of the first and second substances,

the third switch S₃Connected in series to said second comparator COMP₂Between the forward input end and the reverse input end;

the second capacitor C₂Connected in series to said second comparator COMP₂Between the inverting input terminal and the ground terminal GND;

the fourth switch S₄And the third capacitor C₃Are sequentially connected in series with the second comparator COMP₂Between the inverting input terminal and the ground terminal GND;

the fifth switch S₅Is connected in series with the fourth switch S₄And the third capacitor C₃The nodes formed by the series connection are connected with the ground terminal GND.

In an embodiment of the present invention, the discontinuous conduction mode period length control circuit T_{SW_DCM}The Control includes: sixth NMOS transistor M_N6And a seventh NMOS transistor M_N7And the eighth NMOS transistor M_N8And a ninth NMOS transistor M_N9The tenth NMOS transistor M_N10Eleventh NMOS transistor M_N11Sixth PMOS transistor M_P6Seventh PMOS transistor M_P7Eighth PMOS transistor M_P8Ninth PMOS transistor M_P9Tenth PMOS transistor M_P10And a sixth switch group S_6iAnd a seventh switch group S_7iThe eighth switch group S_8iAnd a ninth switch group S_9iThe tenth switch group S_10iAnd a fourth capacitor group C_4iThe fifth capacitor group C_5iAnd a sixth capacitor group C_6iAnd a seventh capacitor group C_7iAnd the eighth capacitor bank C_8iAnd a ninth capacitor bank C_9iI is 1,2, 3; wherein the content of the first and second substances,

the sixth NMOS tube M_N6Connected in series to a bias current I_biasAnd the ground end GND;

the sixth PMOS tube M_P6And the seventh NMOS tube M_N7Are sequentially connected between a power supply end VDD and a ground end GND in series;

the seventh PMOS tube M_P7And the eighth NMOS tube M_N8Are sequentially connected between a power supply end VDD and a ground end GND in series;

the eighth PMOS tube M_P8And the ninth NMOS tube M_N9Are sequentially connected between a power supply end VDD and a ground end GND in series;

the ninth PMOS tube M_P9And the tenth NMOS transistor M_N10Are sequentially connected between a power supply end VDD and a ground end GND in series;

the tenth PMOS tube M_P10And the eleventh NMOS tube M_N11Sequentially connected between a power supply terminal VDD and a ground terminal GND in series, and a common terminal thereof is used as an output terminal V_TSWConnecting the logic and gate drive subcircuit 6;

the seventh NMOS tube M_N7The grid electrode of the NMOS transistor is electrically connected with the sixth NMOS transistor M_N6A gate and a drain;

the seventh PMOS tube M_P7The eighth PMOS tube M_P8The ninth PMOS transistor M_P9The tenth PMOS tube M_P10The grid electrodes of the PMOS tubes are respectively and electrically connected with the sixth PMOS tube M_P6A gate and a drain;

the ninth NMOS tube M_N9Is electrically connected with the eighth NMOS tube M_N8The drain forms a node V_C1；

The tenth NMOS transistor M_N10The grid electrode of the NMOS transistor is electrically connected with the ninth NMOS transistorM_N9The drain forms a node V_C2；

The eighth NMOS tube M_N8The grid of the NMOS transistor is electrically connected with the eleventh NMOS transistor M_N11Is electrically connected with the tenth NMOS tube M_N10The drain forms a node V_C3；

The fourth capacitor bank C_4iConnected in series to a node V_Cii is between 1,2,3 and the ground end GND;

the sixth switch group S_6iAnd the fifth capacitor group C_5iAre sequentially connected in series with a node V_Ci(i ═ 1,2,3) to ground GND;

the seventh switch group S_7iAnd the sixth capacitor group C_6iAre sequentially connected in series with a node V_Ci(i ═ 1,2,3) to ground GND;

the eighth switch group S_8iAnd the seventh capacitor bank C_7iAre sequentially connected in series with a node V_Ci(i ═ 1,2,3) to ground GND;

the ninth switch group S_9iAnd the eighth capacitor bank C_8iAre sequentially connected in series with a node V_Ci(i ═ 1,2,3) to ground GND;

the tenth switch group S_10iAnd the ninth capacitor bank C_9iAre sequentially connected in series with a node V_Ci( i 1,2,3) to ground GND.

In an embodiment of the present invention, the critical conduction mode and continuous conduction mode conduction time control circuit T_{ON_CRM&CCM}The Control includes: bias current source I_biasInverter INV and twelfth NMOS transistor M_N12Thirteenth NMOS transistor M_N13The eleventh switch S₁₁And a twelfth switch S₁₂And a thirteenth switch S₁₃And a fourteenth switch S₁₄The fifteenth switch S₁₅A tenth capacitor C₁₀An eleventh capacitor C₁₁And a twelfth capacitor C₁₂A thirteenth capacitor C₁₃And a fourteenth capacitor C₁₄A fifteenth capacitor C₁₅A fourth comparator COMP₄(ii) a Wherein the content of the first and second substances,

the bias current source I_biasAnd the twelfth NMOS tube M_N12And the thirteenth NMOS tube M_N13Are connected in series between a power supply end VDD and a ground end GND in sequence;

the tenth capacitor C₁₀Is connected in series with the bias current source I_biasAnd the twelfth NMOS tube M_N12The nodes formed by the serial connection are connected with a ground end GND;

the eleventh switch S₁₁And the eleventh capacitor C₁₁Are sequentially connected in series with the bias current source I_biasAnd the twelfth NMOS tube M_N12The nodes formed by the serial connection are connected with a ground end GND;

the twelfth switch S₁₂And the twelfth capacitor C₁₂Are sequentially connected in series with the bias current source I_biasAnd the twelfth NMOS tube M_N12The nodes formed by the serial connection are connected with a ground end GND;

the thirteenth switch S₁₃And the thirteenth capacitor C₁₃Are sequentially connected in series with the bias current source I_biasAnd the twelfth NMOS tube M_N12The nodes formed by the serial connection are connected with a ground end GND;

the fourteenth switch S₁₄And the fourteenth capacitance C₁₄Are sequentially connected in series with the bias current source I_biasAnd the twelfth NMOS tube M_N12The nodes formed by the serial connection are connected with a ground end GND;

the fifteenth switch S₁₅And the fifteenth capacitor C₁₅Are sequentially connected in series with the bias current source I_biasAnd the twelfth NMOS tube M_N12The nodes formed by the serial connection are connected with a ground end GND;

the fourth comparator COMP₄The positive input end is electrically connected with a reference voltage end V_REFThe reverse phase input end is electrically connected with the bias current source I_biasAnd the twelfth NMOS tube M_N12The output end of the node is electrically connected with the input end of the logic and grid electrode driving sub-circuit;

the inverter INV is connected in series with the enable terminal VEN and the twelfth NMOS tube M_N12Between the grids;

the thirteenth NMOS tube M_N13The gate is electrically connected to the output of the logic and gate drive sub-circuit 5.

In one embodiment of the present invention, the sampling and mode selection sub-circuit comprises: fifth comparator COMP₅And a sixth comparator COMP₆(ii) a Wherein the content of the first and second substances,

the fifth comparator COMP₅The inverting input ends of the first and second comparators are respectively electrically connected to the sixth comparator COMP₆A node V formed by connecting the positive input end with the inductor L and the thermoelectric generator TEG in series_IN；

The fifth comparator COMP₅The positive input end is electrically connected with a first reference voltage end V_REF1；

The sixth comparator COMP₆The reverse input end is electrically connected with a second reference voltage end V_REF2；

The fifth comparator COMP₅And said sixth comparator COMP₆The output ends are respectively and electrically connected with the input ends of the logic and grid electrode driving sub-circuits.

The invention has the beneficial effects that:

1. the multi-mode BOOST converter applied to thermoelectric energy acquisition provided by the invention adopts a mode of mixing three working modes of a discontinuous conduction mode, a critical conduction mode and a continuous conduction mode, wherein the discontinuous conduction mode with the minimum switching loss is adopted when the ultralow input voltage is 10mV to 40mV, the critical conduction mode is adopted for transition when the input voltage is 40mV to 100mV, and the continuous conduction mode with the minimum conduction loss is adopted when the input voltage is 100mV to 500mV, so that the circuit loss is reduced to the maximum extent, and the conversion efficiency is improved;

2. the multi-mode BOOST converter provided by the invention adopts the designed high-precision offset calibration comparator to replace a traditional zero-crossing comparator, so that the robustness of the circuit is improved;

3. the multi-mode BOOST converter provided by the invention can multiplex the offset calibration comparator in different working modes, thereby reducing the circuit scale and complexity;

4. the multi-mode BOOST converter provided by the invention is used in all working modesThe maximum power point tracking efficiency can reach 95%, and the peak efficiency under the continuous conduction mode is 92.7% (V)_S280mV), the efficiency can reach 32.8% when the discontinuous conduction mode is input with 10 mV.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

FIG. 1 is a schematic diagram of a multi-mode BOOST converter applied to thermoelectric energy harvesting according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of another structure of a multi-mode BOOST converter applied to thermoelectric energy harvesting according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a detection sub-circuit according to an embodiment of the present invention;

fig. 4 is a schematic structural diagram of a maximum power point tracking sub-circuit according to an embodiment of the present invention;

FIG. 5 is a discontinuous conduction mode conduction time control circuit T according to an embodiment of the present invention_{ON_DCM}A schematic of the structure of Control;

FIG. 6 shows a discontinuous conduction mode cycle length control circuit T according to an embodiment of the present invention_{SW_DCM}A schematic of the structure of Control;

FIG. 7 is a diagram of a critical conduction mode and continuous conduction mode conduction time control circuit T according to an embodiment of the present invention_{ON_CRM&CCM}A schematic of the structure of Control;

FIG. 8 is a waveform diagram illustrating a continuous conduction mode simulation according to an embodiment of the present invention;

fig. 9 is a discontinuous conduction mode simulation waveform diagram according to an embodiment of the present invention.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.