阅读说明：本技术 具有屏蔽干扰功能的电容信号检测电路 (Capacitance signal detection circuit with interference shielding function ) 是由 方毅 查华明 张艺耀 于 2019-10-25 设计创作，主要内容包括：本公开涉及一种具有屏蔽干扰功能的电容信号检测电路,该电容信号检测电路包括运算放大器、电容信号转换电路、分频器、第一电容、第二电容和第三电容,运算放大器的第2引脚与运算放大器的第6引脚连通,第6引脚还连接于第一电容一端,第一电容另一端接地,第6引脚还用于与探极电容连接,运算放大器的第3引脚连接于第二电容一端,第二电容另一端接地,第3引脚还连接于探极电容；电容信号转换电路连接于运算放大器的第3引脚；分频器的第16引脚连接于电源以及第三电容的一端,第三电容的另一端接地,分频器的第11引脚连接于电容信号转换电路,以接收电容信号转换电路传输的脉冲信号,并通过分频器的第13引脚将脉冲信号输出。(The utility model relates to a capacitance signal detection circuit with interference shielding function, this capacitance signal detection circuit includes operational amplifier, capacitance signal conversion circuit, frequency divider, first electric capacity, second electric capacity and third electric capacity, operational amplifier's 2 nd pin and operational amplifier's 6 th pin intercommunication, the 6 th pin still connects to first electric capacity one end, the first electric capacity other end ground connection, the 6 th pin still is used for being connected with the probe capacitor, operational amplifier's 3 rd pin is connected to second electric capacity one end, the second electric capacity other end ground connection, the 3 rd pin still connects to the probe capacitor; the capacitance signal conversion circuit is connected to the No. 3 pin of the operational amplifier; the 16 th pin of the frequency divider is connected with a power supply and one end of a third capacitor, the other end of the third capacitor is grounded, and the 11 th pin of the frequency divider is connected with the capacitance signal conversion circuit to receive the pulse signal transmitted by the capacitance signal conversion circuit and output the pulse signal through the 13 th pin of the frequency divider.)

1. A capacitance signal detection circuit with a function of shielding interference, the capacitance signal detection circuit (10) comprising an operational amplifier U1, a capacitance signal conversion circuit (11), a frequency divider U2, a first capacitor C1, a second capacitor C2 and a third capacitor C3, wherein:

the model of the operational amplifier U1 is OP162GS, the 2 nd pin of the operational amplifier U1 is communicated with the 6 th pin of the operational amplifier U1, the 6 th pin is further connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, the 6 th pin is further used for being connected with a probe capacitor Cx with a liquid level height detection function, the 7 th pin of the operational amplifier U1 is connected to a power supply, the 4 th pin of the operational amplifier U1 is grounded, the 3 rd pin of the operational amplifier U1 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, and the 3 rd pin is further connected to the probe capacitor Cx;

the capacitance signal conversion circuit (11) is connected to the 3 rd pin of the operational amplifier U1, and is used for receiving a capacitance signal transmitted by the operational amplifier U1 and converting the capacitance signal into a pulse signal;

the model of the frequency divider U2 is MC74HC4060ADT, the 12 th pin of the frequency divider U2 is grounded, the 8 th pin of the frequency divider U2 is grounded, the 16 th pin of the frequency divider U2 is connected to a power supply and one end of the third capacitor C3, the other end of the third capacitor C3 is grounded, and the 11 th pin of the frequency divider U2 is connected to the capacitance signal conversion circuit (11) to receive the pulse signal transmitted by the capacitance signal conversion circuit (11) and output the divided pulse signal through the 13 th pin of the frequency divider U2.

2. The capacitance signal detection circuit according to claim 1, wherein the capacitance signal conversion circuit (11) comprises a comparator U3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, wherein:

the model of the comparator U3 is MAX9140EUK-T, the 4 th pin of the comparator U3 is connected to the 3 rd pin of the operational amplifier U1 and the 11 th pin of the frequency divider U2, the first resistor R1 is connected between the 4 th pin of the comparator U3 and the 11 th pin of the frequency divider U2, the 3 rd pin of the comparator U3 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the 11 th pin of the frequency divider U2, the 5 th pin of the comparator U3 is connected to a power supply and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, the 5 th pin of the comparator U3 is further connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is grounded, the 3 rd pin of the comparator U5 is further connected to one end of the third resistor R5857324 and one end of the fourth resistor R57324, the 1 st pin of the comparator U3 is connected to the 11 th pin of the frequency divider U2, and the 2 nd pin of the comparator U3 is grounded.

3. The capacitance signal detection circuit according to claim 1, wherein a voltage clamp circuit (12) is connected between the operational amplifier U1 and the gate capacitor Cx for clamping the voltage of the capacitance signal detection circuit (10) at a voltage threshold when the capacitance signal detection circuit (10) is subjected to a voltage surge higher than the voltage threshold.

4. The capacitance signal detection circuit according to claim 3, wherein the voltage clamp circuit (12) comprises a first suppressor diode D1, a second suppressor diode D2, a fifth resistor R5 and a sixth resistor R6, wherein:

the first suppressor diode D1 and the second suppressor diode D2 are both RCLAMP0502B, the fifth resistor R5 is connected between the 3 rd pin of the operational amplifier U1 and the probe capacitance Cx, the 1 st pin and the 2 nd pin of the first suppressor diode D1 are respectively connected to both ends of the fifth resistor R5, the sixth resistor R6 is connected between the 6 th pin of the operational amplifier U1 and the probe capacitance Cx, the 1 st pin and the 2 nd pin of the second suppressor diode D2 are respectively connected to both ends of the sixth resistor R6, and the 3 rd pins of the first suppressor diode D1 and the second suppressor diode D2 are both grounded.

5. The capacitance signal detection circuit according to claim 4, wherein a non-inverting driver circuit (13) for outputting a capacitance signal detected by the probe capacitance Cx in phase is connected between the voltage clamp circuit (12) and the operational amplifier (U1).

6. The capacitance signal detection circuit according to claim 5, wherein the in-phase driving circuit (13) adopts a coaxial cable to transmit signals, wherein the coaxial cable comprises a core wire (1), an intermediate shielding layer (3) and an outer shielding layer (5), wherein the core wire (1) is used for transmitting capacitance signals detected by the probe capacitance Cx, and voltages of the core wire (1) and the intermediate shielding layer (3) are provided by the in-phase driving circuit (13) so that the core wire (1) and the intermediate shielding layer (3) are equipotential to eliminate capacitive leakage between the core wire (1) and the intermediate shielding layer (3);

the outer shielding layer (5) is grounded, so that the capacitance between the middle shielding layer (3) and the outer shielding layer (5) is used as the load of the in-phase driving circuit (13).

7. The capacitance signal detection circuit according to claim 5, wherein the in-phase driving circuit (13) comprises an analog switch U4, a processor and a seventh resistor R7, wherein:

the model of the analog switch U4 is MA4644, the 5 th pin of the analog switch U4 is connected to the 3 rd pin of the operational amplifier U1, the 2 nd pin of the analog switch U4 is connected to a power supply, the 3 rd pin of the analog switch U4 is grounded, the 4 th pin of the analog switch U4 is connected to the fifth resistor R5, the 1 st pin of the analog switch U4 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to the power supply, and the 1 st pin of the analog switch U4 is further connected to the processor, and is configured to receive a driving signal transmitted by the processor and having the same detection frequency as the detection frequency of the probe capacitor Cx, so as to drive the analog switch U4 to be in a conducting state when the analog switch U4 receives the capacitance signal of the probe capacitor Cx.

8. The capacitance signal detection circuit according to claim 5, wherein a filter circuit (14) for filtering direct current electrically conducted alternating current is connected between the voltage clamp circuit (12) and the probe capacitance Cx.

9. The capacitance signal detection circuit according to claim 8, wherein the filter circuit (14) comprises a fifth capacitor C5, a sixth capacitor C6, an eighth resistor R8 and a ninth resistor R9, wherein:

the fifth capacitor C5 is connected between the fifth resistor R5 and the probe capacitor Cx, and two ends of the eighth resistor R8 are respectively connected to two ends of the fifth capacitor C5;

the sixth capacitor C6 is connected between the sixth resistor R6 and the probe capacitor Cx, and two ends of the ninth resistor R9 are respectively connected to two ends of the sixth capacitor C6.

10. The capacitance signal detecting circuit according to any one of claims 1-9, wherein the capacitance signal detecting circuit (10) further comprises a seventh capacitor C7, the power supply for supplying power to the capacitance signal detecting circuit (10) is connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.

Technical Field

The present disclosure relates to the field of circuit technologies, and in particular, to a capacitive signal detection circuit with interference shielding function.

Background

The level gauge is a device for measuring the level of a liquid medium, and a common level gauge is of a magnetic suspension type. A liquid level meter, a pressure type liquid level meter, a magnetic turning plate liquid level meter and the like.

Disclosure of Invention

The disclosure aims to provide a capacitance signal detection circuit with an interference shielding function, which is used for solving the technical problem that a capacitance signal measured by a liquid level meter adopting a probe capacitor in the related art is easily interfered by external electromagnetic waves.

In order to achieve the above object, in a first aspect of the embodiments of the present disclosure, there is provided a capacitance signal detection circuit with a function of shielding interference, the capacitance signal detection circuit including an operational amplifier, a capacitance signal conversion circuit, a frequency divider, a first capacitor, an electrical second capacitor, and a third capacitor, wherein:

the model of the operational amplifier is OP162GS, a 2 nd pin of the operational amplifier is communicated with a 6 th pin of the operational amplifier, the 6 th pin is further connected to one end of the first capacitor, the other end of the first capacitor is grounded, the 6 th pin is further used for being connected with a probe capacitor with a liquid level height detection function, a 7 th pin of the operational amplifier is connected to a power supply, a4 th pin of the operational amplifier is grounded, a 3 rd pin of the operational amplifier is connected to one end of the second capacitor, the other end of the second capacitor is grounded, and the 3 rd pin is further connected to the probe capacitor;

the capacitance signal conversion circuit is connected to the No. 3 pin of the operational amplifier and used for receiving a capacitance signal transmitted by the operational amplifier and converting the capacitance signal into a pulse signal;

the type of the frequency divider is MC74HC4060ADT, the 12 th pin of the frequency divider is grounded, the 8 th pin of the frequency divider is grounded, the 16 th pin of the frequency divider is connected to a power supply and one end of the third capacitor, the other end of the third capacitor is grounded, the 11 th pin of the frequency divider is connected to the capacitor signal conversion circuit to receive the pulse signal transmitted by the capacitor signal conversion circuit and output the pulse signal after frequency division through the 13 th pin of the frequency divider.

Optionally, the capacitance signal conversion circuit includes a comparator, a fourth capacitor, a first resistor, a second resistor, a third resistor, and a fourth resistor, where:

the model of the comparator is MAX9140EUK-T, a4 th pin of the comparator is connected with a 3 rd pin of the operational amplifier and an 11 th pin of the frequency divider, the first resistor is connected between the 4 th pin of the comparator and the 11 th pin of the frequency divider, a 3 rd pin of the comparator is connected with one end of the second resistor, the other end of the second resistor is connected with the 11 th pin of the frequency divider, a 5 th pin of the comparator is connected with one end of a power supply and one end of a fourth capacitor, the other end of the fourth capacitor is grounded, a 5 th pin of the comparator is further connected with one end of the third resistor, the other end of the third resistor is connected with one end of the fourth resistor, the other end of the fourth resistor is grounded, and a 3 rd pin of the comparator is further connected with one end of the third resistor and the fourth resistor, the 1 st pin of the comparator is connected to the 11 th pin of the frequency divider, and the 2 nd pin of the comparator is grounded.

Optionally, a voltage clamp circuit for clamping the voltage of the capacitance signal detection circuit at a voltage threshold when the capacitance signal detection circuit is subjected to a voltage impact higher than the voltage threshold is connected between the operational amplifier and the gate capacitor.

Optionally, the voltage clamp circuit comprises a first suppressor diode, a second suppressor diode, a fifth resistor, and a sixth resistor, wherein:

the types of the first suppressor diode and the second suppressor diode are RCLAMP0502B, the fifth resistor is connected between the 3 rd pin of the operational amplifier and the probe capacitor, the 1 st pin and the 2 nd pin of the first suppressor diode are respectively connected to two ends of the fifth resistor, the sixth resistor is connected between the 6 th pin of the operational amplifier and the probe capacitor, the 1 st pin and the 2 nd pin of the second suppressor diode are respectively connected to two ends of the sixth resistor, and the 3 rd pins of the first suppressor diode and the second suppressor diode are both grounded.

Optionally, an in-phase driving circuit for outputting a capacitance signal detected by the probe capacitance in the same phase is connected between the voltage clamping circuit and the operational amplifier.

Optionally, the in-phase driving circuit transmits a signal by using a coaxial cable, wherein the coaxial cable includes a core wire, an intermediate shielding layer, and an outer shielding layer, wherein the core wire is used for transmitting a capacitance signal detected by the probe capacitance Cx, and voltages of the core wire and the intermediate shielding layer are provided by the in-phase driving circuit, so that the core wire is equipotential with the intermediate shielding layer to eliminate capacitive leakage between the core wire and the intermediate shielding layer;

the outer shielding layer is grounded, so that the capacitance between the middle shielding layer and the outer shielding layer is used as the load of the in-phase driving circuit.

Optionally, the in-phase driving circuit includes an analog switch, a processor, and a seventh resistor, wherein:

the model of the analog switch is MA4644, a 5 th pin of the analog switch is connected to a 3 rd pin of the operational amplifier, a 2 nd pin of the analog switch is connected to the power supply, a 3 rd pin of the analog switch is grounded, a4 th pin of the analog switch is connected to the fifth resistor, a 1 st pin of the analog switch is connected to one end of the seventh resistor, the other end of the seventh resistor is connected to the power supply, and the 1 st pin of the analog switch is further connected to the processor and is used for receiving a driving signal which is transmitted by the processor and has the same detection frequency as the detection frequency of the probe capacitor, so that the analog switch is driven to be in a conducting state when the analog switch receives a capacitance signal of the probe capacitor.

Optionally, a filter circuit for filtering dc current and electrically conducting ac current is connected between the voltage clamp circuit and the probe capacitor.

Optionally, the filter circuit includes a fifth capacitor, a sixth capacitor, an eighth resistor, and a ninth resistor, where:

the fifth capacitor is connected between the fifth resistor and the electrode detecting capacitor, and two ends of the eighth resistor are respectively connected to two ends of the fifth capacitor;

the sixth capacitor is connected between the sixth resistor and the electrode detecting capacitor, and two ends of the ninth resistor are respectively connected to two ends of the sixth capacitor.

Optionally, the capacitance signal detection circuit further includes a seventh capacitor, the power supply for supplying power to the capacitance signal detection circuit is connected to one end of the seventh capacitor, and the other end of the seventh capacitor is grounded.

In another aspect of the disclosed embodiments, there is provided a liquid level meter including the capacitance signal detection circuit of any one of the above first aspects.

Through the technical scheme, the capacitance signal detected by the probe capacitor is transmitted to the capacitance signal conversion circuit through the operational amplifier, the capacitance signal is converted into the pulse signal, then the frequency of the pulse signal is reduced and output through the frequency divider, and accurate liquid level height data information can be obtained through detecting the pulse signal output by the frequency divider and based on the relation between the liquid level height and the pulse signal obtained in advance. For an operational amplifier with the model number of OP162GS, a 2 nd pin is a negative input end, a 6 th pin is an output end, the 2 nd pin of the operational amplifier is communicated with a 6 th pin of the operational amplifier, the 6 th pin is also connected with one end of the first capacitor, the other end of the first capacitor is grounded, the 6 th pin is also used for being connected with a probe capacitor with a liquid level height detection function, a 7 th pin of the operational amplifier is connected with a power supply, a4 th pin of the operational amplifier is grounded, a 3 rd pin of the operational amplifier is connected with one end of the second capacitor, the other end of the second capacitor is grounded, and the 3 rd pin is also connected with the probe capacitor, so that a circuit with the same output voltage and output voltage in magnitude and phase is formed, the subsequent signal processing is convenient, and the operational amplifier has the characteristics of high input impedance and low output impedance, the operational amplifier is equivalent to an open circuit of a front-stage circuit and forms a constant voltage power supply for a rear-stage circuit, so that the impedance matching effect is achieved, the influence of the front-stage circuit on the rear-stage circuit is reduced, and even if external electromagnetic waves interfere wires connected with a probe capacitor in the front-stage circuit, the operational amplifier can transmit real capacitance signals to the rear-stage circuit, so that most external electromagnetic interference is shielded.

Additional features and advantages of the disclosure will be set forth in the detailed description which follows.

Drawings

The accompanying drawings, which are included to provide a further understanding of the disclosure and are incorporated in and constitute a part of this specification, illustrate embodiments of the disclosure and together with the description serve to explain the disclosure without limiting the disclosure. In the drawings:

fig. 1 is a schematic diagram illustrating a capacitive signal detection circuit with interference shielding functionality according to an exemplary embodiment.

FIG. 2 is a schematic diagram illustrating a sensor configuration according to an exemplary embodiment.

FIG. 3 is a schematic diagram illustrating a circuit schematic of an in-phase output sensor signal according to an exemplary embodiment.

FIG. 4 is a schematic view of a fluid level gauge shown in accordance with an exemplary embodiment.

Description of the reference numerals

10 capacitance signal detection circuit 11 capacitance signal conversion circuit

12 voltage clamp circuit 13 in-phase driving circuit

14 first connection terminal of filter circuit 15

16 second connection end 17 third connection end

18 fourth connection 20 level gauge

21 gauge head 22 lead of liquid level meter

23 liquid level measuring sensor U1 operational amplifier

U2 frequency divider U3 comparator

U4 analog switch D1 first suppressor diode

D2 second suppressor diode R1 first resistor

R2 second resistor R3 third resistor

R4 fourth resistor R5 fifth resistor

R6 sixth resistor R7 seventh resistor

R8 eighth resistor R9 ninth resistor

R10 tenth resistor C1 first capacitor

C2 second capacitance C3 third capacitance

C4 fourth capacitance C5 fifth capacitance

C6 sixth capacitance C7 seventh capacitance

Cx probe capacitor VDD1 power supply terminal

SGND earthing terminal

Detailed Description

The following detailed description of specific embodiments of the present disclosure is provided in connection with the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating the present disclosure, are given by way of illustration and explanation only, not limitation.

Fig. 1 is a schematic diagram illustrating a capacitance signal detection circuit with interference shielding function according to an exemplary embodiment, where, as shown in fig. 1, the capacitance signal detection circuit 10 includes an operational amplifier U1, a capacitance signal conversion circuit 11, a frequency divider U2, a first capacitor C1, a second capacitor C2, and a third capacitor C3, where:

the model of the operational amplifier U1 is OP162GS, the 2 nd pin of the operational amplifier U1 is communicated with the 6 th pin of the operational amplifier U1, the 6 th pin is further connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, the 6 th pin is further used for being connected with a probe capacitor Cx with a liquid level height detection function, the 7 th pin of the operational amplifier U1 is connected to a power supply, the 4 th pin of the operational amplifier U1 is grounded, the 3 rd pin of the operational amplifier U1 is connected to one end of the second capacitor C2, the other end of the second capacitor C2 is grounded, and the 3 rd pin is further connected to the probe capacitor Cx;

in a possible implementation, the liquid level meter 20 can be applied to industries such as central air conditioning, ultra-low temperature storage, chemical engineering and the like, and in consideration of the liquid level height range to be detected in the application environment, the detection range of the probe capacitance Cx is 0-3300 pF, and based on the detection range, the operational amplifier U1 with the model of OP162GS can be selected for better adaptation. The capacitance signal detecting Circuit 10 may be disposed on a Circuit board, such as a pcb (printed Circuit board), and the power supply may be powered by a power supply terminal VDD1 shown in fig. 1, and may be connected to a ground terminal SGND when grounded.

Specifically, the operational amplifier U1 is connected to form a circuit having the same output voltage and the same output voltage in magnitude and phase, and has the characteristics of high input impedance and low output impedance, and the circuit between the operational amplifier U1 and the probe capacitance Cx is regarded as a preceding circuit, the circuit between the operational amplifier U1 and the final output terminal (i.e., the fourth connection terminal 18 connected to the 13 th pin of the frequency divider U2 described below) is regarded as a subsequent circuit, and the circuit is open to the preceding circuit, a constant voltage power supply is formed for the rear-stage circuit, the impedance matching function is realized, the influence of the front-stage circuit on the rear-stage circuit is reduced, further, even if external electromagnetic waves interfere with a lead wire connected with the probe capacitance Cx in the previous stage circuit, the operational amplifier U1 can transmit a real capacitance signal to the next stage circuit, thereby shielding most of the external electromagnetic interference. In a possible implementation manner, the pin 3 of the operational amplifier U1 is connected to one end of the probe capacitance Cx through the first connection terminal 15 shown in fig. 1, the other end of the probe capacitance Cx is grounded, and the pin 6 of the operational amplifier U1 is connected to the shielding layer of the probe capacitance Cx through the second connection terminal 16 shown in fig. 1, so that the capacitance signal detection circuit 10 has a better effect of shielding external electromagnetic waves. It should be noted that, as shown in fig. 1, the pins of the aforementioned non-mentioned operational amplifier U1, such as the 1 st pin, the 5 th pin, and the 8 th pin, are all set to be empty.

The capacitance signal conversion circuit 11 is connected to the 3 rd pin of the operational amplifier U1, and is configured to receive a capacitance signal transmitted by the operational amplifier U1, and convert the capacitance signal into a pulse signal;

the model of the frequency divider U2 is MC74HC4060ADT, the 12 th pin of the frequency divider U2 is grounded, the 8 th pin of the frequency divider U2 is grounded, the 16 th pin of the frequency divider U2 is connected to a power supply and one end of the third capacitor C3, the other end of the third capacitor C3 is grounded, and the 11 th pin of the frequency divider U2 is connected to the capacitor signal conversion circuit 11 to receive the pulse signal transmitted by the capacitor signal conversion circuit 11 and output the divided pulse signal through the 13 th pin of the frequency divider U2.

Specifically, the probe capacitance Cx converts the liquid level height into a capacitance signal, and transmits the capacitance signal to the capacitance signal conversion circuit 11 through the operational amplifier U1, and converts the capacitance signal into a pulse signal, and since the frequency of the pulse signal after conversion is high and a high operation capability is required correspondingly, the frequency of the pulse signal is reduced by the frequency divider U2 in order to reduce the operation amount and increase the operation speed. In a possible embodiment, the capacitance signal detection circuit 10 further includes a tenth resistor R10, the 13 th pin of the frequency divider U2 is connected to one end of the tenth resistor R10, and the other end of the tenth resistor R10 is connected to the fourth connection terminal 18, so that a finally output pulse signal can be obtained through the fourth connection terminal 18 to calculate the liquid level height according to the pulse signal. Similar to the description above regarding operational amplifier U1, pins such as pins 1,2,3,4,5,6,7,9,10,14,15 of divider U2, not mentioned above, are all left empty.

Through the technical scheme, the capacitance signal detected by the probe capacitance Cx is transmitted to the capacitance signal conversion circuit 11 through the operational amplifier U1, the capacitance signal is converted into a pulse signal, then the frequency of the pulse signal is reduced and output through the frequency divider U2, and accurate liquid level height data information can be obtained through detecting the pulse signal output by the frequency divider U2 and based on the relation between the liquid level height and the pulse signal obtained in advance. For an operational amplifier U1 with the model number of OP162GS, a 2 nd pin is a negative input end, a 6 th pin is an output end, the 2 nd pin of the operational amplifier U1 is communicated with a 6 th pin of the operational amplifier U1, the 6 th pin is further connected to one end of a first capacitor C1, the other end of the first capacitor C1 is grounded, the 6 th pin is further used for being connected with a probe capacitor Cx with a liquid level height detection function, a 7 th pin of the operational amplifier U1 is connected to a power supply, a4 th pin of the operational amplifier U1 is grounded, a 3 rd pin of the operational amplifier U1 is connected to one end of a second capacitor C2, the other end of the second capacitor C2 is grounded, and the 3 rd pin is further connected to the probe capacitor Cx, so as to form a circuit with the same output voltage and the same output voltage in magnitude and phase, and facilitate subsequent signal processing, the operational amplifier U1 can transmit a real capacitance signal to the rear-stage circuit to shield most of external electromagnetic interference even if external electromagnetic waves interfere with the lead 22 connected with the probe capacitance Cx in the front-stage circuit.

Optionally, as shown in fig. 1, the capacitance signal conversion circuit 11 includes a comparator U3, a fourth capacitor C4, a first resistor R1, a second resistor R2, a third resistor R3 and a fourth resistor R4, wherein:

the model of the comparator U3 is MAX9140EUK-T, the 4 th pin of the comparator U3 is connected to the 3 rd pin of the operational amplifier U1 and the 11 th pin of the frequency divider U2, the first resistor R1 is connected between the 4 th pin of the comparator U3 and the 11 th pin of the frequency divider U2, the 3 rd pin of the comparator U3 is connected to one end of the second resistor R2, the other end of the second resistor R2 is connected to the 11 th pin of the frequency divider U2, the 5 th pin of the comparator U3 is connected to a power supply and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, the 5 th pin of the comparator U3 is further connected to one end of the third resistor R3, the other end of the third resistor R3 is connected to one end of the fourth resistor R4, the other end of the fourth resistor R4 is grounded, the 3 rd pin of the comparator U5 is further connected to one end of the third resistor R5857324 and one end of the fourth resistor R57324, the 1 st pin of the comparator U3 is connected to the 11 th pin of the frequency divider U2, and the 2 nd pin of the comparator U3 is grounded.

Since the capacitance signal is not easily processed, the capacitance signal can be converted into a pulse signal which is easily processed by the capacitance signal conversion circuit 11 including the comparator U3. Through the connection mode, the capacitance signal change of the probe capacitance Cx can be equivalent to the second capacitance C2, the 4 th pin of the comparator U3 is directly connected with the second capacitance C2, the capacitance signal change can be acquired through the second capacitance C2, and the external interference is reduced. The Comparator U3 with model number MAX9140EUK-T is a Rail-to-Rail Single power Supply Comparator U3(Rail-to-Rail Single-Supply Comparator), and has the advantages of high operation speed and low power consumption.

Optionally, as shown in fig. 1, a voltage clamping circuit 12 for clamping the voltage of the capacitance signal detection circuit 10 to a voltage threshold when the capacitance signal detection circuit 10 is subjected to a voltage surge higher than the voltage threshold is connected between the operational amplifier U1 and the gate capacitance Cx.

In one possible implementation, as shown in fig. 1, the voltage clamp circuit 12 includes a first suppressor diode D1, a second suppressor diode D2, a fifth resistor R5, and a sixth resistor R6, wherein:

the first suppressor diode D1 and the second suppressor diode D2 are both RCLAMP0502B, the fifth resistor R5 is connected between the 3 rd pin of the operational amplifier U1 and the probe capacitance Cx, the 1 st pin and the 2 nd pin of the first suppressor diode D1 are respectively connected to both ends of the fifth resistor R5, the sixth resistor R6 is connected between the 6 th pin of the operational amplifier U1 and the probe capacitance Cx, the 1 st pin and the 2 nd pin of the second suppressor diode D2 are respectively connected to both ends of the sixth resistor R6, and the 3 rd pins of the first suppressor diode D1 and the second suppressor diode D2 are both grounded.

Specifically, the first Suppressor diode D1 and the second Suppressor diode D2 are Transient Voltage Suppressors (TVS), and the Voltage of the capacitance signal detecting circuit 10 can be clamped at the Voltage threshold by the above connection method when receiving a Voltage surge such as an electrostatic high Voltage, so as to prevent the capacitance signal detecting circuit 10 from being damaged by the high Voltage surge. It should be noted that the voltage threshold is determined by parameters of electronic components such as the first suppressor diode D1 and the second suppressor diode D2, and the determination relationship is common knowledge, and the details of the disclosure are not repeated.

On the other hand, the voltage surge that is not completely absorbed by the first suppressor diode D1 and the second suppressor diode D2 can be absorbed by the fifth resistor R5 and the sixth resistor R6, and thus the dual protection effect is formed with the first suppressor diode D1 and the second suppressor diode D2, and the safety of the capacitance signal detection circuit 10 is further improved.

Optionally, as shown in fig. 1, a non-inverting driver 13 for outputting a capacitance signal detected by the gate capacitance Cx in the non-inverting manner is connected between the voltage clamp 12 and the operational amplifier U1.

Wherein, optionally, the in-phase driving circuit 13 employs a coaxial cable to transmit signals, wherein the coaxial cable includes a core wire, an intermediate shielding layer, and an outer shielding layer, wherein the core wire is used to transmit the capacitance signal detected by the probe capacitance Cx, and the voltages of the core wire and the intermediate shielding layer are provided by the in-phase driving circuit, so that the core wire and the intermediate shielding layer are at the same potential to eliminate capacitive leakage between the core wire and the intermediate shielding layer; the outer shield layer is grounded, so that the capacitance between the middle shield layer and the outer shield layer serves as a load of the in-phase driving circuit 13.

In specific implementation, a possible implementation is shown in fig. 2 and 3, and the sensor structure shown in fig. 2 includes a coaxial cable, where the coaxial cable includes a core wire 1, a first braid 2, an intermediate shielding layer 3, a second braid 4, an outer shielding layer 5, and a rubber layer 6. Fig. 2 also shows the internal structure of the sensor, in which the core wire 1 is connected to the sensor inner electrode 9, the outer shielding layer 5 is connected to the sensor outer electrode 7, the middle shielding layer 3 is inserted into the sensor outer electrode 7 and is not connected to any electrode of the sensor, and an in-phase driving signal is applied to the middle shielding layer 3 relative to the core wire 1 when signal measurement is performed, so that the middle shielding layer 3 can effectively suppress the influence of external signals and the change of the capacitance of the cable itself on the measurement of the sensor signal (the capacitance signal detected by the probe capacitance Cx). The intermediate shielding layer 3 has good insulating property with other wires or electrodes, and the insulation between the sensor electrodes is completed by the electrode insulating layer 10.

Fig. 3 is an equivalent circuit diagram of the in-phase driving circuit 13 applying the in-phase driving signal of the opposite core wire 1 to the middle shielding layer 3, and as shown in fig. 3, the in-phase driving circuit 13 is a voltage follower with a voltage amplification factor of 1:1, so as to ensure that the core wire 1 and the middle shielding layer 3 are equipotential, and thus eliminate the influence of the parasitic capacitance of the sensor signal cable. The outer shield 5 is connected to circuit ground (zero potential point). The signal of the sensor finally enters the operational amplifier U1 through the core wire 1 intact for signal measurement processing.

By adopting the in-phase shielding driving technology, the performance of the sensor is not influenced by the cable of the sensor within a distance of 10 meters, and the outer layer is shielded and grounded, so that the better performance of the sensor is ensured.

In one possible implementation, as shown in fig. 1, the in-phase driving circuit 13 includes an analog switch U4, a processor, and a seventh resistor R7, wherein:

the model of the analog switch U4 is MA4644, the 5 th pin of the analog switch U4 is connected to the 3 rd pin of the operational amplifier U1, the 2 nd pin of the analog switch U4 is connected to a power supply, the 3 rd pin of the analog switch U4 is grounded, the 4 th pin of the analog switch U4 is connected to the fifth resistor R5, the 1 st pin of the analog switch U4 is connected to one end of the seventh resistor R7, the other end of the seventh resistor R7 is connected to the power supply, and the 1 st pin of the analog switch U4 is further connected to the processor, and is configured to receive a driving signal transmitted by the processor and having the same detection frequency as the detection frequency of the probe capacitor Cx, so as to drive the analog switch U4 to be in a conducting state when the analog switch U4 receives the capacitance signal of the probe capacitor Cx.

Specifically, the 1 st pin of the analog switch U4 is connected to the processor through the third connection terminal 17, the processor inputs a driving signal with the same detection frequency as the probe capacitance Cx through the 1 st pin of the analog switch U4, when the analog switch U4 receives the driving signal, the analog switch U4 is turned on, and then the capacitance signal detected by the probe capacitance Cx is output through the 5 th pin of the analog switch U4, so that the capacitance signal can be output in the same phase, and delay and error caused by hanging materials when measuring liquid with high viscosity can be better improved. Note that the 6 th pin of the analog switch U4 is left empty.

Optionally, as shown in fig. 1, a filter circuit 14 for filtering dc current and electrically conducting ac current is connected between the voltage clamp circuit 12 and the probe capacitance Cx.

In one possible implementation, as shown in fig. 1, the filter circuit 14 includes a fifth capacitor C5, a sixth capacitor C6, an eighth resistor R8, and a ninth resistor R9, wherein:

the fifth capacitor C5 is connected between the fifth resistor R5 and the probe capacitor Cx, and two ends of the eighth resistor R8 are respectively connected to two ends of the fifth capacitor C5;

the sixth capacitor C6 is connected between the sixth resistor R6 and the probe capacitor Cx, and two ends of the ninth resistor R9 are respectively connected to two ends of the sixth capacitor C6.

Since the capacitance signal detected by the probe capacitance Cx is an alternating current, the capacitance signal detected by the probe capacitance Cx can be conducted through the filter circuit 14, and a noise signal which is a direct current is filtered out, thereby reducing the interference of the noise signal.

Optionally, as shown in fig. 1, the capacitance signal detection circuit 10 further includes a seventh capacitor C7, the power supply for supplying power to the capacitance signal detection circuit 10 is connected to one end of the seventh capacitor C7, and the other end of the seventh capacitor C7 is grounded.

The dc power supplied by the power supply can be filtered by the seventh capacitor C7, so that the above-mentioned electronic components connected to the power supply, such as the operational amplifier U1, the frequency divider U2, the comparator U3, and the analog switch U4, can work better.

In a possible implementation manner, for a probe capacitor with a detection range of 0-3300 pF, in order to obtain an easily processed pulse signal, values of a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, a ninth resistor R9, and a tenth resistor R10 are sequentially 2k Ω,10 k Ω,10 k Ω,10 k Ω, 100 Ω, 100 Ω, 47k Ω, 100k Ω, 100k Ω, 100k Ω, 1k Ω. Values of the first capacitor C1, the second capacitor C2, the third capacitor C3, the fourth capacitor C4, the fifth capacitor C5, the sixth capacitor C6 and the seventh capacitor C7 are 47pF, 220pF, 0.104 muF, 0.334 muF and 0.104 muF in sequence.

As shown in fig. 4, another aspect of the embodiment of the present disclosure further provides a liquid level meter 20, which includes the capacitance signal detection circuit 10 as described in any one of the above, a liquid level measurement sensor 23, a conducting wire 22, and a liquid level meter head 21, wherein the liquid level meter head 21 is connected to the liquid level measurement sensor 23 through the conducting wire 22. The probe capacitance Cx can be provided in the liquid level measuring sensor 23, the capacitance signal detection circuit 10 can be provided in the gauge head 21 of the liquid level meter, the liquid level measuring sensor 23 is inserted into the container to measure the liquid level height, and the measured value can be displayed through the gauge head 21 of the liquid level meter.

The preferred embodiments of the present disclosure are described in detail with reference to the accompanying drawings, however, the present disclosure is not limited to the specific details of the above embodiments, and various simple modifications may be made to the technical solution of the present disclosure within the technical idea of the present disclosure, and these simple modifications all belong to the protection scope of the present disclosure.

It should be noted that, in the foregoing embodiments, various features described in the above embodiments may be combined in any suitable manner, and in order to avoid unnecessary repetition, various combinations that are possible in the present disclosure are not described again.

In addition, any combination of various embodiments of the present disclosure may be made, and the same should be considered as the disclosure of the present disclosure, as long as it does not depart from the spirit of the present disclosure.