阅读说明：本技术 改善临界尺寸一致性的方法与系统 (Method and system for improving critical dimension uniformity ) 是由 陆埼达 蔡启铭 于 2019-07-04 设计创作，主要内容包括：本发明实施例涉及改善临界尺寸一致性的方法与系统。一种方法包含：接收掩模的图案布局；收缩所述图案布局以形成收缩图案；确定所述收缩图案内的多个特征的每一个的中心线；和使所述多个特征的每一个的所述中心线与栅格贴齐。所述栅格表示掩模制造工具的最小分辨率大小。所述方法进一步包含：在将使多个特征的每一个的所述中心线与所述栅格贴齐之后,使用所述收缩图案来制造所述掩模。(Embodiments of the present invention relate to methods and systems for improving critical dimension uniformity. One method comprises the following steps: receiving a pattern layout of a mask; shrinking the pattern layout to form a shrunk pattern; determining a centerline of each of a plurality of features within the contraction pattern; and aligning the centerline of each of the plurality of features with a grid. The grid represents the minimum resolution size of the mask manufacturing tool. The method further comprises: after aligning the centerline of each of a plurality of features with the grid, the mask is fabricated using the shrink pattern.)

1. A method of fabricating a mask, comprising:

receiving a pattern layout of a mask;

shrinking the pattern layout to form a shrunk pattern;

determining a centerline of each of a plurality of features within the contraction pattern;

aligning the centerline of each of the plurality of features with a grid representing a minimum resolution size of a mask fabrication tool; and

after aligning the centerline of each of the plurality of features with the grid, the mask is fabricated using the shrink pattern.

2. The method of claim 1, further comprising: adjusting a critical dimension of a feature of the plurality of features to reach a predetermined critical dimension.

3. The method of claim 2, wherein the predetermined critical dimension is an integer multiple of the minimum resolution size of the mask fabrication tool.

4. The method of claim 1, wherein the minimum resolution size of the mask fabrication tool is in a range of about 0.1 nanometers to about 0.3 nanometers.

5. The method of claim 1, wherein aligning the centerline of each of the plurality of features with the grid comprises: shifting a first subset of the plurality of features in a first direction perpendicular to the centerline and shifting a second subset of the plurality of features in a second direction opposite the first direction.

6. The method of claim 1, wherein aligning the centerline of each of the plurality of features with the grid occurs after an OPC procedure.

7. The method of claim 1, wherein aligning the centerline of each of the plurality of features with the grid occurs during a fracturing procedure.

8. The method of claim 1, further comprising: the mask is used to form an integrated circuit.

9. A method of fabricating a mask, comprising:

receiving a first pattern for fabricating a first mask;

receiving a second pattern for fabricating a second mask;

aligning first features of the first pattern with second features of the second pattern;

after the aligning, shrinking the first pattern and the second pattern to form a first shrunk pattern and a second shrunk pattern;

adjusting an edge of the second feature to match an edge of the first feature in response to determining that the first feature is no longer aligned with the second feature; and

fabricating the first mask using the first shrink pattern and fabricating the second mask using the second shrink pattern.

10. A computer readable medium for manufacturing a mask comprising machine readable instructions that when executed by a processor cause a system to:

receiving a mask pattern for fabricating a layer in an integrated circuit;

shrinking the mask pattern to form a shrunk pattern;

identifying a centerline of a feature of the shrink pattern;

aligning the centerline of the feature with a grid representing a minimum resolution size of a mask manufacturing tool; and

adjusting a critical dimension of the feature to be an integer multiple of the minimum resolution size of the mask fabrication tool.

Technical Field

Embodiments of the present invention relate to methods and systems for improving critical dimension uniformity.

Background

Various photolithographic techniques may be used to form integrated circuits. These techniques typically involve exposing a photoresist layer to a light source through a patterned mask. In general, the final pattern formed onto the photoresist layer does not exactly match the pattern from which the pattern in the mask is formed. This is caused by various lithographic process parameters, such as the resolution of the light source. It is important to ensure that the final printed pattern does not differ too far from the design pattern, otherwise the functionality of the circuit will be negatively affected.

Typically, a circuit designer sends a target pattern to a mask foundry. The target pattern is typically defined as a number of polygonal features that form the desired pattern. Then, the mask foundry may generate an initial layout pattern associated with the target pattern. Then, the mask foundry may apply various lithography models to the target pattern to generate an optimized layout pattern. Then, a mask may be manufactured using the optimized layout pattern. The manufactured mask is then used in a photolithography process to form a desired pattern on the photoresist layer.

In some instances, it is desirable to take a pattern and shrink the pattern to create a slightly smaller circuit. For example, it may be desirable to produce a shrunk pattern having a size that is 98% of the size of the original pattern. It is desirable to thereby protect the layout of the pattern and thus the subsequently formed mask from adverse effects.

Disclosure of Invention

An embodiment of the invention relates to a method, comprising: receiving a pattern layout of a mask; shrinking the pattern layout to form a shrunk pattern; determining a centerline of each of a plurality of features within the contraction pattern; aligning the centerline of each of the plurality of features with a grid representing a minimum resolution size of a mask fabrication tool; and after aligning the centerline of each of the plurality of features with the grid, fabricating the mask using the shrink pattern.

An embodiment of the invention relates to a method, comprising: receiving a first pattern for fabricating a first mask; receiving a second pattern for fabricating a second mask; aligning first features of the first pattern with second features of the second pattern; after the aligning, shrinking the first pattern and the second pattern to form a first shrunk pattern and a second shrunk pattern; in response to determining that the first feature is no longer aligned with the second feature, adjusting an edge of the second feature to match an edge of the first feature; and fabricating the first mask using the first shrink pattern and fabricating the second mask using the second shrink pattern.

An embodiment of the invention relates to a computer readable medium comprising machine readable instructions which, when executed by a processor, cause a system to: receiving a mask pattern for fabricating a layer in an integrated circuit; shrinking the mask pattern to form a shrunk pattern; identifying a centerline of a feature of the shrink pattern; aligning the centerline of the feature with a grid representing a minimum resolution size of a mask manufacturing tool; and adjusting the critical dimension of the feature to be an integer multiple of the minimum resolution size of the mask fabrication tool.

Drawings

Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawing figures. It should be noted that, in accordance with industry standard practice, the various components are not drawn to scale. In fact, the dimensions of the various elements may be arbitrarily increased or decreased for clarity of discussion.

FIG. 1 is a flow chart showing a pictorial method for improving layout pattern optimization, in accordance with an example of the principles described herein.

Fig. 2A is a diagram showing a pictorial contraction pattern on a grid in accordance with an example of the principles described herein.

Fig. 2B is a diagram showing centerlines on features of a shrink pattern in accordance with an example of principles described herein.

Fig. 2C is a diagram showing centerlines aligned with a grid according to an example of principles described herein.

Fig. 2D is a diagram showing the size of features adjusted to match a grid, according to an example of principles described herein.

Fig. 3A, 3B, 3C, and 3D are diagrams showing a procedure for aligning first features of a first shrink pattern with second features of a second shrink pattern, according to an example of principles described herein.

Fig. 4 is a flow chart showing a pictorial method for generating consistent critical dimensions of shrink patterns by aligning centerlines with a grid, according to an example of principles described herein.

Fig. 5 is a flow chart showing a pictorial method for generating consistent critical dimensions of a shrink pattern by aligning edges of features of the shrink pattern with edges of features of another pattern, in accordance with an example of the principles described herein.

Fig. 6 is a flow chart showing an illustrative mask process according to an example of principles described herein.

FIG. 7 is a diagram showing a pictorial representation of a computing system for generating consistent critical dimensions, in accordance with an example of the principles described herein.

Detailed Description

The following disclosure provides many different embodiments, or examples, for implementing different features of the provided objects. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, "forming a first member over or on a second member" may include embodiments in which the first member and the second member are formed in direct contact, and may also include embodiments in which additional members may be formed between the first member and the second member such that the first member and the second member may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Furthermore, spatially relative terms, such as "below," "lower," "above," "upper," and the like, may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s), as illustrated in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The apparatus may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein may be interpreted accordingly.

As described above, it is desirable to take a pattern and shrink the pattern to create a slightly smaller circuit. For example, it may be desirable to produce a shrunk pattern having a size that is 98% of the size of the original pattern. It is desirable to thereby protect the layout of the pattern, and thus the subsequently formed mask, from adverse effects.

The mask may be formed using an electron beam (e-beam) lithography procedure. E-beam lithography involves directing an electron beam onto a thin film (e.g., photoresist) that is sensitive to the electron beam. The e-beam changes the solubility of the photoresist to allow removal of either the exposed areas or the unexposed areas during the development process.

To create a mask using an e-beam lithography tool, the design pattern is subjected to a data preparation procedure. The data preparation procedure may involve a Logical Operation Procedure (LOP) in which various logical operations are applied to the design pattern to ensure compliance with various rules. Various rule-based and model-based Optical Proximity Correction (OPC) techniques are then applied. After applying these techniques, a fracturing procedure is applied.

The fracturing program changes the design pattern modified by the LOP and OPC programs into the electron beam format of the electron beam lithography tool. For example, a manufacturing tool used to perform an electron beam procedure typically has a minimum resolution size. For example, the minimum resolution size of an e-beam lithography tool may be 0.2 Nanometers (NM). Thus, features within the design pattern formed by the e-beam lithography tool are adjusted by the fracturing program to coincide with integer multiples of the minimum resolution size of the tool.

However, when the pattern is shrunk by a relatively small amount (e.g., to 98% of the original design), the fracturing procedure will cause inconsistent material to be truncated. For example, a feature may be truncated, while a neighboring feature may not be truncated. This results in inconsistent critical dimensions for a set of features. In other words, the features within a set of features may have different critical dimensions, which may lead to manufacturing and yield problems.

In accordance with the principles described herein, a process is applied to make the critical dimensions of the shrink pattern more uniform. Thereby resulting in a smoother process and improved yield.

In one example, after a shrink procedure is applied to the pattern layout to form a shrunk pattern layout, the features of the shrunk pattern are given the centerlines. The center line of the respective feature is then adjusted to correspond to a grid, wherein the width of each cell corresponds to the minimum resolution size of the tool. The critical dimensions of the features may then be adjusted so that the edges of the features are also aligned with the grid. Thereby, the features will have more consistent critical dimensions and will not be negatively affected during the fracturing process.

In another example, a first set of features within the main layer may be aligned with a second set of features in a reference layer. Then, after the shrink procedure is applied to both the main layer and the reference layer, the edges of the first set of features may no longer be aligned with the edges of the second set of features. Then, a relationship between the edges of the first set of features and the edges of the second set of features may be defined after the shrink procedure. This definition may be used to adjust the edge of the main layer to match the edge of the reference layer.

FIG. 1 is a flow chart showing an illustrative method 100 for improving layout pattern optimization. According to the present example, the method 100 includes applying a shrink program 104 to the pattern layout 102. The pattern layout 102 may be for one of several layers of an integrated circuit. For example, pattern layout 102 may be used for a polysilicon gate layer. In another example, the pattern layer 102 may be used for a source/drain layer. Other layers of the integrated circuit are contemplated.

Shrink program 104 reduces the size of pattern layout 102 to a slightly smaller size. This can be used, for example, to produce a slightly smaller integrated circuit. The shrink program 104 results in a shrink pattern 106. The layout of the shrink pattern 106 is the same as the pattern layout 102, however, its size is smaller. In an example, the shrink pattern 106 is 98% of the size of the pattern layout 102. In an example, the shrink pattern 106 has a size within about 95% to about 99% of the size of the pattern layout 102. Other size ranges are contemplated.

The method 100 further includes a program 108 for determining a centerline of a feature of the shrinkage pattern 106. For example, the features within the contracted pattern 106 may be long polygonal features. These features may correspond to, for example, gate devices. The centerline may extend longitudinally along the long polygonal feature. In some examples, the centerline may extend perpendicular to the critical dimension. As will be shown in fig. 2B, the centerline extends vertically, while the critical dimension is defined horizontally. In some examples, the critical dimension may be defined vertically. In this case, the centerline may extend horizontally. In some examples, the features may be "L" shaped and extend vertically and horizontally. In this case, the centerlines may be placed in various directions at the center of the feature.

The method 100 further includes a program 110 for aligning the centerline with the grid. The grid may be designed such that each cell of the grid corresponds to a minimum resolution size of an e-beam lithography tool that will be used to fabricate the mask of the shrink pattern 106. Features associated with the centerline are adjusted by aligning the centerline with the grid. In some examples, some features move in one direction while other features move in the opposite direction. More specifically, the feature may be movable in a first direction perpendicular to the centerline. While the other feature is movable in a second direction opposite the first direction and perpendicular to the centerline.

The method 100 further includes a process 112 for adjusting the critical dimension of the feature. The critical dimension may be adjusted to a predetermined critical dimension. The predetermined critical dimension may be an integer multiple of a minimum resolution of the e-beam lithography tool. In general, it may be desirable to adjust the critical dimension to be as small as possible while adjusting it to an integer multiple of the minimum resolution of the e-beam lithography tool. For example, if the critical dimension of the features in the shrink pattern 106 is 15.7nm and the minimum resolution size of the e-beam lithography tool is 0.2nm, the critical dimension of the features may be adjusted to 15.6nm or 15.8 nm. Increasing the critical dimension may be decided if increasing the critical dimension to satisfy the integer multiple requires less modification than decreasing the critical dimension to satisfy the integer multiple. Conversely, if reducing the critical dimension to satisfy the integer multiple requires less modification than increasing the critical dimension to satisfy the integer multiple, it may be decided to reduce the critical dimension. In some examples, the critical dimension may always be reduced to the nearest integer multiple. In some examples, the critical dimension may always be increased to the nearest integer multiple. Thereby, a consistent critical dimension may be facilitated to be maintained.

The method 100 further includes a procedure 114 for fabricating a mask. Specifically, the shrink pattern 106 modified by the procedures 108, 110, and 112 may be subjected to a breaking procedure and provided to an e-beam lithography tool. Next, the electron beam lithography tool may fabricate a mask. The mask may then be used in production to fabricate integrated circuits.

Fig. 2A is a diagram showing a depicted shrink pattern 106 on a grid 202. The grid is made up of a number of cells 203 (which may also be referred to as pixels). The unit 203 may correspond to a minimum resolution size of an e-beam lithography tool to be used for a mask for fabricating the pattern 106.

In this example, the contraction pattern 106 includes a number of features 204a, 204b, 204 c. Each of the features 204a, 204b, 204c has a critical dimension 206. If the fracturing procedure is to be applied without using the principles described herein, each of the features 204a, 204b, 204c will be truncated differently. This will result in inconsistent critical dimensions between each of the features 204a, 204b, 204 c.

Fig. 2B is a diagram showing centerlines 208a, 208B, 208c on features of the shrink pattern 106. Specifically, feature 204a has centerline 208a, feature 204b has centerline 208b, and feature 204c has centerline 208 c. Centerline 208a represents the midpoint between an edge of feature 204a and the opposite edge of feature 204 a. Centerline 208b represents the midpoint between the edge of feature 204b and the opposite edge of feature 204 b. Centerline 208c represents the midpoint between an edge of feature 204c and the opposite edge of feature 204 c. As can be seen, the centerlines 208a, 208b, 208c are not aligned with the grid 202.

Fig. 2C is a diagram showing centerlines 208a, 208b, 208C aligned with the grid 202. The centerlines 208a, 208b, 208c and the respective features 204a, 204b, 204c are adjusted together to align with the grid in accordance with the process 110 described above. In this example, feature 204a is moved in a first direction 205 to align with grid 202. In addition, features 204b and 204c move in second direction 207 to align with grid 202. The first direction 205 is opposite the second direction 207. In some embodiments, the distance of movement of the features 204a, 204b, and 204c may be different from each other and less than the minimum resolution size (e.g., width of a cell) of the e-beam lithography tool. As can be seen in fig. 2C, the centerlines 208a, 208b, 208C are now aligned with the grid. However, the outer edges of the features are not aligned with the grid. Thus, if a fracturing procedure is applied at this time, the feature will not be truncated.

Fig. 2D is a diagram showing the sizes of the features 204a, 204b, 204c adjusted to match the grid 202. The critical dimensions of the features 204a, 204b, 204c are adjusted according to the process 112 described above. In this example, each of the features 204a, 204b, 204c is critical-dimensionally extended such that its edges are aligned with the grid 202. However, in some examples, each of the features 204a, 204b, 204c may be reduced in critical dimension such that its edges are aligned with the grid 202. Undesired or undesired truncation during the fracturing procedure may be avoided by aligning the outer edges of the grid.

Fig. 3A, 3B, 3C, and 3D are diagrams showing a procedure for aligning first features of a first shrink pattern with second features of a second shrink pattern. Fig. 3A illustrates a first feature 302 associated with a first pattern and a second feature 304 associated with a second pattern before a shrink procedure is applied. In some examples, the first pattern may be referred to as a host pattern and the second pattern may be referred to as a reference pattern. In one example, the main pattern may correspond to a polysilicon gate pattern layer, and the reference pattern may correspond to a source/drain pattern. Before the shrink program is applied, the edge 307 of the second feature 304 is aligned with the edge 305 of the first feature 302. In some examples, the two edges 305, 307 may also be aligned with the grid 306.

In some examples, grid 306 may have cells corresponding to a minimum resolution of an e-beam lithography tool. However, in some examples, grid 306 may be independent of a minimum resolution of the e-beam lithography tool. Rather, the grid 306 may be defined by a designer and used to align the edges of the features together in a consistent manner.

Fig. 3B shows two scenarios 301, 303 after the shrink process. In both schemes 301 and 303, the edge 307 of the second feature 304 is no longer aligned with the edge 305 of the first feature 302. In the first scheme 301, misaligned edge 307 has not reached edge 305. In the second scheme 303, edge 307 extends beyond edge 305.

FIG. 3C illustrates the relationship between the defined edges 305 and 307. In the first scheme 301, a relationship 308 is defined between edge 307 and edge 305. Similarly, in scenario 303, relationship 310 is defined between edge 307 and edge 305.

FIG. 3D illustrates adjusting the position of edge 307 to align with edge 305. Specifically, in scenario 301, edge 307 is moved in first direction 312 by a distance corresponding to relationship 308. In scenario 303, edge 307 is moved in a second direction 314 by a distance corresponding to relationship 310. In this example, edge 307 is adjusted without adjusting feature 304. In other words, the width of the feature 304 is reduced rather than horizontally translating the feature. By adjusting all of the features in this manner, the critical dimensions of the features 302 and 304 may be more consistent.

FIG. 4 is a flow chart showing a pictorial method 400 for generating consistent critical dimensions of shrink patterns by bringing the centerlines into registration with the grid. According to the present example, the method 400 includes a program 402 for receiving a pattern layout of a mask. The pattern layout may correspond to the pattern layout 102 described in fig. 1. The pattern layout may be for one of several layers of an integrated circuit. For example, the pattern layout may be used for a polysilicon gate layer. In another example, the pattern layer may be used for a source/drain layer or an active area layer.

The method 400 further includes a procedure 404 for shrinking the pattern layout to form a shrunk pattern. The shrink procedure reduces the size of the pattern layout to a slightly smaller size. This can be used, for example, to produce a slightly smaller integrated circuit. The shrinking procedure results in shrinking the pattern. The layout of the shrink pattern is identical to the pattern layout, however, its size is smaller. In one example, the shrink pattern is 98% of the size of the pattern layout. In an example, the shrink pattern has a size within about 95% to about 99% of the size of the pattern layout.

The method 400 further includes a program 406 for determining a centerline (e.g., 208a, 208b, 208c) for each of a plurality of features within the shrink pattern. For example, the features within the shrink pattern may be long polygonal features. These features may correspond to, for example, gate devices. The centerline may extend longitudinally along the long polygonal feature.

The method 400 further includes a routine 408 for aligning a centerline of each of the plurality of features with a grid having cells representing a minimum resolution size of the mask fabrication tool. The grid may be designed such that each cell of the grid corresponds to a minimum resolution size of an electron beam lithography tool to be used for manufacturing a mask for the shrink pattern. The position of each feature associated with the centerline is adjusted by aligning the centerline with the grid. In some examples, some features move in one direction while other features move in the opposite direction.

The method 400 further includes a procedure 410 for fabricating a mask. The mask may be fabricated using an electron beam lithography tool. The fabricated mask may then be used in production to fabricate integrated circuits. More details of mask fabrication will be discussed below in conjunction with fig. 6.

Fig. 5 is a flow diagram showing a diagrammatic method 500 for generating consistent critical dimensions for a shrink pattern by aligning edges of features of the shrink pattern with edges of features of another pattern. The method 500 includes a procedure 502 for receiving a first pattern for fabricating a first mask. The method 500 further includes a procedure 504 for receiving a second pattern for fabricating a second mask. In some examples, the first pattern may be referred to as a host pattern and the second pattern may be referred to as a reference pattern. In one example, the main pattern may correspond to a polysilicon gate pattern, and the reference pattern may correspond to a source/drain pattern.

The method 500 further includes a procedure 506 for aligning a first feature (e.g., 302) of the first pattern with a second feature (e.g., 304) of the second pattern. For example, an edge (e.g., 307) of the second feature (e.g., 304) is aligned with an edge (e.g., 305) of the first feature (e.g., 302). In some examples, both edges may also be aligned with a grid (e.g., 306).

The method 500 further includes a procedure 508 for shrinking the first pattern and the second pattern after the aligning to form a first shrunk pattern and a second shrunk pattern. This can be used, for example, to produce a slightly smaller integrated circuit. The shrink program results in a first shrink pattern and a second shrink pattern. The layout of the shrink pattern is the same as the first and second patterns, but smaller in size. In one example, the shrunk pattern is 98% of the size of the original pattern. In one example, the shrunk pattern has a size that is within about 95% to about 99% of the size of the original pattern. Other size ranges are contemplated.

The method 500 further includes a program 510 for adjusting an edge of the second feature to match an edge of the first feature in response to determining that the first feature is no longer aligned with the second feature. For example, the edge of the second feature may be adjusted without adjusting the second feature itself.

The method 500 further includes a procedure 512 for fabricating a first mask using the first shrink pattern and a second mask using the second shrink pattern. The mask may be fabricated using an electron beam lithography tool. The fabricated mask may then be used in production to fabricate integrated circuits. More details of mask fabrication will be discussed below in conjunction with fig. 6.

Fig. 6 is a flow chart showing an illustrative mask process. For example, fig. 6 depicts an example of an Integrated Circuit (IC) manufacturing system 600 and its associated IC manufacturing flow, which may be used to fabricate masks using the above-described procedure. The IC manufacturing system 600 comprises a plurality of entities, such as a design room 620, a mask shop 630 and an IC manufacturing factory 650 (i.e., a wafer shop), that interact with each other in the design, development and manufacturing cycles and/or services associated with manufacturing Integrated Circuit (IC) devices 650. Multiple entities are connected by a communication network, which may be a single network or a variety of different networks (e.g., an intranet and the internet) and may include wired and/or wireless communication channels. Each entity may interact with and may provide services to and/or receive services from other entities. One or more of the design chamber 620, the mask factory 630, and the IC fab 650 may be owned by a single larger company, and may even co-exist in a common facility and use common resources.

A design room (or design team) 620 generates an IC design layout 622. The IC design layout 622 includes various geometric patterns designed for the IC device 650. The geometric pattern corresponds to the pattern of the metal, oxide, or semiconductor layers that make up the various components of the IC device 650 to be fabricated. The various layers combine to form various IC components. For example, a portion of the IC design layout 622 includes various IC components such as active areas, gate electrodes, source and drain, metal lines or vias for inter-level interconnects, and openings for bond pads formed in a semiconductor substrate (e.g., a silicon wafer) and various layers of materials disposed on the semiconductor substrate. The design chamber 620 implements an appropriate design procedure to form an IC design layout 622. The design process may include logical design, physical design, and/or placement and routing. The IC design layout 622 is presented in one or more data files having information of geometric patterns. For example, the IC design layout 622 may be expressed in a GDSII file format or a DFII file format.

The mask shop 630 uses the IC design layout 622 to fabricate one or more masks for fabricating the various layers of the IC device 650 according to the IC design layout 622. Mask factory 630 performs mask data preparation 632 (where IC design layout 622 is translated into a form that can be physically exposed by a mask exposer) and mask manufacturing 634 (where the design layout prepared by mask data preparation 632 is modified to comply with a particular mask exposer and/or mask manufacturing factory and then a mask is manufactured.) in this embodiment, mask data preparation 632 and mask manufacturing 634 are depicted as separate components, however, mask data preparation 632 and mask manufacturing 634 may be collectively referred to as mask data preparation.

Mask data preparation 632 typically includes Optical Proximity Correction (OPC) using lithographic enhancement techniques to compensate for image errors, such as image errors attributable to diffraction, interference, or other procedural effects. For example, OPC can adjust line width depending on the density of surrounding geometry, add "dog bone" terminations back to line ends to prevent line end shortening, or correct for electron beam (e-beam) proximity effects. OPC can add assist features such as scatter bars, serifs, and/or hammerheads to the IC design layout 622 based on optical models or rules so that the final pattern on the wafer is improved with increased resolution and accuracy after the photolithography process. Mask data preparation 632 may further include Resolution Enhancement Techniques (RET), such as off-axis illumination, sub-resolution assist features, phase shift masks, other suitable techniques, or combinations thereof. A technique that may be used with OPC is the reflective lithography technique (ILT), which treats OPC as an anti-imaging problem. In some cases, the ILT generates non-intuitive mask patterns, such as from (or arbitrarily shaped) patterns.

Mask data preparation 632 further includes a Mask Rule Checker (MRC) that checks the IC design layout that has been subjected to the procedure in OPC using a set of mask generation rules that may contain specific geometry and connection constraints to ensure adequate margins, account for semiconductor process variability, and so forth. In some cases, the MRC modifies the IC design layout to compensate for constraints during mask manufacturing 634, which may undo the partial modifications performed by OPC to meet mask generation rules. For example, the MRC may perform a Manhattan (Manhattan) transformation to transform the curved ideal mask from the ILT to a zigzag polygon pattern to comply with mask generation rules. In one example, the manhattan transform limits the output pattern edges to horizontal or vertical to accommodate the e-beam mask writer. Thus, it can produce extended periods and step sizes that suffer from long run times in mask manufacturing 634. Mask data preparation 632 may further include photolithography program inspection (LPC), which simulates the processing to be performed by the IC fab 650 to fabricate the IC device 650. The LPC models such processing based on the IC design layout 622 to produce a simulated fabrication device such as IC device 650. The process parameters of the LPC simulation may include parameters associated with various procedures of the IC fabrication cycle, parameters associated with the tool used to fabricate the IC, and/or other aspects of the process. LPC considers various factors such as aerial image contrast, depth of field ("DOF"), mask error magnification factor ("MEEF"), other suitable factors, or a combination thereof.

After the simulated fabrication devices are generated by the LPC, if the shapes of the simulated devices are not close enough to satisfy the design rules, certain steps in the mask data preparation 632 (such as OPC and MRC) may be repeated to further refine the IC design layout 622.

It should be appreciated that the above description of mask data preparation 632 has been simplified for clarity, and that data preparation may include additional features such as Logic Operations (LOPs) to modify an IC design layout according to manufacturing rules. In addition, the procedures applied to the IC design layout 622 during the data preparation 632 may be performed in a variety of different orders.

After mask data preparation 632 and during mask fabrication 634, a mask or a group of masks is fabricated based on the modified IC design layout. This may be done at manufacturing facility 640. For example, an electron beam (e-beam) or multiple electron beams mechanism is used to form a pattern on a mask (reticle or reticle) based on a modified IC design layout. The mask may be formed by various techniques. In one embodiment, the mask is formed using a binary technique. In the present embodiment, the mask pattern includes opaque regions and transparent regions. The radiation beam (e.g., an Ultraviolet (UV) beam) used to expose the image sensitive material layer (e.g., photoresist) applied to wafer 642 is blocked by the opaque regions and transmitted through the transparent regions. In one example, a binary mask includes a transparent substrate (e.g., fused silica) and an opaque material (e.g., chrome) applied in opaque regions of the mask. In another example, a phase shift technique is used to form the mask. In a Phase Shift Mask (PSM), various features in a pattern formed on the mask are configured to have appropriate phase differences to improve resolution and imaging quality. In various examples, the phase shift mask may be an attenuating PSM or an alternating PSM.

An IC fab 650, such as a foundry, manufactures the IC devices 650 using the mask (or masks) manufactured by the mask fab 630. An IC fab 650 is an IC manufacturing enterprise that may contain various manufacturing facilities for manufacturing various different IC products. For example, there may be a manufacturing facility for front end of line (i.e., front end of line (FEOL) manufacturing) of a plurality of IC products, while a second manufacturing facility may provide interconnect and back end of package (i.e., back end of line (BEOL) manufacturing) for IC products, and a third manufacturing facility may provide other services for a foundry. In this embodiment, a mask (or masks) is used to fabricate a semiconductor wafer to form the IC device 650. A semiconductor wafer comprises a silicon substrate or other suitable substrate having a layer of material formed thereon. Other suitable substrate materials include: another suitable elemental semiconductor (e.g., diamond or germanium); suitable compound semiconductors, such as silicon carbide, indium arsenide, or indium phosphide; or a suitable alloy semiconductor such as silicon germanium carbide, gallium arsenic phosphide or gallium indium phosphide. The semiconductor wafer may further comprise various doped regions, dielectric members, and multilevel interconnects (formed in subsequent fabrication steps). Masks may be used in a variety of procedures. For example, the mask may be used in an ion implantation procedure to form various doped regions in a semiconductor wafer, in an etching procedure to form various etched regions in a semiconductor wafer, and/or in other suitable procedures.

FIG. 7 is a diagram showing a illustrative computing system for generating uniform critical dimensions. According to a particular illustrative example, the physical computing system 700 includes a memory 702 having stored thereon software 704 and data 706. The physical computing system 700 also includes a processor 708 and a user interface 710.

There are many types of memory available. Some types of memory (e.g., solid state drives) are designed for storage. These types of memories typically have large storage capacities but are relatively slow in performance. Other types of memory, such as memory used for Random Access Memory (RAM), are optimized for speed and are commonly referred to as "working memory. Various forms of memory may store information in the form of software 704 and data 706. The data 706 may include a digital representation of the pattern layout 102 and the shrink pattern 106 (as depicted in FIG. 1). The software 704 may include machine readable instructions for executing the programs described herein, such as programs 100, 400, or 500.

The physical computing system 700 also includes a processor 708 for executing the software 704 and using or updating the data 706 stored in the memory 702. In addition to storing software 704, memory 702 may also store an operating system. The operating system allows other applications to properly interact with the hardware of the physical computing system.

User interface 710 may provide a means for user 712 to interact with the system. User 712 may use various tools, such as a keyboard or mouse, to enter information into the physical computing system. In addition, various output devices, such as a monitor, may be used to provide information to user 712. The user may enter various data, such as constraints associated with the target pattern, to generate the target pattern space 107.

According to an example, a method comprises: receiving a pattern layout of a mask; shrinking the pattern layout to form a shrunk pattern; determining a centerline of each of a plurality of features within the contraction pattern; and aligning the centerline of each of the plurality of features with a grid. The grid represents the minimum resolution size of the mask manufacturing tool. The method further comprises: after aligning the centerline of each of the plurality of features with the grid, the mask is fabricated using the shrink pattern.

According to an example, a method comprises: receiving a first pattern for fabricating a first mask; receiving a second pattern for fabricating a second mask; aligning first features of the first pattern with second features of the second pattern; and after the aligning, shrinking the first pattern and the second pattern to form a first shrunk pattern and a second shrunk pattern. The method further comprises: adjusting an edge of the second feature to match an edge of the first feature in response to determining that the first feature is no longer aligned with the second feature. The method further comprises: fabricating the first mask using the first shrink pattern and fabricating the second mask using the second shrink pattern.

According to an example, a computer readable medium comprises machine readable instructions which, when executed by a processor, cause a system to: receiving a mask pattern for fabricating a layer in an integrated circuit; shrinking the mask pattern to form a shrunk pattern; identifying a centerline of a feature of the shrink pattern; aligning the centerline of the feature with a grid representing a minimum resolution size of a mask manufacturing tool; and adjusting the critical dimension of the feature to be an integer multiple of the minimum resolution size of the mask fabrication tool.

The foregoing has outlined features of several embodiments so that those skilled in the art may better understand the aspects of the disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Description of the symbols

100 method

102 pattern layout/pattern layer

104 shrink procedure

106 shrinkage pattern

107 target pattern space

108 procedure

110 procedure

112 procedure

114 procedure

202 grid

203 unit

204a characteristic

204b characteristic

204c characteristic

205 first direction

206 critical dimension

207 second direction

208a center line

208b center line

208c center line

301 scheme

302 first feature

303 scheme

304 second characteristic

305 edge

306 grid

307 edge

308 relationship

310 relationship

312 first direction

314 second direction

400 method

402 procedure

404 procedure

406 procedure

408 program

410 procedure

500 method

502 procedure

504 procedure

506 procedure

508 procedure

510 procedure

512 procedure

600 Integrated Circuit (IC) manufacturing System

620 design room

622 IC design layout

630 mask factory

632 mask data preparation

634 mask fabrication

640 manufacturing facility

642 wafer

650 IC manufacturer/IC device

700 physical computing system

702 memory

704 software

706 data

708 processor

710 user interface

712 user