Pulse clock generation circuit, integrated circuit, and pulse clock generation method
阅读说明:本技术 脉冲时钟产生电路、集成电路及脉冲时钟产生方法 (Pulse clock generation circuit, integrated circuit, and pulse clock generation method ) 是由 任丛飞 于 2019-11-05 设计创作,主要内容包括:本发明实施例提供一种脉冲时钟产生电路、集成电路及脉冲时钟产生方法。该脉冲时钟产生电路包括逻辑门电路、反相器及脉冲宽度控制电路。逻辑门电路用于在时钟输入信号的驱动下,输出门控信号。反相器与逻辑门电路连接,并用于在门控信号的驱动下,输出脉冲时钟信号。脉冲宽度控制电路接入于逻辑门电路与反相器之间,用于在门控信号的控制下,输出脉冲宽度控制信号并反馈回逻辑门电路,以调节脉冲时钟信号。本发明实施例的脉冲时钟产生电路及脉冲时钟产生方法能够输出具有稳定宽度的脉冲时钟信号。(The embodiment of the invention provides a pulse clock generating circuit, an integrated circuit and a pulse clock generating method. The pulse clock generating circuit comprises a logic gate circuit, an inverter and a pulse width control circuit. The logic gate circuit is used for outputting a gating signal under the driving of a clock input signal. The inverter is connected with the logic gate circuit and used for outputting a pulse clock signal under the driving of the gating signal. The pulse width control circuit is connected between the logic gate circuit and the inverter and used for outputting a pulse width control signal under the control of the gate control signal and feeding back the pulse width control signal to the logic gate circuit so as to adjust the pulse clock signal. The pulse clock generating circuit and the pulse clock generating method can output the pulse clock signal with stable width.)
1. A pulse clock generating circuit, comprising:
the logic gate circuit is used for outputting a gate control signal under the driving of a clock input signal;
the inverter is connected with the logic gate circuit and is used for outputting a pulse clock signal under the driving of the gating signal;
and the pulse width control circuit is connected between the logic gate circuit and the inverter and used for outputting a pulse width control signal under the control of the gate control signal and feeding back the pulse width control signal to the logic gate circuit so as to adjust the pulse clock signal.
2. The pulse clock generation circuit of claim 1, further comprising:
and the feedback signal control circuit is respectively connected with the pulse width control circuit and the logic gate circuit and is used for feeding back an output feedback signal to the logic gate circuit under the control of the pulse width control signal and the clock input signal so as to stabilize the pulse width of the pulse clock signal.
3. The pulse clock generating circuit as claimed in claim 2, wherein the feedback signal control circuit has a first terminal for receiving the clock input signal, a second terminal for receiving the pulse width control signal, and a third terminal for feeding the feedback signal back to the logic gate circuit, and the feedback signal control circuit includes a first MOS transistor and a second MOS transistor, the first MOS transistor is a PMOS transistor, and the second MOS transistor is an NMOS transistor, wherein the gate of the first MOS transistor is connected to the first terminal, the source of the first MOS transistor is connected to the power supply, the drain of the first MOS transistor is connected to the drain of the second MOS transistor and to the third terminal, the gate of the second MOS transistor is connected to the second terminal, and the source of the second MOS transistor is grounded.
4. The pulse clock generating circuit according to claim 3, wherein the feedback signal control circuit further comprises a self-feedback circuit connected between the first terminal and the third terminal, wherein the self-feedback circuit outputs a self-feedback signal and feeds back to the third terminal when the clock input signal changes, so that the feedback signal output from the third terminal is stabilized.
5. The pulse clock generating circuit according to claim 4, wherein the self-feedback circuit comprises a third MOS transistor, a fourth MOS transistor and an inverter circuit, wherein a gate of the third MOS transistor is connected to the third terminal through the inverter circuit, a drain of the third MOS transistor is connected to the third terminal, a source of the third MOS transistor is connected to a drain of the fourth MOS transistor, a gate of the fourth MOS transistor is connected to the first terminal, a source of the fourth MOS transistor is grounded, and when the feedback signal output from the third terminal changes from a high level to a low level, the third MOS transistor and the fourth MOS transistor are turned on.
6. The pulse clock generating circuit as claimed in claim 5, wherein said third MOS transistor and said fourth MOS transistor are NMOS transistors.
7. The pulse clock generating circuit as claimed in claim 5, wherein the inverter circuit includes a fifth MOS transistor and a sixth MOS transistor, the fifth MOS transistor is a PMOS transistor, the sixth MOS transistor is an NMOS transistor, a gate of the fifth MOS transistor is connected to a gate of the sixth MOS transistor and to the third terminal, a source of the fifth MOS transistor is connected to the power supply, a drain of the fifth MOS transistor is connected to a drain of the sixth MOS transistor, and a source of the sixth MOS transistor is grounded.
8. The pulse clock generating circuit as claimed in claim 5, wherein the feedback signal control circuit further comprises a seventh MOS transistor and an eighth MOS transistor for stabilizing the feedback signal at the third terminal, a gate of the seventh MOS transistor is connected to the third terminal through the inverter circuit, a source of the seventh MOS transistor is connected to a drain of the eighth MOS transistor, a drain of the seventh MOS transistor is connected to the third terminal, a gate of the eighth MOS transistor is connected to the second terminal, a source of the eighth MOS transistor is connected to the power supply, and a source of the first MOS transistor is connected to a drain of the eighth MOS transistor and is connected to the power supply through the eighth MOS transistor.
9. The pulse clock generating circuit as claimed in claim 8, wherein said seventh MOS transistor and said eighth MOS transistor are PMOS transistors.
10. The pulse clock generation circuit of claim 1, wherein the logic gate circuit comprises a nand gate; and the pulse width control circuit includes an odd number of inverters connected in series.
11. An integrated circuit comprising the pulse clock generation circuit of any one of claims 1 to 10 and a pulse latch connected to the pulse clock generation circuit, the pulse clock generation circuit being configured to provide the generated pulse clock signal to the pulse latch.
12. A pulse clock generating method, comprising:
receiving a clock input signal through a logic gate circuit, and outputting a gating signal under the driving of the clock input signal;
receiving the gating signal through an inverter, and outputting a pulse clock signal under the driving of the gating signal;
and receiving the gate control signal through a pulse width control circuit, outputting a pulse width control signal under the control of the gate control signal, and feeding back the pulse width control signal to the logic gate circuit so as to adjust the pulse clock signal.
13. The pulse clock generating method according to claim 12, further comprising:
and receiving the pulse width control signal and the clock input signal through a feedback signal control circuit, outputting a feedback signal under the control of the pulse width control signal and the clock input signal, and feeding back the output feedback signal to the logic gate circuit so as to stabilize the pulse width of the pulse clock signal.
Technical Field
The embodiment of the invention relates to the technical field of clock circuits, in particular to a pulse clock generating circuit, an integrated circuit and a pulse clock generating method.
Background
A Pulse Latch (Pulse Latch) is a memory cell circuit sensitive to a Pulse signal, and can change states under the action of a specific Pulse clock signal. In a circuit which has high requirements for speed and power consumption, a pulse latch is adopted, so that the circuit can be simplified, and dynamic power consumption can be effectively reduced in a CPU (central processing unit), and therefore, the pulse latch is generally applied to the circuit.
The pulse latch inputs a pulse clock signal, the pulse clock signal with stable width is the basis of the application of the pulse latch, and the design of the pulse clock generating circuit determines the waveform quality and the application range of the pulse clock signal. Therefore, the design of the pulse clock generation circuit plays a crucial role for the entire circuit.
Fig. 1 shows a circuit diagram of a conventional pulse
Therefore, how to improve the quality of the pulse waveform is an important consideration in designing the pulse clock generation circuit.
Disclosure of Invention
An embodiment of the invention provides a pulse clock generating circuit, an integrated circuit and a pulse clock generating method for generating a pulse clock signal with a stable width.
One aspect of the embodiments of the present invention provides a pulse clock generating circuit including a logic gate circuit, an inverter, and a pulse width control circuit. The logic gate circuit is used for outputting a gating signal under the driving of a clock input signal. The inverter is connected with the logic gate circuit and used for outputting a pulse clock signal under the driving of the gating signal. The pulse width control circuit is connected between the logic gate circuit and the inverter and used for outputting a pulse width control signal under the control of the gate control signal and feeding back the pulse width control signal to the logic gate circuit so as to adjust the pulse clock signal.
Further, the pulse clock generation circuit further comprises a feedback signal control circuit. The pulse width control circuit is respectively connected with the pulse width control circuit and the logic gate circuit and is used for feeding back an output feedback signal to the logic gate circuit under the control of the pulse width control signal and the clock input signal so as to stabilize the pulse width of the pulse clock signal.
Further, the feedback signal control circuit has a first end for receiving the clock input signal, a second end for receiving the pulse width control signal, and a third end for feeding the feedback signal back to the logic gate circuit, and the feedback signal control circuit includes a first MOS transistor and a second MOS transistor, where the first MOS transistor is a PMOS transistor and the second MOS transistor is an NMOS transistor, a gate of the first MOS transistor is connected to the first end, a source of the first MOS transistor is connected to the power supply, a drain of the first MOS transistor is connected to a drain of the second MOS transistor and to the third end, a gate of the second MOS transistor is connected to the second end, and a source of the second MOS transistor is grounded.
Further, the feedback signal control circuit further includes a self-feedback circuit, and the self-feedback circuit is connected between the first terminal and the third terminal, wherein when the clock input signal changes, the self-feedback circuit outputs a self-feedback signal and feeds back the self-feedback signal to the third terminal, so that the feedback signal output by the third terminal is stable.
Further, the self-feedback circuit comprises a third MOS transistor, a fourth MOS transistor and an inverter circuit, wherein a gate of the third MOS transistor is connected to the third terminal through the inverter circuit, a drain of the third MOS transistor is connected to the third terminal, a source of the third MOS transistor is connected to a drain of the fourth MOS transistor, a gate of the fourth MOS transistor is connected to the first terminal, a source of the fourth MOS transistor is grounded, and when the feedback signal output from the third terminal changes from a high level to a low level, the third MOS transistor is connected to the fourth MOS transistor.
Further, the third MOS transistor and the fourth MOS transistor are NMOS transistors.
Furthermore, the inverter circuit comprises a fifth MOS tube and a sixth MOS tube, the fifth MOS tube is a PMOS tube, the sixth MOS tube is an NMOS tube, the grid electrode of the fifth MOS tube is connected with the grid electrode of the sixth MOS tube and is connected to the third end, the source electrode of the fifth MOS tube is connected to the power supply, the drain electrode of the fifth MOS tube is connected with the drain electrode of the sixth MOS tube, and the source electrode of the sixth MOS tube is grounded.
Further, the feedback signal control circuit further comprises a seventh MOS transistor and an eighth MOS transistor for stabilizing the feedback signal at the third end, a gate of the seventh MOS transistor is connected to the third end through the inverter circuit, a source of the seventh MOS transistor is connected to a drain of the eighth MOS transistor, the drain of the seventh MOS transistor is connected to the third end, a gate of the eighth MOS transistor is connected to the second end, a source of the eighth MOS transistor is connected to the power supply, and a source of the first MOS transistor is connected to the drain of the eighth MOS transistor and is connected to the power supply through the eighth MOS transistor.
Further, the seventh MOS transistor and the eighth MOS transistor are PMOS transistors.
Further, the logic gate circuit comprises a nand gate; and the pulse width control circuit includes an odd number of inverters connected in series.
Another aspect of the embodiments of the present invention also provides an integrated circuit, which includes the pulse clock generating circuit as described above and a pulse latch connected to the pulse clock generating circuit, where the pulse clock generating circuit is configured to provide the generated pulse clock signal to the pulse latch.
Compared with the conventional pulse clock generating circuit in which the start point of the feedback loop is connected to the output terminal of the pulse clock signal, the pulse clock generating circuit and the integrated circuit having the same according to the embodiments of the present invention modify the start point of the feedback loop from the output terminal of the pulse clock signal to the previous node of the pulse clock signal by connecting the start point of the feedback loop between the logic gate circuit and the inverter, and since the load of the previous node is only the inverter and the pulse width control circuit connected thereto, the load size is not substantially changed, and therefore, even if the load connected to the pulse clock signal is changed, the previous node is hardly affected by the previous node, and therefore, the previous node is used as the start point of the feedback signal, and is not affected by the change in the load connected to the pulse clock signal, that is, the level of the gate signal is kept stable, and the pulse clock signal output based on the previous node is kept stable, therefore, the effect of stabilizing the pulse width of the output pulse clock signal is achieved.
Yet another aspect of the embodiments of the present invention also provides a pulse clock generating method. The pulse clock generation method comprises the following steps: receiving a clock input signal through a logic gate circuit, and outputting a gating signal under the driving of the clock input signal; receiving the gating signal through an inverter, and outputting a pulse clock signal under the driving of the gating signal; and receiving the gate control signal through a pulse width control circuit, outputting a pulse width control signal under the control of the gate control signal, and feeding back the pulse width control signal to the logic gate circuit so as to adjust the pulse clock signal.
Further, the pulse clock generation method further includes: and receiving the pulse width control signal and the clock input signal through a feedback signal control circuit, outputting a feedback signal under the control of the pulse width control signal and the clock input signal, and feeding back the output feedback signal to the logic gate circuit so as to stabilize the pulse width of the pulse clock signal.
According to the pulse clock generation method provided by the embodiment of the invention, the starting point of the feedback loop is connected with the gating signal, and the gating signal is hardly influenced by the load change connected with the pulse clock signal, so that the gating signal is used as the starting point of the feedback signal and is not influenced by the load change connected with the pulse clock signal, namely, the level of the gating signal is kept stable, and further, the pulse clock signal output based on the gating signal is kept stable, so that the effect of stabilizing the pulse width of the output pulse clock signal is achieved.
Drawings
FIG. 1 is a circuit diagram of a conventional pulse clock generating circuit;
FIG. 2 is a waveform diagram associated with the pulse clock generating circuit shown in FIG. 1;
FIG. 3 is a general block diagram of a pulse clock generation circuit according to one embodiment of the invention;
FIG. 4 is a circuit diagram of a pulse clock generating circuit according to an embodiment of the present invention;
FIG. 5 is a circuit diagram of a feedback signal control circuit according to an embodiment of the present invention;
FIG. 6 is a graph showing a comparison of simulation effects of the pulse clock generation circuit of FIG. 4 of the present invention and a conventional pulse clock generation circuit;
fig. 7 is a graph showing a comparison of simulation effects of the pulse clock generation circuit shown in fig. 4 of the present invention and the conventional pulse clock generation circuit after changing the load to which the pulse clock signal PCLK is connected.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present invention. Rather, they are merely examples of apparatus consistent with certain aspects of the invention, as detailed in the appended claims.
The terminology used in the embodiments of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. Unless otherwise defined, technical or scientific terms used in the embodiments of the present invention should have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. The use of "first," "second," and similar terms in the description and in the claims does not indicate any order, quantity, or importance, but rather is used to distinguish one element from another. Also, the use of the terms "a" or "an" and the like do not denote a limitation of quantity, but rather denote the presence of at least one. "plurality" or "a number" means two or more. Unless otherwise indicated, "front", "rear", "lower" and/or "upper" and the like are for convenience of description and are not limited to one position or one spatial orientation. The word "comprising" or "comprises", and the like, means that the element or item listed as preceding "comprising" or "includes" covers the element or item listed as following "comprising" or "includes" and its equivalents, and does not exclude other elements or items. The terms "connected" or "coupled" and the like are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. As used in this specification and the appended claims, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
Fig. 3 discloses a general block diagram of the pulse
Compared with the conventional pulse clock generating circuit in which the start point of the feedback loop is connected to the output terminal of the pulse clock signal, the pulse
Fig. 4 discloses a circuit diagram of the pulse
In some embodiments, the pulse
Of course, in other embodiments, the pulse
Continuing to refer to fig. 4, in some embodiments, pulse
The pulse
Fig. 5 discloses a circuit diagram of the feedback
The feedback
In some embodiments, the self-
In some embodiments, the third MOS transistor nch2 and the fourth MOS transistor nch3 are both NMOS transistors.
As shown in fig. 4, when the clock input signal CLK is at a low level, the output gate signal pclk _ n is at a high level, the pulse width control signal n1 is at a low level, and since the clock input signal CLK is at a low level, the first MOS transistor pch1 in fig. 5 is turned on, since the source of the first MOS transistor pch1 is connected to the power Vcc, and the drain of the first MOS transistor pch1 is connected to the third terminal A3, based on the basic principle of the PMOS transistor, it can be known that the feedback signal nclk output from the third terminal A3 is at a high level. When the clock input signal CLK switches from the low level to the high level, the feedback signal nclk output by the feedback
In other embodiments, the gate of the third MOS transistor nch2 and the gate of the fourth MOS transistor nch3 may also be controlled by separate driving circuits or by other level signals. One or both of the third MOS transistor nch2 and the fourth MOS transistor nch3 may also take the form of PMOS transistors. The invention is not limited to this, but the circuit form in which the third MOS transistor nch2 and the fourth MOS transistor nch3 are turned on when the level signal of the third terminal a3 changes from high level to low level is within the protection scope of the invention.
The feedback
Referring to fig. 5, in some embodiments, the
In some embodiments, the feedback
In some embodiments, the seventh MOS transistor pch3 and the eighth MOS transistor pch4 are both PMOS transistors.
In other embodiments, the gate of the seventh MOS transistor pch3 and the gate of the eighth MOS transistor pch4 may be controlled by separate driving circuits or by other signal levels. One or both of the seventh MOS transistor pch3 and the eighth MOS transistor pch4 may also take the form of NMOS transistors. The present invention is not limited to this, but any circuit form that can realize that the seventh MOS transistor pch3 and the eighth MOS transistor pch4 are turned on when the clock input signal CLK changes from a low level to a high level is within the scope of the present invention.
Referring to fig. 4 and 5, the following is a timing variation process of the pulse
When the clock input signal CLK is at a low level, as shown in fig. 4, the gate control signal PCLK _ n is at a high level, and the pulse clock signal PCLK and the pulse width control signal n1 at the output terminal OUT are at a low level, so that the second MOS transistor nch1 and the fourth MOS transistor nch3 in fig. 5 are turned off, the first MOS transistor pch1 and the eighth MOS transistor pch4 are turned on, so that it can be obtained that the feedback signal nclk output by the feedback signal control circuit 34 is at a high level, since the nclk is at a high level, the sixth MOS transistor nch4 is turned on, the fifth MOS transistor pch2 is turned off, the inverter circuit 342 outputs a low level, so that the third MOS transistor nch2 is turned off, the seventh MOS transistor pch3 is turned on, since both pch1 and pch4 are turned on, so that the drain of the first MOS transistor pch1 is at a high level, that the feedback signal 737 at the third terminal A3 connected to the drain of the pch3 is at a high level, and the reference signal CLK is at this time, since the reference signal PCLK at the high level, the input signal PCLK is at this time, the input level of the reference signal PCLK 4, thereby keeping the pulse clock signal PCLK at the output terminal OUT at a low level.
When the clock input signal CLK is switched from low to high, because the level switching requires time, the circuit shown in fig. 5 does not respond in time, and therefore the feedback signal nclk of the feedback signal control circuit 34 still maintains a high level, according to fig. 4, because the feedback signal nclk of the feedback signal control circuit 34 is still at a high level and the pulse width control signal n1 is still at a low level, the pulse clock signal PCLK _ n in fig. 4 changes from a high level to a low level because the clock input signal CLK and the feedback signal nclk are both at a high level, and the gate control signal PCLK _ n in fig. 4 changes from a high level to a low level, and the pulse clock signal PCLK in fig. 4 changes from a low level to a high level; in addition, since the clock input signal CLK is at a high level, the first MOS transistor pch1 in fig. 5 is turned off, the fourth MOS transistor nch3 is turned on, but since the pulse width control signal n1 is at a low level, states of the other devices in fig. 5 are maintained unchanged, and since the eighth MOS transistor pch4 and the seventh MOS transistor pch3 are still in a turned-on state, the feedback signal nclk output by the feedback signal control circuit 34 can be better maintained at a high level, and a floating state of the existing pulse signal generating circuit at this time does not occur. Since the feedback signal nclk is maintained at a high level and the clock input signal CLK is at a high level, the pulse clock signal PCLK at the output terminal OUT can be maintained at a high level, and thus a stable pulse clock signal is formed, i.e., the pulse width of the pulse clock signal is stabilized.
When the
When the clock input signal CLK is switched from low to high and then causes the pulse width control signal n1 in fig. 4 to turn over from low to high after a delay, as described above, the second MOS transistor nch1 in fig. 5 is turned on, the eighth MOS transistor pch4 is turned off, the level of the feedback signal nclk rapidly falls after the pulse width control signal n1 turns over from low to high, during the falling of the feedback signal nclk, the fifth MOS transistor pch2 is turned on, the sixth MOS transistor nch4 is turned off, the output of the
When the feedback signal nclk changes to a low level, the gate control signal pclk _ n output by the
When the gating signal pclk _ n in fig. 4 is inverted from a low level to a high level and then delayed by the pulse
When the clock input signal CLK switches from high level to low level, the state of the
In summary, the pulse signal generating circuit in fig. 5 achieves an accelerated drop of the level of the feedback signal nclk during the process of changing from high to low, so that the speed of the pulse clock signal PCLK output in fig. 4 dropping from high to low is faster.
Moreover, the pulse signal generating circuit shown in fig. 5 is added with the seventh MOS transistor pch3 and the eighth MOS transistor pch4, which can effectively maintain the feedback signal nlck at a high level until the pulse width control signal n1 turns from low to high to turn on the second MOS transistor nch1, and the eighth MOS transistor pch4 is turned off, so that the level of the feedback signal nclk will fall rapidly after the pulse width control signal n1 turns from low to high, thereby avoiding the suspension state of the feedback signal in the signal generating process of the existing pulse signal generating circuit.
The pulse
The pulse
The pulse
Fig. 6 is a graph showing a comparison between the simulation effect of the pulse
Fig. 7 is a graph showing a comparison between the simulation effect of the pulse
As can be seen from fig. 6 and 7, the conventional pulse clock generation circuit is greatly affected by the load of the pulse clock signal PCLK0, whereas the pulse
The embodiment of the present invention further provides an integrated circuit, which includes the pulse
The integrated circuit according to the embodiment of the present invention has similar advantageous technical effects to the pulse
The embodiment of the invention also provides a pulse clock generating method. The pulse clock generation method comprises the following steps: receiving a clock input signal through a logic gate circuit, and outputting a gating signal under the driving of the clock input signal; receiving a gating signal through an inverter, and outputting a pulse clock signal under the driving of the gating signal; the gate control signal is received by the pulse width control circuit, and under the control of the gate control signal, the pulse width control signal is output and fed back to the logic gate circuit to adjust the pulse clock signal.
According to the pulse clock generation method provided by the embodiment of the invention, the starting point of the feedback loop is connected with the gating signal, and the gating signal is hardly influenced by the load change connected with the pulse clock signal, so that the gating signal is used as the starting point of the feedback signal and is not influenced by the load change connected with the pulse clock signal, namely, the level of the gating signal is kept stable, and further, the pulse clock signal output based on the gating signal is kept stable, so that the effect of stabilizing the pulse width of the output pulse clock signal is achieved.
In some embodiments, the pulse clock generation method of the embodiments of the present invention further includes: the feedback signal control circuit receives the pulse width control signal and the clock input signal, outputs a feedback signal under the control of the pulse width control signal and the clock input signal, and feeds the output feedback signal back to the logic gate circuit so as to stabilize the pulse width of the pulse clock signal.
The pulse clock generating circuit, the integrated circuit, and the pulse clock generating method according to the embodiments of the present invention are described in detail above. The pulse clock generating circuit, the integrated circuit and the pulse clock generating method according to the embodiments of the present invention are described herein by using specific examples, and the above descriptions of the embodiments are only used to help understanding the core idea of the present invention and are not intended to limit the present invention. It should be noted that, for those skilled in the art, various improvements and modifications can be made without departing from the spirit and principle of the present invention, and these improvements and modifications should fall within the scope of the appended claims.
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